CY62126DV30L-55BVXET

CY62126DV30L-55BVXET Datasheet

CY62126DV30

Part	Datasheet
CY62126DV30L-55BVXET	CY62126DV30L-55BVXET (pdf)

Related Parts	Information
CY62126DV30L-55BVXE	CY62126DV30L-55BVXE
CY62126DV30L-55ZSXET	CY62126DV30L-55ZSXET
CY62126DV30L-55ZSXE	CY62126DV30L-55ZSXE

PDF Datasheet Preview
CY62126DV30 1-Mbit 64K x 16 Static RAM • Very high speed 55 ns • Temperature Ranges Industrial to 85°C Automotive to 125°C • Wide voltage range 2.2V - 3.6V • Pin compatible with CY62126BV • Ultra-low active power Typical active current mA f = 1 MHz Typical active current 5 mA f = fMax 55 ns speed • Ultra-low standby power • Easy memory expansion with CE and OE features • Automatic power-down when deselected • Available in Pb-free and non Pb-free 48-ball VFBGA and 44-pin TSOP Type II packages Functional Description[1] The CY62126DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features Logic Block Diagram advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected CE HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE HIGH , outputs are disabled OE HIGH , both Byte High Enable and Byte Low Enable are disabled BHE, BLE HIGH or during a write operation CE LOW and WE LOW . Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A15 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A15 . Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes. ROW DECODER A11 A12 A13 A14 A15 SENSE AMPS DATA IN DRIVERS 64K x 16 RAM Array A2 A1 A0 COLUMN DECODER BHE WE CE OE BLE Note For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY62126DV30 Product Portfolio Product CY62126DV30L CY62126DV30LL Range Automotive Industrial Power Dissipation VCC Range V Min. Typ. Max. Speed ns Operating, ICC mA f = 1 MHz Typ.[2] Max. f = fMax Typ.[2] Max. Standby, ISB2 µA Typ.[2] Max. Pin Configurations[3, 4] 48-ball VFBGA Top View BLE OE A0 A1 A2 NC I/O8 BHE A3 A4 CE I/O0 I/O9 I/O10 A5 A6 I/O1 I/O2 Ordering Information Speed ns Ordering Code Package Diagram Package Type 55 CY62126DV30LL-55BVI 51-85150 48-ball Fine-Pitch Ball Grid Array 6 x 8 x 1 mm CY62126DV30LL-55BVXI 48-ball Fine-Pitch Ball Grid Array 6 x 8 x 1 mm Pb-free CY62126DV30LL-55ZI 51-85087 44-pin TSOP II CY62126DV30LL-55ZXI 44-pin TSOP II Pb-free CY62126DV30L-55BVXE 51-85150 48-ball Fine-Pitch Ball Grid Array 6 x 8 x 1 mm Pb-free CY62126DV30L-55ZSXE 51-85087 44-pin TSOP II Pb-free Please contact your local Cypress sales representative for availability of these parts Operating Range Industrial Automotive Page 9 of 12 [+] Feedback Package Diagrams TOP VIEW A1 CORNER 12 3 4 5 6 A B C D E F G H CY62126DV30 48-ball VFBGA 6 x 8 x 1 mm 51-85150 BOTTOM VIEW A1 CORNER M C M C A B Ø0.30±0.05 48X 6 54 3 2 1 A B C D E F G H B 0.15 4X C MAX. SEATING PLANE C 51-85150-D MAX. Page 10 of 12 [+] Feedback Package Diagrams continued CY62126DV30 44-pin TSOP II 51-85087 51-85087-A MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders. Page 11 of 12 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be JUI Changed from Preliminary to Final Add 70-ns speed, updated ordering information C 129002 08/29/03 CDY Changed ICC 1 MHz typ from mA to mA D 238050 See ECN AJU Fixed typo Changed tDBE from 70 ns to 35 ns E 316039 See ECN PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables Added Footnote #8 on page #4 Added Pb-free package ordering information on page # 9 Changed 44-pin TSOP-II package name from Z44 to ZS44 F 335861 See ECN SYT Added Temperature Ranges in the Features Section on Page # 1 Added Automotive Product Information for CY62126DV30-L for 55 ns Added ISB1 and ISB2 values for Automotive range of CY62126DV30-L for 55 ns Added Automotive Information for ICCDR in the Data Retention Characteristics table Added Pb-free packages in the ordering information Changed 44-pin TSOP-II package name from ZS44 to Z44 G 357256 See ECN PCI Added Pin Configuration and Package Diagram for 56-Lead QFN Package Updated Thermal Characteristics and Ordering Information Table Added Automotive Specs for IIX and IOZ in the DC Electrical Characteristics table on Page# 4 H 486789 See ECN VKN Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Removed 45 ns and 70ns Speed bin from Product offering Removed 56-pin QFN package Updated Ordering Information Table Page 12 of 12 [+] Feedback

PDF Datasheet Preview

CY62126DV30
1-Mbit 64K x 16 Static RAM
• Very high speed 55 ns
• Temperature Ranges Industrial to 85°C Automotive to 125°C
• Wide voltage range 2.2V - 3.6V
• Pin compatible with CY62126BV
• Ultra-low active power

Typical active current mA f = 1 MHz Typical active current 5 mA f = fMax 55 ns speed
• Ultra-low standby power
• Easy memory expansion with CE and OE features
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 48-ball VFBGA and 44-pin TSOP Type II packages

Functional Description[1]

The CY62126DV30 is a high-performance CMOS static RAM organized as 64K words by 16 bits. This device features

Logic Block Diagram
advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery Life in portable applications such as cellular telephones. The device also has an automatic power-down feature that significantly reduces power consumption by 90% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected CE HIGH . The input/output pins I/O0 through I/O15 are placed in a high-impedance state when deselected CE HIGH , outputs are disabled OE HIGH , both Byte High Enable and Byte Low Enable are disabled BHE, BLE HIGH or during a write operation CE LOW and WE LOW .

Writing to the device is accomplished by taking Chip Enable CE and Write Enable WE inputs LOW. If Byte Low Enable BLE is LOW, then data from I/O pins I/O0 through I/O7 , is written into the location specified on the address pins A0 through A15 . If Byte High Enable BHE is LOW, then data from I/O pins I/O8 through I/O15 is written into the location specified on the address pins A0 through A15 .

Reading from the device is accomplished by taking Chip Enable CE and Output Enable OE LOW while forcing the Write Enable WE HIGH. If Byte Low Enable BLE is LOW, then data from the memory location specified by the address pins will appear on I/O0 to I/O7. If Byte High Enable BHE is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of read and write modes.

ROW DECODER A11 A12 A13 A14 A15

SENSE AMPS

DATA IN DRIVERS
64K x 16

RAM Array

A2 A1 A0

COLUMN DECODER

BHE WE CE OE BLE

Note For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY62126DV30

Product Portfolio

Product CY62126DV30L CY62126DV30LL

Range Automotive Industrial

Power Dissipation

VCC Range V Min. Typ. Max.

Speed ns

Operating, ICC mA
f = 1 MHz Typ.[2] Max.
f = fMax Typ.[2] Max.

Standby, ISB2 µA

Typ.[2] Max.

Pin Configurations[3, 4]
48-ball VFBGA Top View

BLE OE A0 A1 A2 NC

I/O8 BHE A3 A4 CE I/O0

I/O9 I/O10 A5 A6 I/O1 I/O2
Ordering Information

Speed ns
Ordering Code

Package Diagram

Package Type
55 CY62126DV30LL-55BVI 51-85150 48-ball Fine-Pitch Ball Grid Array 6 x 8 x 1 mm

CY62126DV30LL-55BVXI
48-ball Fine-Pitch Ball Grid Array 6 x 8 x 1 mm Pb-free

CY62126DV30LL-55ZI
51-85087 44-pin TSOP II

CY62126DV30LL-55ZXI
44-pin TSOP II Pb-free

CY62126DV30L-55BVXE 51-85150 48-ball Fine-Pitch Ball Grid Array 6 x 8 x 1 mm Pb-free

CY62126DV30L-55ZSXE 51-85087 44-pin TSOP II Pb-free

Please contact your local Cypress sales representative for availability of these parts

Operating Range Industrial

Automotive

Page 9 of 12 [+] Feedback

Package Diagrams

TOP VIEW

A1 CORNER
12 3 4 5 6

A B C D E F G H

CY62126DV30
48-ball VFBGA 6 x 8 x 1 mm 51-85150

BOTTOM VIEW A1 CORNER

M C M C A B Ø0.30±0.05 48X
6 54 3 2 1

A B C D E F G H

B 0.15 4X

C MAX.

SEATING PLANE C
51-85150-*D

MAX.

Page 10 of 12 [+] Feedback

Package Diagrams continued

CY62126DV30
44-pin TSOP II 51-85087
51-85087-*A

MoBL is a registered trademark, and MoBL2 and More Battery Life are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 11 of 12

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
JUI Changed from Preliminary to Final Add 70-ns speed, updated ordering information
*C 129002 08/29/03 CDY Changed ICC 1 MHz typ from mA to mA
*D 238050 See ECN AJU Fixed typo Changed tDBE from 70 ns to 35 ns
*E 316039 See ECN PCI Added 45-ns Speed Bin in AC, DC and Ordering Information tables Added Footnote #8 on page #4 Added Pb-free package ordering information on page # 9 Changed 44-pin TSOP-II package name from Z44 to ZS44
*F 335861 See ECN SYT Added Temperature Ranges in the Features Section on Page # 1 Added Automotive Product Information for CY62126DV30-L for 55 ns Added ISB1 and ISB2 values for Automotive range of CY62126DV30-L for 55 ns Added Automotive Information for ICCDR in the Data Retention Characteristics table Added Pb-free packages in the ordering information Changed 44-pin TSOP-II package name from ZS44 to Z44
*G 357256 See ECN PCI Added Pin Configuration and Package Diagram for 56-Lead QFN Package Updated Thermal Characteristics and Ordering Information Table Added Automotive Specs for IIX and IOZ in the DC Electrical Characteristics table on Page# 4
*H 486789 See ECN VKN Changed the address of Cypress Semiconductor Corporation on Page #1 from “3901 North First Street” to “198 Champion Court” Removed 45 ns and 70ns Speed bin from Product offering Removed 56-pin QFN package Updated Ordering Information Table

Page 12 of 12 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY62126DV30L-55BVXET Datasheet file may be downloaded here without warranties.

Datasheet ID: CY62126DV30L-55BVXET 507801