CY3120R62

CY3120R62 Datasheet

CY3120

Part	Datasheet
CY3120R62	CY3120R62 (pdf)

PDF Datasheet Preview
CY3120 CPLD Development Software for PC • VHDL IEEE 1076 and 1164 and Verilog IEEE 1364 high-level language compilers with the following features Designs are portable across multiple devices and/or EDA environments Facilitates the use of industry-standard simulation and synthesis tools for board and system-level design Support for functions and libraries facilitating modular design methodology • IEEE Standard 1076 and 1164 VHDL synthesis supports Enumerated types Operator overloading For... Generate statements Integers • IEEE Standard 1364 Verilog synthesis supports Reduction and conditional operators Blocking and non-blocking procedural assignments While loops Integers • Several design entry methods support high-level and low-level design descriptions Behavioral VHDL and Verilog IF...THEN...ELSE; CASE... Boolean Aldec Active-HDL FSM graphical Finite State Machine editor Structural Verilog and VHDL Designs can include multiple entry methods but only one HDL language in a single design • UltraGen Synthesis and Fitting Technology Infers “modules” such as adders, comparators, etc., from behavioral descriptions and replaces them with circuits pre-optimized for the target device User selectable speed and/or area optimization on a block-by-block basis Perfect communication between synthesis and fitting Automatic selection of optimal flip-flop type D type/T type Automatic pin assignment • Ability to specify timing constraints for all of the Delta39K and PSI devices • Supports all Cypress Programmable Logic Devices PSI Programmable Serial Interface Delta39K Complex Programmable Logic Devices CPLDs Ultra37000 CPLDs FLASH370i CPLDs MAX340 CPLDs Industry standard PLDs 16V8, 20V8, 22V10 • VHDL and Verilog timing model output for use with third-party simulators • Timing simulation provided by Active-HDL Sim Release from Aldec Graphical waveform simulator Entry and modification of on-screen waveforms Ability to probe internal nodes Display of inputs, outputs, and high impedance Z signals in different colors Automatic clock and pulse creation Support for buses • Architecture Explorer and Dynamic Timing Analysis for PSI and Delta39K devices Graphical representation of exactly how your design will be implemented on your specific target device Zoom from the device level down to the macrocell level Product Ordering Information Product Code CY3120R62 Description Warp development system for PCs Warp includes: • CD-ROM with Warp, Aldec Active-HDL Sim and FSM, and on-line documentation Getting Started Manual, User’s Guide, HDL Reference Manual • VHDL for Programmable Logic textbook • Registration card Intel and Pentium are registered trademarks of Intel Corporation. Windows 95, Windows 98, Windows 2000, Windows NT and Windows XP are trademarks of Microsoft Corporation. Solaris is a trademark of Sun Microsystems Corporation. Active-HDL is a trademark of Aldec Incorporated. Warp is a registered trademark, and Warp Enterprise, UltraGen, PSI, Ultra37000, Delta39K, PSI, Programmable Serial Interface, MAX340, ISR, In-System Reprogrammable, and FLASH370i are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Page 7 of 8 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY3120 Document History Page Document Title CY3120 CPLD Development Software for PC Document Number 38-03049 Orig. of ECN NO. Issue Date Change Description of Change 109967 09/17/01 SZV Change from Spec number 38-00218 to 38-03049 111244 01/21/02 CNH Update product code, remove reference to Windows 95 116891 08/30/02 FSG Added timing constraints, Windows XP and Internet Access 127860 08/19/03 FSG Removed Quantum38K from all pages Page 8 of 8

PDF Datasheet Preview

CY3120

CPLD Development Software for PC
• VHDL IEEE 1076 and 1164 and Verilog IEEE 1364 high-level language compilers with the following features Designs are portable across multiple devices and/or EDA environments

Facilitates the use of industry-standard simulation and synthesis tools for board and system-level design

Support for functions and libraries facilitating modular design methodology
• IEEE Standard 1076 and 1164 VHDL synthesis supports Enumerated types

Operator overloading

For... Generate statements

Integers
• IEEE Standard 1364 Verilog synthesis supports

Reduction and conditional operators

Blocking and non-blocking procedural assignments

While loops

Integers
• Several design entry methods support high-level and
low-level design descriptions Behavioral VHDL and Verilog IF...THEN...ELSE;

CASE...

Boolean

Aldec Active-HDL FSM graphical Finite State Machine editor

Structural Verilog and VHDL

Designs can include multiple entry methods but only one HDL language in a single design
• UltraGen Synthesis and Fitting Technology Infers “modules” such as adders, comparators, etc., from behavioral descriptions and replaces them with circuits pre-optimized for the target device

User selectable speed and/or area optimization on a block-by-block basis

Perfect communication between synthesis and fitting

Automatic selection of optimal flip-flop type D type/T type

Automatic pin assignment
• Ability to specify timing constraints for all of the

Delta39K and PSI devices
• Supports all Cypress Programmable Logic Devices

PSI Programmable Serial Interface

Delta39K Complex Programmable Logic Devices CPLDs

Ultra37000 CPLDs

FLASH370i CPLDs

MAX340 CPLDs

Industry standard PLDs 16V8, 20V8, 22V10
• VHDL and Verilog timing model output for use with
third-party simulators
• Timing simulation provided by Active-HDL Sim

Release from Aldec Graphical waveform simulator

Entry and modification of on-screen waveforms

Ability to probe internal nodes

Display of inputs, outputs, and high impedance Z signals in different colors

Automatic clock and pulse creation

Support for buses
• Architecture Explorer and Dynamic Timing Analysis for

PSI and Delta39K devices Graphical representation of exactly how your design
will be implemented on your specific target device

Zoom from the device level down to the macrocell level
Product Ordering Information

Product Code CY3120R62

Description Warp development system for PCs

Warp includes:
• CD-ROM with Warp, Aldec Active-HDL Sim and FSM, and on-line documentation Getting Started Manual, User’s Guide, HDL Reference Manual
• VHDL for Programmable Logic textbook
• Registration card

Intel and Pentium are registered trademarks of Intel Corporation. Windows 95, Windows 98, Windows 2000, Windows NT and Windows XP are trademarks of Microsoft Corporation. Solaris is a trademark of Sun Microsystems Corporation. Active-HDL is a trademark of Aldec Incorporated. Warp is a registered trademark, and Warp Enterprise, UltraGen, PSI, Ultra37000, Delta39K, PSI, Programmable Serial Interface, MAX340, ISR, In-System Reprogrammable, and FLASH370i are trademarks, of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.

Page 7 of 8

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

CY3120

Document History Page

Document Title CY3120 CPLD Development Software for PC Document Number 38-03049

Orig. of ECN NO. Issue Date Change Description of Change
109967 09/17/01

SZV Change from Spec number 38-00218 to 38-03049
111244 01/21/02 CNH Update product code, remove reference to Windows 95
116891 08/30/02

FSG Added timing constraints, Windows XP and Internet Access
127860 08/19/03

FSG Removed Quantum38K from all pages

Page 8 of 8

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY3120R62 Datasheet file may be downloaded here without warranties.

Datasheet ID: CY3120R62 507769