CY2DP818ZC

CY2DP818ZC Datasheet

CY2DP818

Part	Datasheet
CY2DP818ZC	CY2DP818ZC (pdf)

PDF Datasheet Preview
CY2DP818 1:8 Clock Fanout Buffer • Low-voltage operation VDD = 3.3V • 1:8 fanout • Operation to 350 MHz • Single input configurable for LVDS, LVPECL, or LVTTL • 8 pair of LVPECL outputs • Drives a 50 ohm load • Low input capacitance • Low output skew • Low propagation delay tpd = 4 ns, typical • Commercial and Industrial temperature ranges • 38-Pin TSSOP Package Logic Block Diagram INPUT LVPECL / LVDS / LVTTL INPUT A INPUT B InConfig The Cypress CY2DP818 fanout buffer features a single LVDS or a single ended LVTTL compatible input and eight LVPECL output pairs. Designed for data-communications clock management applications, the large fanout from a single input reduces loading on the input clock. The CY2DP818 is ideal for both level translations from single ended to LVPECL and/or for the distribution of LVPECL based clock signals. The Cypress CY2DP818 has configurable input functions. The input is user configurable via the InConfig pin for single ended or differential input. Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B Q5A Q5B Q6A Q6B Q7A Q7B Q8A Q8B OUTPUT LVPECL • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY2DP818 Pinouts Pin Configuration Figure 38-Pin TSSOP GND 1 VDD 2 VDD 3 VDD 4 VDD 5 VDD 6 InConfig 7 VDD 8 GND 9 INPUT A 10 INPUT B 11 GND 12 VDD 13 VDD 14 VDD 15 VDD 16 VDD 17 GND 18 GND 19 CY2DP818 38 GND 37 Q1A 36 Q1B 35 Q2A 34 Q2B 33 Q3A 32 Q3B 31 Q4A 30 Q4B 29 VDD 28 Q5A 27 Q5B 26 Q6A 25 Q6B 24 Q7A 23 Q7B 22 Q8A 21 Q8B 20 GND Pin Description Pin Number Pin Name 1, 9, 12, 18, 19, 20, 38 2, 3, 4, 5, 6, 8, 13, 14, 15, 16, 17, 29 VDD 10, 11 Input A, Input B 37, 36, 35, 34, 33, 32, 31, 30, 28, 27, 26, 25, 24, 23, 22, 21 Q1 A,B , Q2 A,B Q3 A,B , Q4 A,B Q5 A,B , Q6 A,B Q7 A,B , Q8 A,B Ordering Information Part Number CY2DP818ZI CY2DP818ZIT CY2DP818ZC CY2DP818ZCT Pb-Free CY2DP818ZXI CY2DP818ZXIT CY2DP818ZXC CY2DP818ZXCT Package Type 38-pin TSSOP 38-pin and Reel 38-pin TSSOP 38-pin and Reel 38-pin TSSOP 38-pin and Reel 38-pin TSSOP 38-pin and Reel Product Flow Industrial, to 85°C Industrial, to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Industrial, to 85°C Industrial, to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C Package Drawing and Dimensions Figure 38-Pin TSSOP mm Body Z38 and ZZ38 51-85151-*A Page 6 of 7 [+] Feedback CY2DP818 Document History Page Document Title CY2DP818 1:8 Clock Fanout Buffer Document Number 38-07061 Orig. of Submission Change Description of Change 107086 06/07/01 IKA New Data Sheet 115913 07/11/02 CTK IC, VCM, VOC, Rise/Fall Time Fmax 20 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. PSoC Designer , Programmable System-on-Chip , and PSoC Express are trademarks and is a registered trademark of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 7 of 7 [+] Feedback

PDF Datasheet Preview

CY2DP818
1:8 Clock Fanout Buffer
• Low-voltage operation VDD = 3.3V
• 1:8 fanout
• Operation to 350 MHz
• Single input configurable for LVDS, LVPECL, or LVTTL
• 8 pair of LVPECL outputs
• Drives a 50 ohm load
• Low input capacitance
• Low output skew
• Low propagation delay tpd = 4 ns, typical
• Commercial and Industrial temperature ranges
• 38-Pin TSSOP Package

Logic Block Diagram

INPUT

LVPECL / LVDS / LVTTL

INPUT A INPUT B

InConfig

The Cypress CY2DP818 fanout buffer features a single LVDS or a single ended LVTTL compatible input and eight LVPECL output pairs. Designed for data-communications clock management applications, the large fanout from a single input reduces loading on the input clock. The CY2DP818 is ideal for both level translations from single ended to LVPECL and/or for the distribution of LVPECL based clock signals. The Cypress CY2DP818 has configurable input functions. The input is user configurable via the InConfig pin for single ended or differential input.

Q1A Q1B

Q2A Q2B

Q3A Q3B

Q4A Q4B

Q5A Q5B

Q6A Q6B

Q7A Q7B

Q8A Q8B

OUTPUT

LVPECL
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY2DP818

Pinouts Pin Configuration

Figure 38-Pin TSSOP

GND 1 VDD 2 VDD 3 VDD 4 VDD 5 VDD 6 InConfig 7 VDD 8 GND 9 INPUT A 10 INPUT B 11 GND 12 VDD 13 VDD 14 VDD 15 VDD 16 VDD 17 GND 18 GND 19

CY2DP818
38 GND 37 Q1A
36 Q1B
35 Q2A
34 Q2B 33 Q3A 32 Q3B 31 Q4A 30 Q4B 29 VDD 28 Q5A 27 Q5B 26 Q6A 25 Q6B 24 Q7A 23 Q7B 22 Q8A
21 Q8B
20 GND

Pin Description

Pin Number

Pin Name
1, 9, 12, 18, 19, 20, 38
2, 3, 4, 5, 6, 8, 13, 14, 15, 16, 17, 29 VDD
10, 11

Input A, Input B
37, 36, 35, 34, 33, 32, 31, 30, 28, 27, 26, 25, 24, 23, 22, 21

Q1 A,B , Q2 A,B Q3 A,B , Q4 A,B Q5 A,B , Q6 A,B Q7 A,B , Q8 A,B
Ordering Information

Part Number CY2DP818ZI CY2DP818ZIT CY2DP818ZC CY2DP818ZCT Pb-Free CY2DP818ZXI CY2DP818ZXIT CY2DP818ZXC CY2DP818ZXCT

Package Type 38-pin TSSOP 38-pin and Reel 38-pin TSSOP 38-pin and Reel
38-pin TSSOP 38-pin and Reel 38-pin TSSOP 38-pin and Reel

Product Flow Industrial, to 85°C Industrial, to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C

Industrial, to 85°C Industrial, to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C

Package Drawing and Dimensions

Figure 38-Pin TSSOP mm Body Z38 and ZZ38
51-85151-*A

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CY2DP818

Document History Page

Document Title CY2DP818 1:8 Clock Fanout Buffer Document Number 38-07061

Orig. of Submission

Change

Description of Change
107086 06/07/01

IKA New Data Sheet
115913 07/11/02

CTK IC, VCM, VOC, Rise/Fall Time Fmax 20
Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

Products PSoC Clocks & Buffers Wireless Memories Image Sensors
psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

PSoC Designer , Programmable System-on-Chip , and PSoC Express are trademarks and is a registered trademark of Cypress Semiconductor Corp. All products and company names mentioned in this document may be the trademarks of their respective holders.

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Datasheet ID: CY2DP818ZC 507752