CY2DP818ZXC-2

CY2DP818ZXC-2 Datasheet


CY2DP818-2

Part Datasheet
CY2DP818ZXC-2 CY2DP818ZXC-2 CY2DP818ZXC-2 (pdf)
Related Parts Information
CY2DP818ZXI-2 CY2DP818ZXI-2 CY2DP818ZXI-2
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CY2DP818-2
1:8 Clock Fanout Buffer
• Low voltage operation VDD = 3.3V
• 1:8 fanout
• Single-input configurable for LVDS, LVPECL, or LVTTL
• 8 pairs of LVPECL outputs with enable and disable
• Drives a 50 ohm load
• Low input capacitance
• Low output skew
• Low propagation delay typical tpd < 4 ns
• Industrial versions available
• Package available include TSSOP
• Does not exceed Bellcore standards
• Operation up to 350 MHz and 700 Mbps

This Cypress series of network circuits is produced using advanced micron CMOS technology, achieving the industry’s fastest logic.

The Cypress CY2DP818-2 fanout buffer features a single LVDS or a single-ended LVTTL compatible input and eight LVPECL output pairs.

Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock.

The CY2DP818-2 is ideal for both level translations from single-ended to LVPECL and for the distribution of LVPECL based clock signals.

The Cypress CY2DP818-2 has configurable input functions. The input is user configurable through the Inconfig pin for single ended or differential input.

Logic Block Diagram

EN1 Q1A Q1B

INPUT

LVPECL / LVDS / LVTTL EN4

INPUT A INPUT B

InConfig

Q2A Q2B

Q3A Q3B

Q4A Q4B

Q5A Q5B

Q6A Q6B

Q8A Q8B

OUTPUT

LVPECL
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CY2DP818-2

Pin Configuration

Figure Pin Diagram - 38-Pin TSSOP

GND 1 VDD 2 EN1 3 EN2 4 EN3 5 EN4 6 InConfig 7 VDD 8 GND 9 INPUT A 10 INPUT B 11 GND 12 VDD 13 EN5 14 EN6 15 EN7 16 VDD 17 GND 18 GND 19

CY2DP818-2
38 GND 37 Q1A
36 Q1B
35 Q2A 34 Q2B 33 Q3A 32 Q3B 31 Q4A 30 Q4B 29 VDD 28 Q5A 27 Q5B 26 Q6A 25 Q6B 24 Q7A 23 Q7B 22 Q8A
21 Q8B 20 GND

Pin Description

Pin Number 1, 9,12,18,19,20,38 2,8,13,29,17 3,4,5,6,14,15,16

Pin Name GND VDD EN 1:7
10,11
37, 36,35,34, 33,32,31, 30, 28,27,26,25, 24,23,22,21 7

Input A, Input B

Q1 A,B , Q2 A,B Q3 A,B , Q4 A,B Q5 A,B , Q6 A,B Q7 A,B , Q8 A,B InConfig

Pin Standard Interface POWER LVTTL/LVCMOS
Ordering Information

Part Number CY2DP818ZI-2 CY2DP818ZI-2T CY2DP818ZC-2 CY2DP818ZC-2T Pb Free Devices CY2DP818ZXI-2 CY2DP818ZXI-2T CY2DP818ZXC-2 CY2DP818ZXC-2T

Note LVPECL or LVDS differential input value.

Package Type 38-Pin TSSOP 38-Pin and Reel 38-Pin TSSOP 38-Pin and Reel
38-Pin TSSOP 38-Pin and Reel 38-Pin TSSOP 38-Pin and Reel

Product Flow Industrial, to 85°C Industrial, to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C

Industrial, to 85°C Industrial, to 85°C Commercial, 0°C to 70°C Commercial, 0°C to 70°C

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Package Drawing and Dimensions

Figure 38-Pin TSSOP mm Body Z38

CY2DP818-2
51-85151-*A

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CY2DP818-2

Document History Page

Document Title CY2DP818-2 1:8 Clock Fanout Buffer Document Number 38-07588

ECN No.

Submission Date

Orig. of Change

Description of Change
129879
11/07/03

RGL New Data Sheet
2595534 10/23/08 CXQ/PYRS Removed “Preliminary”, added Pb-free devices to Ordering Information

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

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Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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Datasheet ID: CY2DP818ZXC-2 507751