CY2DL814SXIT

CY2DL814SXIT Datasheet

ComLink Series CY2DL814

Part	Datasheet
CY2DL814SXIT	CY2DL814SXIT (pdf)

Related Parts	Information
CY2DL814SXC	CY2DL814SXC
CY2DL814SXCT	CY2DL814SXCT
CY2DL814SXI	CY2DL814SXI
CY2DL814ZXC	CY2DL814ZXC
CY2DL814ZXCT	CY2DL814ZXCT
CY2DL814ZXI	CY2DL814ZXI
CY2DL814ZXIT	CY2DL814ZXIT

PDF Datasheet Preview
• Low-voltage operation • VDD = 3.3V • 1:4 Fanout • Single-input configurable for LVDS, LVPECL, or LVTTL Four differential pairs of LVDS outputs • Drives 50- or 100-ohm load selectable • Low input capacitance • 85 ps typical output-to-output skew • <4 ns typical propagation delay • Does not exceed Bellcore standards • Operation at 350 MHz 700 Mbps • Industrial versions available • Packages available include TSSOP/SOIC ComLink Series CY2DL814 1:4 Clock Fanout Buffer The Cypress CY2 series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic. The Cypress CY2DL814 fanout buffer features a single LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS output pairs. Designed for data-communication clock management applications, the fanout from a single input reduces loading on the input clock. The CY2DL814 is ideal for both level translations from single ended to LVDS and/or for the distribution of LVDS-based clock signals. The Cypress CY2DL814 has configurable input and output functions. The input can be selectable for LVPECL/LVTTL or LVDS signals while the output driver’s support standard and high drive LVDS. Drive either a 50-ohm or 100-ohm line with a single part number/device. Block Diagram EN1 EN2 IN+ IN- LVDS / LVPECL / LVTTL CONFIG CNTRL Pin Configuration Q1A Q1B Q2A Q2B Q3A Q3B Q4A Q4B OUTPUT LVDS EN1 1 CONFIG 2 CNTRL 3 VDD 4 GND 5 IN+ 6 IN- 7 EN2 8 CY2DL814 16 Q1A 15 Q1B 14 Q2A 13 Q2B 12 Q3A 11 Q3B 10 Q4A 9 Q4B 16-pin TSSOP/SOIC Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 ComLink Series CY2DL814 Pin Description Pin Number 6,7 Pin Name IN+, CNTRL CONFIG EN1, EN2 16,15,14,13 12,11,10,9 Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B Maximum Ratings[1, 2] Pin Standard Interface Configurable LVTTL/LVCMOS LVTTL/LVCMOS Ordering Information Figure LVPECL or LVDS Differential Input Value[8] Package Type Product Flow CY2DL814ZI 16-pin TSSOP Industrial, to 85°C CY2DL814ZIT 16-pin and Reel Industrial, to 85°C CY2DL814SI 16-pin SOIC Industrial, to 85°C CY2DL814SIT 16-pin and Reel Industrial, to 85°C CY2DL814ZC 16-pin TSSOP Commercial, 0°C to 70 °C CY2DL814ZCT 16-pin and Reel Commercial, 0°C to 70 °C CY2DL814SC 16-pin SOIC Commercial, 0°C to 70 °C CY2DL814SCT 16-pin and Reel Commercial, 0°C to 70 °C Lead-free CY2DL814ZXI 16-pin TSSOP Industrial, to 85°C CY2DL814ZXIT 16-pin and Reel Industrial, to 85°C CY2DL814SXI 16-pin SOIC Industrial, to 85°C CY2DL814SXIT 16-pin and Reel Industrial, to 85°C

PDF Datasheet Preview

• Low-voltage operation
• VDD = 3.3V
• 1:4 Fanout
• Single-input configurable for

LVDS, LVPECL, or LVTTL Four differential pairs of LVDS outputs
• Drives 50- or 100-ohm load selectable
• Low input capacitance
• 85 ps typical output-to-output skew
• <4 ns typical propagation delay
• Does not exceed Bellcore standards
• Operation at 350 MHz 700 Mbps
• Industrial versions available
• Packages available include TSSOP/SOIC

ComLink Series CY2DL814
1:4 Clock Fanout Buffer

The Cypress CY2 series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic. The Cypress CY2DL814 fanout buffer features a single LVDS-, LVPECL-, or LVTTL-compatible input and four LVDS output pairs. Designed for data-communication clock management applications, the fanout from a single input reduces loading on the input clock. The CY2DL814 is ideal for both level translations from single ended to LVDS and/or for the distribution of LVDS-based clock signals. The Cypress CY2DL814 has configurable input and output functions. The input can be selectable for LVPECL/LVTTL or LVDS signals while the output driver’s support standard and high drive LVDS. Drive either a 50-ohm or 100-ohm line with a single part number/device.

Block Diagram

EN1 EN2

IN+ IN-

LVDS / LVPECL /

LVTTL CONFIG

CNTRL

Pin Configuration

Q1A Q1B

Q2A Q2B

Q3A Q3B

Q4A Q4B

OUTPUT

LVDS

EN1 1 CONFIG 2 CNTRL 3

VDD 4 GND 5

IN+ 6 IN- 7

EN2 8

CY2DL814
16 Q1A 15 Q1B 14 Q2A 13 Q2B 12 Q3A 11 Q3B
10 Q4A 9 Q4B
16-pin TSSOP/SOIC

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

ComLink Series CY2DL814

Pin Description

Pin Number 6,7

Pin Name IN+,

CNTRL

CONFIG

EN1, EN2
16,15,14,13 12,11,10,9

Q1A, Q1B, Q2A, Q2B,

Q3A, Q3B, Q4A, Q4B

Maximum Ratings[1, 2]

Pin Standard Interface Configurable

LVTTL/LVCMOS

LVTTL/LVCMOS
Ordering Information

Figure LVPECL or LVDS Differential Input Value[8]

Package Type

Product Flow

CY2DL814ZI
16-pin TSSOP

Industrial, to 85°C

CY2DL814ZIT
16-pin and Reel

Industrial, to 85°C

CY2DL814SI
16-pin SOIC

Industrial, to 85°C

CY2DL814SIT
16-pin and Reel

Industrial, to 85°C

CY2DL814ZC
16-pin TSSOP

Commercial, 0°C to 70 °C

CY2DL814ZCT
16-pin and Reel

Commercial, 0°C to 70 °C

CY2DL814SC
16-pin SOIC

Commercial, 0°C to 70 °C

CY2DL814SCT
16-pin and Reel

Commercial, 0°C to 70 °C

Lead-free

CY2DL814ZXI
16-pin TSSOP

Industrial, to 85°C

CY2DL814ZXIT
16-pin and Reel

Industrial, to 85°C

CY2DL814SXI
16-pin SOIC

Industrial, to 85°C

CY2DL814SXIT
16-pin and Reel

Industrial, to 85°C

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY2DL814SXIT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY2DL814SXIT 507750