74ABT16952CMTDX

74ABT16952CMTDX Datasheet

74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs

Part	Datasheet
74ABT16952CMTDX	74ABT16952CMTDX (pdf)

Related Parts	Information
74ABT16952CMTD	74ABT16952CMTD
74ABT16952CSSC	74ABT16952CSSC
74ABT16952CSSCX	74ABT16952CSSCX

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74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs 74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs The ABT16952 is a 16-bit registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-STATE output enable signals are provided for each register. The output pins are guaranteed to source 32 mA and to sink 64 mA. s Separate clock, clock enable and 3-STATE output enable provided for each register s A and B output sink capability of 64 mA source capability of 32 mA s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability Ordering Code: Order Number Package Number Package Description 74ABT16952CSSC MS56A 56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide 74ABT16952CMTD MTD56 56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code. Pin Descriptions Connection Diagram Pin Names CPABn, CPBAn CEAn, CEBn OEABn, OEBAn Description Data Register A Inputs/ B-Register 3-STATE Outputs Data Register B Inputs/ A-Register 3-STATE Outputs Clock Pulse Inputs Clock Enable Output Enable Inputs Output Control Internal Q Output Function Disable Outputs Enable Outputs Register Function Table Applies to A or B Register Inputs Internal Q Function H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial NC Hold Data L Load Data = HIGH Impedance = LOW-to-HIGH Transition NC = No Change 2001 Fairchild Semiconductor Corporation DS011647 74ABT16952 Block Diagram n for either byte 1 or byte 2 74ABT16952 Absolute Maximum Ratings Note 1 Recommended Operating Storage Temperature −65°C to +150°C Conditions Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage Note 2 Input Current Note 2 Voltage Applied to Any Output in the Disable or Power-Off State −55°C to +125°C −55°C to +150°C −0.5V to +7.0V −0.5V to +7.0V −30 mA to mA −0.5V to +5.5V Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate Data Input Enable Input Clock Input −40°C to +85°C +4.5V to +5.5V 50 mV/ns 20 mV/ns 100 mV/ns in the HIGH State Current Applied to Output −0.5V to VCC in LOW State Max DC Latchup Source Current Over Voltage Latchup I/O

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74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs
74ABT16952 16-Bit Registered Transceiver with 3-STATE Outputs

The ABT16952 is a 16-bit registered transceiver. Two 8-bit back to back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-STATE output enable signals are provided for each register. The output pins are guaranteed to source 32 mA and to sink 64 mA.
s Separate clock, clock enable and 3-STATE output enable provided for each register
s A and B output sink capability of 64 mA source capability of 32 mA
s Guaranteed latchup protection s High impedance glitch free bus loading during entire
power up and power down cycle s Nondestructive hot insertion capability
Ordering Code:

Order Number Package Number

Package Description
74ABT16952CSSC

MS56A
56-Lead Shrink Small Outline Package SSOP , JEDEC MO-118, Wide
74ABT16952CMTD

MTD56
56-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the letter suffix “X” to the ordering code.

Pin Descriptions

Connection Diagram

Pin Names

CPABn, CPBAn CEAn, CEBn OEABn, OEBAn

Description Data Register A Inputs/ B-Register 3-STATE Outputs Data Register B Inputs/ A-Register 3-STATE Outputs Clock Pulse Inputs Clock Enable Output Enable Inputs

Output Control

Internal Q

Output

Function

Disable Outputs

Enable Outputs

Register Function Table

Applies to A or B Register Inputs

Internal Q

Function

H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial

NC Hold Data

L Load Data
= HIGH Impedance = LOW-to-HIGH Transition NC = No Change
2001 Fairchild Semiconductor Corporation DS011647
74ABT16952

Block Diagram
n for either byte 1 or byte 2
74ABT16952

Absolute Maximum Ratings Note 1

Recommended Operating

Storage Temperature
−65°C to +150°C Conditions

Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage Note 2 Input Current Note 2 Voltage Applied to Any Output
in the Disable or Power-Off State
−55°C to +125°C −55°C to +150°C
−0.5V to +7.0V −0.5V to +7.0V −30 mA to mA
−0.5V to +5.5V

Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate

Data Input Enable Input Clock Input
−40°C to +85°C +4.5V to +5.5V
50 mV/ns 20 mV/ns 100 mV/ns
in the HIGH State Current Applied to Output
−0.5V to VCC
in LOW State Max DC Latchup Source Current Over Voltage Latchup I/O

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Datasheet ID: 74ABT16952CMTDX 513043