CY28329
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CY28329ZXC (pdf) |
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CY28329ZXCT |
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CY28329OXC |
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CY28329OXCT |
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CY28329 133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs • Multiple output clocks at different frequencies Four pairs of differential CPU outputs, up to 133 MHz Ten synchronous PCI clocks, three free-running Six 3V66 clocks Two 48-MHz clocks One reference clock at MHz One VCH clock • Spread Spectrum clocking down spread • Power-down features PCI_STOP#, PD# • Three Select inputs Mode select & IC Frequency Select • OE and Test Mode support • 56-pin SSOP package and 56-pin TSSOP package • Motherboard clock generator Support Multiple CPUs and a chipset Support for PCI slots and chipset Supports AGP and Hub Link Supports USB host controller and graphic controller Supports ISA slots and I/O chip • Enables reduction of EMI and overall system cost • Enables ACPI compliant designs • Supports up to four CPU clock frequencies • Enables ATE and “bed of nails” testing • Widely available, standard package enables lower cost Logic Block Diagram XTAL PLL Ref Freq Mult0 S1:2 VTTPWRGD# PLL 1 Divider Network Gate PCI_STOP# PD# Stop Clock Control PLL 2 SDATA SCLK SMBus Logic VDD_REF REF VDD_CPU CPU[0:3] CPU[0:3]# VDD_PCI PCI_F[0:2] PCI0:6 VDD_3V66 3V66_0 3V66_[2:]4/ 66BUFF0:2 3V66_5/ 66IN VDD_48MHz USB 48MHz DOT 48MHz VCH_CLK/ 3V66_1 Pin Configurations SSOP and TSSOP Top View VDD_REF 1 XTAL_IN 2 XTAL_OUT 3 56 REF 55 S1 54 CPU3 GND_REF 4 53 CPU3# PCI_F0 5 PCI_F1 6 PCI_F2 7 VDD_PCI 8 GND_PCI 9 PCI0 10 PCI1 11 PCI2 12 PCI3 13 52 CPU0 51 CPU0# 50 VDD_CPU 49 CPU1 48 CPU1# 47 GND_CPU 46 VDD_CPU 45 CPU2 44 CPU2# CY28329 VDD_PCI 14 GND_PCI 15 PCI4 16 PCI5 17 PCI6 18 VDD_3V66 19 GND_3V66 20 66BUFF0/3V66_2 21 66BUFF1/3V66_3 22 66BUFF2/3V66_4 23 66IN/3V66_5 24 PD# 25 VDD_CORE 26 GND_CORE 27 VTTPWRGD# 28 Ordering Information Ordering Code Standard CY28329PVC CY28329PVCT CY28329ZC CY28329ZCT Lead-free CY28329OXC CY28329OXCT CY28329ZXC CY28329ZXCT Package Type Operating Range 56-Pin Small Shrunk Outline Package SSOP Commercial 56-Pin Small Shrunk Outline Package SSOP - Tape and Reel Commercial 56-Pin Thin Small Shrunk Outline Package TSSOP Commercial 56-Pin Thin Small Shrunk Outline Package TSSOP - Tape and Reel Commercial 56-Pin Small Shrunk Outline Package SSOP 56-Pin Small Shrunk Outline Package SSOP -Tape and Reel 56-Pin Thin Small Shrunk Outline Package TSSOP 56-Pin Thin Small Shrunk Outline Package TSSOP Commercial Page 15 of 17 Package Diagrams 56-Lead Shrunk Small Outline Package O56 CY28329 51-85062-*C 56-Lead Thin Shrunk Small Outline Package, Type II 6 mm x 12 mm Z56 DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. MAX. MAX. GAUGE PLANE SEATING PLANE 0° -8° 51-85060-*C Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 16 of 17 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY28329 Document History Page Document Title CY28329 133-MHz Spread Spectrum Clock Synthesizer/Driver with Differential CPU Outputs Document Number 38-07040 Description of Change 115133 04/26/02 DSG Changed from Spec number 38-01147 to 38-07040 Preliminary to Final *A 122733 12/14/02 RBI Added power-up requirements to operating conditions information. *B 127128 06/13/03 Added t10 timing AC specification. Added Notes 10 and Added VDD to POR diagram. Added pull-up resistor to PD# in Layout example.Verified I2C default values Added “Use an external to pull-up resistor” to Pin 25 description. |
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