CY26049ZXC-36

CY26049ZXC-36 Datasheet


CY26049-36

Part Datasheet
CY26049ZXC-36 CY26049ZXC-36 CY26049ZXC-36 (pdf)
Related Parts Information
CY26049ZXC-36T CY26049ZXC-36T CY26049ZXC-36T
CY26049ZXI-36 CY26049ZXI-36 CY26049ZXI-36
CY26049ZXI-36T CY26049ZXI-36T CY26049ZXI-36T
PDF Datasheet Preview
CY26049-36

FailSafe PacketClock Global Communications Clock Generator
• Fully integrated phase-locked loop PLL
• output
• PLL driven by a crystal oscillator that is phase aligned
with external reference
• Output frequencies selectable and/or programmed to
standard communication frequencies
• Low-jitter, high-accuracy outputs
• Commercial and Industrial operation
• 3.3V ± 5% operation
• 16-lead TSSOP
• Integrated high-performance PLL tailored for telecommunications frequency synthesis eliminates the need for external loop filter components
• When reference is in range, SAFE pin is driven high.
• When reference is off, DCXO maintains clock outputs. SAFE pin is low.
• DCXO maintains continuous operation should the input reference clock fail
• Glitch-free transition simplifies system design
• Selectable output clock rates include T1/DS1, E1, T3/DS3, E3, and OC-3.
• Works with commonly available, low-cost 18.432-MHz crystal
• Zero-ppm error for all output frequencies
• Performance guaranteed for applications that require an extended temperature range
• Compatible across industry standard design platforms
• Industry standard package with x mm2 footprint
and a height profile of just mm.

Logic Block Diagram
external pullable crystal MHz

XOUT

Input reference typical 8 kHz

ICLK

FAILSAFETM CONTROL

DIGITAL

CONTROLLED CRYSTAL

OSCILLATOR

PHASE LOCKED

LOOP

OUTPUT DIVIDERS

CLK/2

FS[3:0] frequency select

Pin Configuration

SAFE High=ICLK detected

CY26049-36 16-pin TSSOP

Top View

ICLK 1 8K 2

FS1 3 FS2 4 VDD 5 VSS 6 CLK/2 7 XIN 8
16 NC 15 CLK 14 FS0 13 FS3 12 VDD 11 VSS 10 SAFE 9 XOUT

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

CY26049-36

Pin Definitions

Pin Name Pin Number
Ordering Information
Ordering Code CY26049ZC-36 CY26049ZC-36T CY26049ZI-36 CY26049ZI-36T Lead Free CY26049ZXC-36 CY26049ZXC-36T CY26049ZXI-36 CY26049ZXI-36T

Package Diagram

Package Type 16-lead TSSOP 16-lead and Reel 16-lead TSSOP 16-lead and Reel
16-lead TSSOP 16-lead and Reel 16-lead TSSOP 16-lead and Reel

Operating Temperature Range Commercial 0 to 70°C Commercial 0 to 70°C Industrial to 85°C Industrial to 85°C

Commercial 0 to 70°C Commercial 0 to 70°C Industrial to 85°C Industrial to 85°C
16-lead TSSOP MM Body Z16.173

PIN 1 ID

DIMENSIONS IN MM[INCHES] MIN. MAX.

REFERENCE JEDEC MO-153 PACKAGE WEIGHT gms

PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG.

BSC.

MAX.

SEATING PLANE

GAUGE PLANE
0° -8°
51-85091-*A

FailSafe and PacketClock are trademarks of Cypress Semiconductor. All product and company names mentioned in this document are the trademarks of their respective holders.

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Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY26049-36

Document History Page

Document Title CY26049-36 FailSafe PacketClock Global Communications Clock Generator Document Number 38-07415

Description of Change
114749 08/08/02 CKN New Data Sheet
*A 120067 01/06/03 CKN Changed “FailSafe is a trademark of Silicon Graphics, Inc.” to read “FailSafe is a trademark of Cypress Semiconductor”
*B 128000 07/15/03

IJA Changed Benefits to read “When reference is in range, SAFE pin is driven high” Changed first sentence to “CY26049 is a FailSafe frequency synthesizer with a reference clock input and three clock outputs” Changed title from Global Communications Clocks” to Global Communications Clock Generator” Changed definitions in Pin Description Table Replaced format for Absolute Maximum Conditions Replaced Recommended Pullable Crystal Specifications table Added tpu to Recommended Operating Conditions Added IIH and IIL to DC Electrical Specifications Replaced AC Electrical Specifications from Cy26049-16 data sheet Changed Voltage and Timing Definitions to match CY2410 data sheet Moved Package Diagram to end of data sheet
*C 244412 See ECN RGL Spec. tER I Input Edge Rate in the Recommended Operating Conditions Table Added Lead Free Devices

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Datasheet ID: CY26049ZXC-36 507714