CY26049ZXC-22T

CY26049ZXC-22T Datasheet

CY26049-22

Part	Datasheet
CY26049ZXC-22T	CY26049ZXC-22T (pdf)

Related Parts	Information
CY26049ZXC-22	CY26049ZXC-22

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CY26049-22 FailSafe PacketClock Global Communications Clock Generator • Fully integrated phase-locked loop PLL • output • PLL driven by a crystal oscillator that is phase aligned with external reference • 100-MHz output from 10-MHz input • Low-jitter, high-accuracy outputs • 3.3V ± 5% operation • 16-lead TSSOP • Integrated high-performance PLL tailored for telecommunications frequency synthesis eliminates the need for external loop filter components • When reference is off, DCXO maintains clock outputs and SAFE pin indicates FailSafe conditions • DCXO maintains continuous operation should the input reference clock fail • Glitch-free transition simplifies system design • Works with commonly available, low-cost 10-MHz crystal • Zero-ppm error for all output frequencies • Compatible across industry standard design platforms • Industry standard package with x mm2 footprint and a height profile of just mm Logic Block Diagram input reference 10M Hz IC L K external pullable crystal 10M Hz XOUT F A ILS A F ETM CONTROL D IG IT A L CONTROLLED CRYSTAL O SCILLATOR PHASE LOCKED LOOP OUTPUT D IV ID E R CLKA 100M H z SAFE ICLK detected Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Pin Configuration CY26049-22 16-pin TSSOP Top View ICLK 1 NC 2 NC 3 NC 4 VDD 5 VSS 6 NC 7 XIN 8 16 NC 15 CLKA 14 NC 13 NC 12 VDD 11 VSS 10 SAFE 9 XOUT Pin Description Pin Number Pin Name Pin Description ICLK Reference Input Clock 10 MHz. NC No Connect. NC No Connect. NC No Connect. VDD Voltage Supply 3.3V. VSS Ground. NC No Connect Ordering Information Ordering Code Lead-Free CY26049ZXC-22 CY26049ZXC-22T 10MHz Package Type 16-lead TSSOP 16-lead and Reel Operating Temperature Range Commercial 0° to 70°C Commercial 0° to 70°C Page 4 of 6 Package Drawing and Dimensions 16-lead TSSOP MM Body Z16.173 CY26049-22 PIN 1 ID DIMENSIONS IN MM[INCHES] MIN. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.05gms MAX. BSC. MAX. SEATING PLANE GAUGE PLANE 0° -8° 51-85091-*A FailSafe and PacketClock are trademarks of Cypress Semiconductor. Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Page 5 of 6 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY26049-22 Document History Page Document Title CY26049-22 FailSafe PacketClock Global Communications Clock Generator Document Number 38-07730 Description of Change 308456 See ECN RGL New Data Sheet Page 6 of 6

PDF Datasheet Preview

CY26049-22

FailSafe PacketClock Global Communications Clock Generator
• Fully integrated phase-locked loop PLL
• output
• PLL driven by a crystal oscillator that is phase aligned
with external reference
• 100-MHz output from 10-MHz input
• Low-jitter, high-accuracy outputs
• 3.3V ± 5% operation
• 16-lead TSSOP
• Integrated high-performance PLL tailored for telecommunications frequency synthesis eliminates the need for external loop filter components
• When reference is off, DCXO maintains clock outputs and SAFE pin indicates FailSafe conditions
• DCXO maintains continuous operation should the input reference clock fail
• Glitch-free transition simplifies system design
• Works with commonly available, low-cost 10-MHz crystal
• Zero-ppm error for all output frequencies
• Compatible across industry standard design platforms
• Industry standard package with x mm2 footprint and
a height profile of just mm

Logic Block Diagram
input reference 10M Hz IC L K
external pullable crystal 10M Hz

XOUT

F A ILS A F ETM CONTROL

D IG IT A L CONTROLLED

CRYSTAL O SCILLATOR

PHASE LOCKED

LOOP

OUTPUT D IV ID E R

CLKA 100M H z

SAFE ICLK detected

Cypress Semiconductor Corporation
• 3901 North First Street
• San Jose, CA 95134
• 408-943-2600

Pin Configuration

CY26049-22
16-pin TSSOP Top View

ICLK 1 NC 2 NC 3 NC 4

VDD 5 VSS 6 NC 7 XIN 8
16 NC 15 CLKA 14 NC 13 NC 12 VDD 11 VSS 10 SAFE 9 XOUT

Pin Description

Pin Number Pin Name

Pin Description

ICLK Reference Input Clock 10 MHz.

NC No Connect.

NC No Connect.

NC No Connect.

VDD Voltage Supply 3.3V.

VSS Ground.

NC No Connect
Ordering Information
Ordering Code Lead-Free CY26049ZXC-22 CY26049ZXC-22T
10MHz

Package Type
16-lead TSSOP 16-lead and Reel

Operating Temperature Range

Commercial 0° to 70°C Commercial 0° to 70°C

Page 4 of 6

Package Drawing and Dimensions
16-lead TSSOP MM Body Z16.173

CY26049-22

PIN 1 ID

DIMENSIONS IN MM[INCHES] MIN.

REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.05gms

MAX.

BSC.

MAX.

SEATING PLANE

GAUGE PLANE
0° -8°
51-85091-*A

FailSafe and PacketClock are trademarks of Cypress Semiconductor. Corporation. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 5 of 6

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

CY26049-22

Document History Page

Document Title CY26049-22 FailSafe PacketClock Global Communications Clock Generator Document Number 38-07730

Description of Change
308456 See ECN RGL New Data Sheet

Page 6 of 6

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY26049ZXC-22T Datasheet file may be downloaded here without warranties.

Datasheet ID: CY26049ZXC-22T 507713