CY24130ZXC-1

CY24130ZXC-1 Datasheet


CY24130

Part Datasheet
CY24130ZXC-1 CY24130ZXC-1 CY24130ZXC-1 (pdf)
Related Parts Information
CY24130ZXC-1T CY24130ZXC-1T CY24130ZXC-1T
CY24130ZXC-2T CY24130ZXC-2T CY24130ZXC-2T
CY24130ZXC-2 CY24130ZXC-2 CY24130ZXC-2
CY24130KZXC-1T CY24130KZXC-1T CY24130KZXC-1T
CY24130KZXC-1 CY24130KZXC-1 CY24130KZXC-1
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CY24130

HOTLink II SMPTE Receiver Training Clock
• Integrated phase-locked loop
• Low-jitter, high-accuracy outputs
• 3.3V operation
• Internal PLL with up to 400-MHz internal operation
• Meets critical timing requirements in complex system designs
• Enables application compatibility

Table Frequency table

Part Number Outputs

CY24130-1

CY24130-2

Input Frequency 27 MHz Driven Reference
27 MHz Crystal Reference

Output Frequency Range
1 copy 27-MHz reference clock output 1 copy of 27-/36-/54-/148.5-/74.25-MHz frequency selectable
1 copy 27-MHz reference clock output 1 copy of 27-/36-/54-/148.5-/74.25-MHz frequency selectable

Logic Block Diagram

XIN XOUT

OSC.

S0 S1 S2

OUTPUT

MULTIPLEXER AND

DIVIDERS

VDDL VDD AVDD AVSS VSS VSSL

CLKA REFCLK

Table Frequency Select Options

CLKA 27 36 54

OFF, pulled low OFF, pulled low OFF, pulled low

REFCLK 27

Units MHz
• San Jose, CA 95134-1709
• 408-943-2600
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CY24130

Pin Configuration

Figure CY24130-1, -2, 16-pin TSSOP

XIN 1 VDD 2 AVDD 3

S0 4 AVSS 5 VSSL 6

N/C 7 CLKA 8
16 XOUT 15 S2 14 REFCLK 13 VSS 12 N/C 11 VDDL 10 S1 9 N/C

Table Pin Definition

Name XIN VDD AVDD S0 AVSS VSSL N/C CLKA N/C S1 VDDL N/C VSS REFCLK S2 XOUT

Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Ordering Information
Ordering Code Pb-free CY24130ZXC-1[2] CY24130ZXC-1T[2] CY24130ZXC-2[2] CY24130ZXC-2T[2] CY24130KZXC-1 CY24130KZXC-1T

Package Type
16-Pin TSSOP 16-Pin TSSOP Tape and Reel 16-Pin TSSOP 16-Pin TSSOP Tape and Reel 16-Pin TSSOP 16-Pin TSSOP Tape and Reel
20% of V DD

Operating Range

Commercial

Operating Voltage
3.3V 3.3V 3.3V 3.3V 3.3V 3.3V

Note Not recommended for new design.

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Package Drawing and Dimensions

Figure 16-lead TSSOP MM Body Z16.173

CY24130

BSC.

PIN 1 ID

DIMENSIONS IN MM[INCHES] MIN. MAX.

REFERENCE JEDEC MO-153 PACKAGE WEIGHT gms

PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG.

MAX.

SEATING PLANE

GAUGE PLANE
0° -8°
51-85091-*A

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CY24130

Document History Page

Document Title CY24130 HOTLink II SMPTE Receiver Training Clock Document Number 38-07711

ECN NO.

Orig. of Change

Submission Date

Description of Change
314514 RGL

See ECN New Data Sheet
2442066 AESA

See ECN Updated template. Added Note “Not recommended for new designs.”
Added part number CY24130KZXC-1, and CY24130KZXC-1T in ordering
information table.

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales.

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Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

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MediaClock is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders. All products and company names mentioned in this document may be the trademarks of their respective holders.
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Datasheet ID: CY24130ZXC-1 507697