CY23FS04ZXC-2T

CY23FS04ZXC-2T Datasheet


CY23FS04-2

Part Datasheet
CY23FS04ZXC-2T CY23FS04ZXC-2T CY23FS04ZXC-2T (pdf)
Related Parts Information
CY23FS04ZXC-2 CY23FS04ZXC-2 CY23FS04ZXC-2
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CY23FS04-2

Failsafe 2.5V/3.3V Zero Delay Buffer
• Internal DCXO for Continuous Glitch-free Operation
• Zero Input-Output Propagation Delay
• Low-Jitter 35 ps max RMS Outputs
• Low Output-to-Output Skew 200 ps max
• MHz to 50 MHz Reference Input
• Supports Industry Standard Input Crystals
• MHz to 50 MHz Outputs
• 5V-Tolerant Inputs
• Phase-Locked Loop PLL Bypass Mode
• Dual Reference Inputs
• 16-Pin TSSOP
• 2.5V or 3.3V Output Power Supplies
• 3.3V Core Power Supply

Logic Block Diagram

Functional Description

The CY23FS04-2 is a FailSafe zero delay buffer with two reference clock inputs and four phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure.

The continuous, glitch-free operation is achieved by using a DCXO, which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock.

The unique feature of the CY23FS04-2 is that the DCXO is in fact the primary clocking source, which is synchronized phase-aligned to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock.

The frequency of the crystal that is connected to the DCXO must be an integer factor of the frequency of the reference clock. This factor is set by two select lines S[2:1], see Table The output power supply VDD can be connected to either 2.5V or 3.3V. VDDC is the power supply pin for internal circuits and must be connected to 3.3V.

REFSEL

XIN XOUT DCXO

REF1

REF2

FailsafeTM Block
2 CLKA[1:2]
2 CLKB[1:2]

S[2:1]

Decoder 2

FAIL# /SAFE
• San Jose, CA 95134-1709
• 408-943-2600
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CY23FS04-2

Contents

Features 1 Functional Description 1 Logic Block Diagram 1 Contents 2 Pin Configuration 3 FailSafe Function 4

XTAL Selection Criteria and Application Example 7 Absolute Maximum Conditions 9 Recommended Pullable Crystal Specifications 9 Operating Conditions for FailSafe Devices 9
Electrical Characteristics for FailSafe Devices 10 Switching Characteristics for FailSafe Devices 10 Ordering Information 10 Package Diagram 11 Document History Page 12 Sales, Solutions, and Legal Information 12

Worldwide Sales and Design Support 12 Products 12 PSoC Solutions 12

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Pin Configuration

Figure 16-Pin TSSOP

CY23FS04-2

Table Pin Definition

Pin No. 1,2 3,4 14,13 15

Pin Name REF[1:2] CLKB[1:2] CLKA[1:2] FBK
12,5

S[1:2]

XOUT

FAIL#/SAFE

VDDC

REFSEL

Description Reference clock inputs. 5V-tolerant.[4] Bank B clock outputs.[1,2] Bank A clock outputs.[1,2] Feedback input to the PLL.[1,4] Frequency select pins and PLL and DCXO bypass mode.[3]

Reference crystal input.

Reference crystal output.

Valid reference indicator. A high level indicates a valid reference input.
2.5V or 3.3V power supply.
3.3V power supply.

Ground.

Reference select. Selects the active reference clock from either REF1 or REF2. REFSEL = 1, REF1 is selected REFSEL = 0, REF2 is selected.

Table Configuration Table

S[2:1] 00

XTAL MHz

REF MHz

OUT MHz

REF:OUT Ratio

PLL and DCXO Bypass Mode

REF:XTAL Ratio
1/2 1

Out:XTAL Ratio
1/2 1

Notes For normal operation, connect either one of the four clock outputs to the FBK input. Weak pull downs on all outputs. Weak pull ups on these inputs. Weak pull down on these inputs

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CY23FS04-2

FailSafe Function

The CY23FS04-2 is targeted at clock distribution applications that require continued operation should the main reference clock fail. Existing approaches to this requirement have used multiple reference clocks with either internal or external methods to switch between references. The problem with this technique is that it leads to interruptions or glitches when transitioning from one reference to another, often requiring complex external circuitry or software to maintain system stability. The technique implemented in this design completely eliminates any switching of references to the PLL, greatly simplifying system design.

The CY23FS04-2 PLL is driven by the crystal oscillator, which is phase-aligned to an external reference clock so that the output of the device is effectively phase-aligned to the reference via the external feedback loop. This is accomplished by using a digitally controlled capacitor array to pull the crystal frequency over an approximate range of +300 ppm from its nominal frequency.

In this mode, if the reference frequency fails stop or disappear , the DCXO maintains its last setting and a flag signal FAIL#/SAFE is set to indicate failure of the reference clock.
Ordering Information

Part Number Pb-free CY23FS04ZXC-2 CY23FS04ZXC-2T

Package Type
16-Pin TSSOP 16-Pin TSSOP Tape and Reel

Product Flow

Commercial, 0°C to 70°C Commercial, 0°C to 70°C

Notes

The reference feedback input delay is guaranteed for a maximum 4:1 input edge ratio between the two signals as long as tSR I is maintained.

Parameters guaranteed by design and characterization, not 100% tested in production.

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CY23FS04-2

Package Diagram

Figure 16-Pin TSSOP mm Body

PIN 1 ID

DIMENSIONS IN MM[INCHES] MIN. MAX.

REFERENCE JEDEC MO-153

PACKAGE WEIGHT 0.05gms

BSC.

MAX.

SEATING PLANE

GAUGE PLANE
0°-8°
51-85091 *B

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CY23FS04-2

Document History Page

Document Title CY23FS04-2 Failsafe 2.5V/3.3V Zero Delay Buffer Document Number 38-07671

ECN No.

Submission Date

Orig. of Change

Description of Change
224423 See ECN

RGL New data sheet
276753

See ECN RGL/ZJX Removed TLOCK Lock Time Specification
2865337 01/25/2010

CXQ Updated format.

Added “Contents” section on page

Removed previous Figures 5 and

Added / separated Figures 7 through
Changed test condition from 15 pF to 30 pF for fOUT spec. Removed industrial temp range devices from Ordering Information.

Removed unreferenced Note

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Automotive Clocks & Buffers Interface Lighting & Power Control

Memory Optical & Image Sensing
cypress.com/go/automotive cypress.com/go/clocks
cypress.com/go/interface cypress.com/go/powerpsoc
cypress.com/go/plc cypress.com/go/memory
cypress.com/go/image

PSoC Touch Sensing USB Controllers Wireless/RF
cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless

PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Page 12 of 12

FailSafe is a trademark of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.
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Datasheet ID: CY23FS04ZXC-2T 507690