CY14V101QS-SE108XI

CY14V101QS-SE108XI Datasheet

CY14V101QS

Part	Datasheet
CY14V101QS-SE108XI	CY14V101QS-SE108XI (pdf)

Related Parts	Information
CY14V101QS-SF108XI	CY14V101QS-SF108XI
CY14V101QS-SF108XQ	CY14V101QS-SF108XQ
CY14V101QS-BK108XQ	CY14V101QS-BK108XQ
CY14V101QS-BK108XI	CY14V101QS-BK108XI
CY14V101QS-SE108XQ	CY14V101QS-SE108XQ

PDF Datasheet Preview
CY14V101QS 1-Mbit 128K x 8 Quad SPI nvSRAM • Density 1 Mbit 128K x 8 • Bandwidth 108-MHz high-speed interface Read and write at 54 Mbps • Serial Peripheral Interface Clock polarity and phase modes 0 and 3 Multi I/O option Single SPI , Dual SPI DPI , and Quad SPI QPI • High reliability Infinite read, write, and RECALL cycles One million STORE cycles to nonvolatile elements SONOS FLASH Quantum trap Data retention 20 years at 85 °C • Read Commands Normal, Fast, Dual I/O, and Quad I/O Modes Burst Wrap, Continuous XIP • Write Commands Normal, Fast, Dual I/O, and Quad I/O Modes Burst Wrap, Continuous XIP • Data protection Hardware Through Write Protect Pin WP Software Through Write Disable instruction Block Protection Status Register bits to control protection • Special instructions STORE/RECALL Access data between SRAM and Quantum Trap Serial Number 8-byte customer selectable OTP Identification Number 4-byte Manufacturer ID and Product ID • Store from SRAM to nonvolatile SONOS FLASH Quantum Trap AutoStore Initiated automatically at power-down with a small capacitor VCAP Software Using SPI instruction STORE Hardware HSB pin • Recall from nonvolatile SONOS FLASH Quantum Trap to SRAM Auto RECALL Initiated automatically at power-up Software Using SPI instruction RECALL • Low-power modes Sleep Average current = 280 µA at 85 °C, 500 µA at 105 °C Hibernate Average current = 8 µA at 85 °C, 10 µA at 105 °C • Operating supply voltages Core VCC V to V I/O VCCQ V to V • Temperature range Extended Industrial °C to 105 °C Industrial °C to 85 °C • Packages 16-pin SOIC 24-ball FBGA Functional Overview The Cypress CY14V101QS combines a 1-Mbit nvSRAM in a monolithic integrated circuit with a QPI interface. The QPI allows writing and reading the memory in either a single one I/O channel for one bit per clock cycle , dual two I/O channels for two bits per clock cycle , or quad four I/O channels for four bits per clock cycle through the use of selected opcodes. The memory is organized as 128K words of eight bits each consisting of SRAM and nonvolatile SONOS FLASH Quantum Trap cells. The SRAM provides infinite read and write cycles, while the nonvolatile cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile cells STORE operation take place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile cells RECALL operation . You can also initiate the STORE and RECALL operations through SPI instruction. Errata For information on silicon errata, see “Errata” on page Details include trigger conditions, devices affected, and proposed workaround. • San Jose, CA 95134-1709 • 408-943-2600 Logic Block Diagram Status Configuration Registers Serial Number Manufacturer ID Product ID HOLD I/O3 HSB SI I/O0 CS SCK WP I/O2 SO I/O1 VCC VCCQ VSS VCAP SPI/DPI/QPI Control Logic Write Protection Instruction Decoder SLEEP/HIBERNATE Power Control Block Memory Control Address & Data CY14V101QS Nonvolatile Array 128K x 8 STORE SRAM Array 128K x 8 RECALL Page 2 of 60 CY14V101QS Identification Register RDID Instruction 36 Identification Register FAST_RDID Instruction 37 Serial Number Register Write WRSN Instruction 38 Serial Number Register Read RDSN Instruction 39 Fast Read Serial Number Register FAST_RDSN Instruction 40 NV Specific Instructions 41 Software Store Instruction 41 Software Recall Instruction 41 Autostore Enable ASEN Instruction 42 Autostore Disable ASDI Instruction 42 HOLD Pin Operation 43 Maximum Ratings 44 Operating Range 44 DC Specifications 44 Data Retention and Endurance 46 Capacitance 46 Thermal Resistance 46 AC Test Loads and Waveforms 46 AC Test Conditions 46 AC Switching Characteristics 47 Switching Waveforms 48 AutoStore or Power-Up RECALL 48 Switching Waveforms 49 Software Controlled STORE and RECALL Cycles 50 Switching Waveforms 50 Hardware STORE Cycle 51 Switching Waveforms 51 Ordering Information 52 Ordering Code Definitions 52 Package Diagrams 53 Acronyms 54 Document Conventions 54 Units of Measure 54 Errata 55 Document History Page 57 Sales, Solutions, and Legal Information 60 Worldwide Sales and Design Support 60 Products 60 Solutions 60 Cypress Developer Community 60 Technical Support 60 Page 3 of 60 Pinout Figure 16-Pin SOIC Standard Pinout HOLD I/O3 1 VCC 2 RFU 3 NC 4 NC 5 RFU 6 CS 7 SO I/O1 8 16 15 16-pin 14 SOIC 13 12 Top View 11 SCK SI I/O0 VCCQ VCAP HSB NC VSS WP I/O2 Figure 16-Pin SOIC Custom Pinout HOLD I/O3 1 VCCQ 2 VCC 3 NC 4 NC 5 NC 6 CS 7 SO I/O1 8 16 15 16- pin SOIC 12 Top View 11 SCK SI I/O0 NC VCAP HSB NC VSS WP I/O2 CY14V101QS Page 4 of 60 CY14V101QS Figure 24-Ball FPGA Standard Pinout-Top View Ball Side Down WP I/O2 VCAP SO I/O1 SI I/O0 HOLD I/O3 VCCQ Pin Definitions Pin Description HOLD I/O3 I/O Type Input Input/Output VCCQ VCC Power Supply Power Supply Input SO I/O1 Output Input/Output WP I/O2 Input/Output Ground Input/Output Ordering Information Ordering Code Package Diagram Package Type/Pinout CY14V101QS-BK108XI CY14V101QS-BK108XITR CY14V101QS-BK108XQ 001-97209 24-FBGA, Standard CY14V101QS-BK108XQTR CY14V101QS-SE108XI CY14V101QS-SE108XITR CY14V101QS-SE108XQ 16-SOIC, Custom CY14V101QS-SE108XQTR CY14V101QS-SF108XI 51-85022 CY14V101QS-SF108XITR CY14V101QS-SF108XQ 16-SOIC, Standard CY14V101QS-SF108XQTR All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts. Ordering Code Definitions CY 14 V 101 QS - SF 108 X I TR Option TR - Tape and Reel, Blank - Std. Temperature I - Industrial, Q - Extended Industrial Pb-free Frequency 108 - 108 MHz Operating Range Industrial Extended Industrial Extended Industrial Extended Industrial Package SF - 16 SOIC Standard, SE - 16 SOIC Custom, BK - 24 FBGA QS - Quad SPI, PS - Quad SPI with RTC Density 101 - 1-Mbit Voltage V - V, V I/O 14 - nvSRAM CY - Cypress Page 52 of 60 CY14V101QS Package Diagrams Figure 16-Pin SOIC x Inches Package Outline, 51-85022 TOP VIEW BSC PIN A1 CORNER Figure 24-ball FBGA Package SIDE VIEW 51-85022 E BOTTOM VIEW BSC MAX C PIN A1 CORNER 001-97209 * Page 53 of 60 CY14V101QS Acronyms Acronym CPHA CPOL CMOS CRC EEPROM EIA I/O JEDEC LSB MSB nvSRAM RWI RoHS SNL SPI SONOS SOIC SRAM Description clock phase clock polarity complementary metal oxide semiconductor cyclic redundancy check electrically erasable programmable read-only memory Electronic Industries Alliance input/output Joint Electron Devices Engineering Council least significant bit most significant bit nonvolatile static random access memory read and write inhibit restriction of hazardous substances serial number lock serial peripheral interface silicon-oxide-nitride-oxide semiconductor small outline integrated circuit static random access memory Document Conventions Units of Measure Symbol °C Hz kHz Mbit MHz mA ms ns % pF V W Unit of Measure degree Celsius hertz kilohertz kilohm megabit megahertz microampere microfarad microsecond milliampere millisecond nanosecond ohm percent picofarad volt watt Page 54 of 60 Removed DFN package Updated ordering information Updated the document title removed the brackets around SPI since this is not a Quad nvSRAM . Replaced the following sections Features, Functional Overview, Device Operation, SPI Functional Description, DC Specifications, AC Switching Characteristics, and Ordering Information. Added The device provides a default recovery mode where the device is brought back to SPI mode. A logic high on all I/Os I/O3, I/O2, I/O1, I/O0 with eight SCLKs brings the device into a known mode SPI so that the host can communicate to the device if the starting mode is unknown. Updated the figure title in Figure Added Figure Replaced Figure 40 and Figure Updated Pin Definitions. Removed the Notes in Pin Definitions section. Updated Table 4620720 SZZX 01/23/2015 Updated Power-Down from “conditional AutoStore operation is performed” to “Autostore operation is performed”. Updated the first paragraph in SPI Overview. Updated the first sentence to “CY14V101QS has one 8-bit Status Register, in Status Register. Updated the device status for Status Register state, in Power-Up. Updated the VCCQ values in Operating Range. Updated the Minimum factor VIH and Maximum factor for VIL in DC Specifications. Updated the description for DATAR in Data Retention and Endurance. Updated the Maximum value of CIN, CCLK, and COUT to 7, in Capacitance. Updated AutoStore or Power-Up RECALL. Updated Figure Added Note Updated the Maximum value of tRECALL to 500 in Software Controlled STORE and RECALL Cycles. Updated Ordering Information and Ordering Code Definitions. Updated Low-power modes feature in Features. Updated section heading “Active Power and Standby Power Modes” to Updated CS Pin Description in Pin Definitions. Updated the term “Standby power mode” to “Standby mode” in Power-Up and Power-Down. Updated the section title “Active Power and Standby Modes” to Active Power 4653540 SZZX 02/19/2015 Mode and Standby State. Updated Table Updated Active Power Mode and Standby State. Updated the Power modes in System Resource instruction, in SPI Functional Description. Removed “Standby Instruction” section. Updated Sleep Instruction. Page 57 of 60 CY14V101QS Document Title CY14V101QS, 1-Mbit 128K x 8 Quad SPI nvSRAM Document Number 001-85257 ECN No. Orig. of Submission Change Description of Change D Cont. 4653540 SZZX 02/19/2015 Added Hibernate HIBEN Instruction. Replaced the term “dummy” to “mode” in the following subsections SRAM Read, Fast Read Instructions, FAST_READ Instruction, DOR Instruction, and QOR Instruction. Replaced the term “dummy” with “mode/dummy” in Instruction. Replaced the term “dummy cycle” with “mode byte cycle” in FAST_READ Instruction. Replaced the following figures Figure 22, Figure 23, Figure 31, Figure 40, and Figure 70 through Figure Updated DC Specifications. Updated AutoStore or Power-Up RECALL. Updated the following in Features Temperature range, Packages, and Low-power modes. Added the following figures Figure 3, Figure 61, Figure 63 through Figure 65, and Figure 79 through Figure Updated the following figures Figure 6, Figure 7, Figure 14, Figure 15, Figure 22, Figure 23, Figure 38 through Figure 45, Figure 66, Figure 70 through Figure 72, Figure 78, Figure 82 through Figure 93, and Figure Added the following sections Write-Protect WP , Hold , Configuration Register, Read Status Register RDSR Instruction, Write Configuration Register WRCR Instruction, and Fast Read Serial Number Register FAST_RDSN Instruction. Updated the following sections: Functional Overview, SRAM Read, Status Register Write Disable SRWD SR[7], Write Enable WEL SR[1], Quad Data Width QUAD CR[1], Software Store Instruction, Software Recall Instruction, Data Transmission - SI/SO, Write-Protect WP , Power-Up, Configuration Register, Enable QPI QPIEN Instruction, Enable SPI SPIEN Instruction, Software Reset Instruction, Serial Number Register Write WRSN Instruction, Serial Number Register Read RDSN Instruction, Identification Register RDID Instruction, Maximum Ratings, Operating Range, DC Specifications, 4779656 SZZX 05/28/2015 Thermal Resistance, AC Switching Characteristics, AutoStore or Power-Up RECALL, Ordering Information and Ordering Code Definitions. Updated the following in SPI Functional Description Updated the Register instructions and nvSRAM Special instruction, and added a Note. Updated the following in Quad Data Width QUAD CR[1] Updated the section and added a Note. Added Table 7 through Table Updated the following tables Table 1, Table 2, Table 5, and Table Added a Note in Write-Protect WP , Chip Select CS , QOR Instruction, QIOR Instruction, QIW Instructions, QIOW Instruction, Status Register Write Disable SRWD SR[7], Write Enable WEL SR[1], Quad Data Width QUAD CR[1], Write Disable WRDI Instruction, Write Enable WREN Instruction, Enable DPI DPIEN Instruction, Enable SPI SPIEN Instruction, READ Instruction, FAST_READ Instruction, WRITE Instruction, Default Recovery Instruction, Software Reset Instruction, Hibernate HIBEN Instruction, Sleep Instruction, Read Status Register RDSR Instruction, Write Status Register WRSR Instruction, Identification Register RDID Instruction, Identification Register FAST_RDID Instruction, Serial Number Register Write WRSN Instruction, Serial Number Register Read RDSN Instruction, Fast Read Serial Number Register FAST_RDSN Instruction, Software Store Instruction, Software Recall Instruction, Autostore Disable ASDI Instruction, and Autostore Enable ASEN Instruction. Page 58 of 60 CY14V101QS Document Title CY14V101QS, 1-Mbit 128K x 8 Quad SPI nvSRAM Document Number 001-85257 ECN No. Orig. of Submission Change Description of Change E Cont. 4779656 4797469 4827642 4856882 SZZX SZZX 05/28/2015 07/02/2015 07/09/2015 07/24/2015 Removed the section “Read Fault Register RDGR Instruction” and “Device ID section”. Removed Table Fault Register Format and Bit Definitions. Removed Figure RDGR Instruction in SPI Mode, Figure RDGR Instruction in DPI Mode, and Figure RDGR Instruction in QPI Mode. Removed 256-Kbit device description and associated part numbers Changed datasheet status from SUMMARY to PRELIMINARY No technical changes Added Figure Updated Figure 6 through Figure Added Errata. Page 59 of 60 CY14V101QS Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Solutions Clocks & Buffers cypress.com/go/clocks psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 4 \| PSoC 5LP cypress.com/go/interface Lighting & Power Control............ cypress.com/go/powerpsoc cypress.com/go/memory PSoC Touch Sensing cypress.com/go/touch Cypress Developer Community \| Forums \| Blogs \| Video \| Training Technical Support cypress.com/go/support Wireless/RF cypress.com/go/wireless Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. All products and company names mentioned in this document may be the trademarks of their respective holders. Page 60 of 60

PDF Datasheet Preview

CY14V101QS
1-Mbit 128K x 8 Quad SPI nvSRAM
• Density 1 Mbit 128K x 8
• Bandwidth 108-MHz high-speed interface Read and write at 54 Mbps
• Serial Peripheral Interface Clock polarity and phase modes 0 and 3 Multi I/O option Single SPI , Dual SPI DPI , and Quad SPI QPI
• High reliability Infinite read, write, and RECALL cycles One million STORE cycles to nonvolatile elements SONOS FLASH Quantum trap Data retention 20 years at 85 °C
• Read Commands Normal, Fast, Dual I/O, and Quad I/O Modes Burst Wrap, Continuous XIP
• Write Commands Normal, Fast, Dual I/O, and Quad I/O Modes Burst Wrap, Continuous XIP
• Data protection Hardware Through Write Protect Pin WP Software Through Write Disable instruction Block Protection Status Register bits to control protection
• Special instructions STORE/RECALL Access data between SRAM and Quantum Trap Serial Number 8-byte customer selectable OTP Identification Number 4-byte Manufacturer ID and Product ID
• Store from SRAM to nonvolatile SONOS FLASH Quantum Trap AutoStore Initiated automatically at power-down with a small capacitor VCAP Software Using SPI instruction STORE Hardware HSB pin
• Recall from nonvolatile SONOS FLASH Quantum Trap to SRAM Auto RECALL Initiated automatically at power-up Software Using SPI instruction RECALL
• Low-power modes Sleep Average current = 280 µA at 85 °C, 500 µA at 105 °C Hibernate Average current = 8 µA at 85 °C, 10 µA at 105 °C
• Operating supply voltages Core VCC V to V I/O VCCQ V to V
• Temperature range Extended Industrial °C to 105 °C Industrial °C to 85 °C
• Packages 16-pin SOIC 24-ball FBGA

Functional Overview

The Cypress CY14V101QS combines a 1-Mbit nvSRAM in a monolithic integrated circuit with a QPI interface. The QPI allows writing and reading the memory in either a single one I/O channel for one bit per clock cycle , dual two I/O channels for two bits per clock cycle , or quad four I/O channels for four bits per clock cycle through the use of selected opcodes. The memory is organized as 128K words of eight bits each consisting of SRAM and nonvolatile SONOS FLASH Quantum Trap cells. The SRAM provides infinite read and write cycles, while the nonvolatile cells provide highly reliable nonvolatile storage of data. Data transfers from SRAM to the nonvolatile cells STORE operation take place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile cells RECALL operation . You can also initiate the STORE and RECALL operations through SPI instruction.

Errata For information on silicon errata, see “Errata” on page Details include trigger conditions, devices affected, and proposed workaround.
• San Jose, CA 95134-1709
• 408-943-2600

Logic Block Diagram

Status Configuration

Registers

Serial Number Manufacturer ID

Product ID

HOLD I/O3 HSB

SI I/O0 CS

SCK WP I/O2 SO I/O1

VCC VCCQ

VSS VCAP

SPI/DPI/QPI Control Logic Write Protection Instruction Decoder

SLEEP/HIBERNATE

Power Control Block

Memory Control Address & Data

CY14V101QS

Nonvolatile Array 128K x 8

STORE

SRAM Array 128K x 8

RECALL

Page 2 of 60

CY14V101QS
Identification Register RDID Instruction 36 Identification Register FAST_RDID Instruction 37 Serial Number Register Write WRSN Instruction 38 Serial Number Register Read RDSN Instruction 39 Fast Read Serial Number Register FAST_RDSN Instruction 40 NV Specific Instructions 41 Software Store Instruction 41 Software Recall Instruction 41 Autostore Enable ASEN Instruction 42 Autostore Disable ASDI Instruction 42 HOLD Pin Operation 43 Maximum Ratings 44 Operating Range 44 DC Specifications 44 Data Retention and Endurance 46 Capacitance 46 Thermal Resistance 46 AC Test Loads and Waveforms 46 AC Test Conditions 46 AC Switching Characteristics 47 Switching Waveforms 48 AutoStore or Power-Up RECALL 48 Switching Waveforms 49 Software Controlled STORE and RECALL Cycles 50 Switching Waveforms 50 Hardware STORE Cycle 51 Switching Waveforms 51 Ordering Information 52 Ordering Code Definitions 52 Package Diagrams 53 Acronyms 54 Document Conventions 54 Units of Measure 54 Errata 55 Document History Page 57 Sales, Solutions, and Legal Information 60 Worldwide Sales and Design Support 60 Products 60 Solutions 60 Cypress Developer Community 60 Technical Support 60

Page 3 of 60

Pinout

Figure 16-Pin SOIC Standard Pinout

HOLD I/O3 1 VCC 2 RFU 3 NC 4 NC 5 RFU 6 CS 7

SO I/O1 8
16 15
16-pin 14 SOIC 13
12 Top View 11

SCK SI I/O0 VCCQ VCAP HSB NC VSS WP I/O2

Figure 16-Pin SOIC Custom Pinout

HOLD I/O3 1 VCCQ 2 VCC 3 NC 4 NC 5

NC 6 CS 7 SO I/O1 8
16 15
16- pin

SOIC
12 Top View 11

SCK SI I/O0 NC VCAP HSB NC VSS WP I/O2

CY14V101QS

Page 4 of 60

CY14V101QS

Figure 24-Ball FPGA Standard Pinout-Top View Ball Side Down

WP I/O2

VCAP

SO I/O1

SI I/O0

HOLD I/O3

VCCQ

Pin Definitions Pin Description

HOLD I/O3

I/O Type Input

Input/Output

VCCQ VCC

Power Supply Power Supply

Input

SO I/O1

Output Input/Output

WP I/O2

Input/Output

Ground

Input/Output
Ordering Information
Ordering Code

Package Diagram

Package Type/Pinout

CY14V101QS-BK108XI

CY14V101QS-BK108XITR CY14V101QS-BK108XQ
001-97209
24-FBGA, Standard

CY14V101QS-BK108XQTR

CY14V101QS-SE108XI

CY14V101QS-SE108XITR CY14V101QS-SE108XQ
16-SOIC, Custom

CY14V101QS-SE108XQTR CY14V101QS-SF108XI
51-85022

CY14V101QS-SF108XITR CY14V101QS-SF108XQ
16-SOIC, Standard

CY14V101QS-SF108XQTR

All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts.
Ordering Code Definitions

CY 14 V 101 QS - SF 108 X I TR

Option TR - Tape and Reel, Blank - Std.

Temperature I - Industrial, Q - Extended Industrial

Pb-free

Frequency 108 - 108 MHz

Operating Range Industrial

Extended Industrial

Extended Industrial

Extended Industrial

Package SF - 16 SOIC Standard, SE - 16 SOIC Custom, BK - 24 FBGA

QS - Quad SPI, PS - Quad SPI with RTC

Density 101 - 1-Mbit

Voltage V - V, V I/O
14 - nvSRAM

CY - Cypress

Page 52 of 60

CY14V101QS

Package Diagrams

Figure 16-Pin SOIC x Inches Package Outline, 51-85022

TOP VIEW BSC

PIN A1 CORNER

Figure 24-ball FBGA Package

SIDE VIEW
51-85022 *E

BOTTOM VIEW BSC

MAX C

PIN A1 CORNER
001-97209 **

Page 53 of 60

CY14V101QS

Acronyms

Acronym CPHA CPOL CMOS CRC EEPROM

EIA I/O JEDEC LSB MSB nvSRAM RWI RoHS SNL SPI SONOS SOIC SRAM

Description clock phase clock polarity complementary metal oxide semiconductor cyclic redundancy check electrically erasable programmable read-only memory Electronic Industries Alliance input/output Joint Electron Devices Engineering Council least significant bit most significant bit nonvolatile static random access memory read and write inhibit restriction of hazardous substances serial number lock serial peripheral interface silicon-oxide-nitride-oxide semiconductor small outline integrated circuit static random access memory

Document Conventions

Units of Measure

Symbol °C Hz kHz Mbit MHz mA ms ns
% pF V W

Unit of Measure degree Celsius hertz kilohertz kilohm megabit megahertz microampere microfarad microsecond milliampere millisecond nanosecond ohm percent picofarad volt watt

Page 54 of 60
Removed DFN package Updated ordering information

Updated the document title removed the brackets around SPI since this is not
a Quad nvSRAM .

Replaced the following sections Features, Functional Overview, Device

Operation, SPI Functional Description, DC Specifications, AC Switching
Characteristics, and Ordering Information.

Added The device provides a default recovery mode where the device is
brought back to SPI mode. A logic high on all I/Os I/O3, I/O2, I/O1, I/O0 with
eight SCLKs brings the device into a known mode SPI so that the host can
communicate to the device if the starting mode is unknown.

Updated the figure title in Figure

Added Figure

Replaced Figure 40 and Figure

Updated Pin Definitions.

Removed the Notes in Pin Definitions section.

Updated Table
4620720

SZZX
01/23/2015

Updated Power-Down from “conditional AutoStore operation is performed” to “Autostore operation is performed”.

Updated the first paragraph in SPI Overview.

Updated the first sentence to “CY14V101QS has one 8-bit Status Register, in

Status Register.

Updated the device status for Status Register state, in Power-Up.

Updated the VCCQ values in Operating Range. Updated the Minimum factor VIH and Maximum factor for VIL in DC Specifications.

Updated the description for DATAR in Data Retention and Endurance. Updated the Maximum value of CIN, CCLK, and COUT to 7, in Capacitance. Updated AutoStore or Power-Up RECALL.

Updated Figure

Added Note

Updated the Maximum value of tRECALL to 500 in Software Controlled STORE and RECALL Cycles.
Updated Ordering Information and Ordering Code Definitions.

Updated Low-power modes feature in Features.

Updated section heading “Active Power and Standby Power Modes” to

Updated CS Pin Description in Pin Definitions.

Updated the term “Standby power mode” to “Standby mode” in Power-Up and

Power-Down.

Updated the section title “Active Power and Standby Modes” to Active Power
4653540 SZZX 02/19/2015 Mode and Standby State.

Updated Table

Updated Active Power Mode and Standby State.

Updated the Power modes in System Resource instruction, in SPI Functional

Description.

Removed “Standby Instruction” section.

Updated Sleep Instruction.

Page 57 of 60

CY14V101QS

Document Title CY14V101QS, 1-Mbit 128K x 8 Quad SPI nvSRAM Document Number 001-85257

ECN No.

Orig. of Submission

Change

Description of Change
*D Cont. 4653540

SZZX
02/19/2015

Added Hibernate HIBEN Instruction. Replaced the term “dummy” to “mode” in the following subsections SRAM Read, Fast Read Instructions, FAST_READ Instruction, DOR Instruction, and QOR Instruction. Replaced the term “dummy” with “mode/dummy” in Instruction. Replaced the term “dummy cycle” with “mode byte cycle” in FAST_READ Instruction. Replaced the following figures Figure 22, Figure 23, Figure 31, Figure 40, and Figure 70 through Figure Updated DC Specifications. Updated AutoStore or Power-Up RECALL.

Updated the following in Features Temperature range, Packages, and Low-power modes. Added the following figures Figure 3, Figure 61, Figure 63 through Figure 65, and Figure 79 through Figure

Updated the following figures Figure 6, Figure 7, Figure 14, Figure 15, Figure 22, Figure 23, Figure 38 through Figure 45, Figure 66, Figure 70 through Figure 72, Figure 78, Figure 82 through Figure 93, and Figure

Added the following sections Write-Protect WP , Hold , Configuration Register, Read Status Register RDSR Instruction, Write Configuration Register WRCR Instruction, and Fast Read Serial Number Register FAST_RDSN Instruction.

Updated the following sections:

Functional Overview, SRAM Read, Status Register Write Disable SRWD

SR[7], Write Enable WEL SR[1], Quad Data Width QUAD CR[1], Software

Store Instruction, Software Recall Instruction, Data

Transmission - SI/SO, Write-Protect WP , Power-Up, Configuration Register,

Enable QPI QPIEN Instruction, Enable SPI SPIEN Instruction, Software

Reset Instruction, Serial Number Register Write WRSN Instruction,

Serial Number Register Read RDSN Instruction, Identification Register

RDID Instruction, Maximum Ratings, Operating Range, DC Specifications,
4779656 SZZX 05/28/2015 Thermal Resistance, AC Switching Characteristics, AutoStore or Power-Up
RECALL, Ordering Information and Ordering Code Definitions.

Updated the following in SPI Functional Description Updated the Register
instructions and nvSRAM Special instruction, and added a Note.

Updated the following in Quad Data Width QUAD CR[1] Updated the section
and added a Note.

Added Table 7 through Table Updated the following tables Table 1, Table 2, Table 5, and Table Added a Note in Write-Protect WP , Chip Select CS , QOR Instruction, QIOR Instruction, QIW Instructions, QIOW Instruction, Status Register Write Disable SRWD SR[7], Write Enable WEL SR[1], Quad Data Width QUAD CR[1], Write Disable WRDI Instruction, Write Enable WREN Instruction, Enable DPI DPIEN Instruction, Enable SPI SPIEN Instruction, READ Instruction, FAST_READ Instruction, WRITE Instruction, Default Recovery Instruction, Software Reset Instruction, Hibernate HIBEN Instruction, Sleep Instruction, Read Status Register RDSR Instruction, Write Status Register WRSR Instruction, Identification Register RDID Instruction, Identification Register FAST_RDID Instruction, Serial Number Register Write WRSN Instruction, Serial Number Register Read RDSN Instruction, Fast Read Serial Number Register FAST_RDSN Instruction, Software Store Instruction, Software Recall Instruction, Autostore Disable ASDI Instruction, and Autostore Enable ASEN Instruction.

Page 58 of 60

CY14V101QS

Document Title CY14V101QS, 1-Mbit 128K x 8 Quad SPI nvSRAM Document Number 001-85257

ECN No.

Orig. of Submission

Change

Description of Change
*E Cont. 4779656
4797469
4827642
4856882

SZZX

SZZX
05/28/2015
07/02/2015 07/09/2015 07/24/2015

Removed the section “Read Fault Register RDGR Instruction” and “Device ID section”. Removed Table Fault Register Format and Bit Definitions. Removed Figure RDGR Instruction in SPI Mode, Figure RDGR Instruction in DPI Mode, and Figure RDGR Instruction in QPI Mode. Removed 256-Kbit device description and associated part numbers Changed datasheet status from SUMMARY to PRELIMINARY No technical changes Added Figure Updated Figure 6 through Figure Added Errata.

Page 59 of 60

CY14V101QS

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support

Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products

Solutions

Clocks & Buffers cypress.com/go/clocks
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/go/interface Lighting & Power Control............ cypress.com/go/powerpsoc cypress.com/go/memory PSoC Touch Sensing cypress.com/go/touch

Cypress Developer Community | Forums | Blogs | Video | Training

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Wireless/RF cypress.com/go/wireless

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY14V101QS-SE108XI Datasheet file may be downloaded here without warranties.

Datasheet ID: CY14V101QS-SE108XI 507663