CY14B104N-BA20XIT

CY14B104N-BA20XIT Datasheet

CY14B104L, CY14B104N

Part	Datasheet
CY14B104N-BA20XIT	CY14B104N-BA20XIT (pdf)

Related Parts	Information
CY14B104N-ZS25XCT	CY14B104N-ZS25XCT
CY14B104N-BA25XC	CY14B104N-BA25XC
CY14B104N-BA25XCT	CY14B104N-BA25XCT
CY14B104N-BA25XI	CY14B104N-BA25XI
CY14B104N-BA25XIT	CY14B104N-BA25XIT
CY14B104N-BA45XC	CY14B104N-BA45XC
CY14B104N-BA45XCT	CY14B104N-BA45XCT
CY14B104N-BA45XIT	CY14B104N-BA45XIT
CY14B104N-BA20XCT	CY14B104N-BA20XCT
CY14B104N-ZS25XC	CY14B104N-ZS25XC
CY14B104N-BA20XC	CY14B104N-BA20XC
CY14B104N-ZS25XI	CY14B104N-ZS25XI
CY14B104N-ZS25XIT	CY14B104N-ZS25XIT
CY14B104N-ZS45XC	CY14B104N-ZS45XC
CY14B104N-ZS45XCT	CY14B104N-ZS45XCT
CY14B104N-ZS45XI	CY14B104N-ZS45XI
CY14B104N-ZS45XIT	CY14B104N-ZS45XIT
CY14B104N-ZS20XCT	CY14B104N-ZS20XCT
CY14B104L-ZS20XCT	CY14B104L-ZS20XCT
CY14B104L-BA20XC	CY14B104L-BA20XC
CY14B104L-BA20XCT	CY14B104L-BA20XCT
CY14B104L-BA20XI	CY14B104L-BA20XI
CY14B104L-BA20XIT	CY14B104L-BA20XIT
CY14B104L-BA25XI	CY14B104L-BA25XI
CY14B104L-BA25XIT	CY14B104L-BA25XIT
CY14B104L-BA45XC	CY14B104L-BA45XC
CY14B104L-BA45XCT	CY14B104L-BA45XCT
CY14B104L-BA45XI	CY14B104L-BA45XI
CY14B104N-BA20XI	CY14B104N-BA20XI
CY14B104L-ZS20XC	CY14B104L-ZS20XC
CY14B104N-ZS20XC	CY14B104N-ZS20XC
CY14B104L-ZS20XI	CY14B104L-ZS20XI
CY14B104L-ZS20XIT	CY14B104L-ZS20XIT
CY14B104L-ZS25XC	CY14B104L-ZS25XC
CY14B104L-ZS25XCT	CY14B104L-ZS25XCT
CY14B104L-ZS25XI	CY14B104L-ZS25XI
CY14B104L-ZS25XIT	CY14B104L-ZS25XIT
CY14B104L-ZS45XC	CY14B104L-ZS45XC
CY14B104L-ZS45XCT	CY14B104L-ZS45XCT
CY14B104L-ZS45XI	CY14B104L-ZS45XI
CY14B104L-ZS45XIT	CY14B104L-ZS45XIT
CY14B104L-BA45XIT	CY14B104L-BA45XIT
CY14B104N-BA45XI	CY14B104N-BA45XI

PDF Datasheet Preview
CY14B104L, CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM • 20 ns, 25 ns, and 45 ns Access Times • Internally organized as 512K x 8 CY14B104L or 256K x 16 CY14B104N • Hands off Automatic STORE on power down with only a small Capacitor • STORE to nonvolatile elements initiated by software, device pin, or on power down • RECALL to SRAM initiated by software or power up • Infinite Read, Write, and Recall Cycles • 200,000 STORE cycles to QuantumTrap • 20 year data retention • Single 3V +20% to operation • Commercial and Industrial Temperatures • 48-ball FBGA and 44/54-pin TSOP II packages • Pb-free and RoHS compliance Functional Description The Cypress CY14B104L/CY14B104N is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 512K bytes of 8 bits each or 256K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down. On power up, data is restored to the SRAM the RECALL operation from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control. Logic Block Diagram[1, 2, 3] 6725 &21752/ &21752/ ' 7 &7 Notes Address A0 - A18 for x8 configuration and Address A0 - A17 for x16 configuration. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration. BHE and BLE are applicable for x16 configuration only. • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback CY14B104L, CY14B104N Pinouts Figure Pin Diagram - 48 FBGA 48-FBGA x8 Top View not to scale 48-FBGA x16 Top View not to scale NC OE A0 A1 A2 NC A4 CE NC DQ0 NC A5 A6 NC DQ4 VSS DQ1 A17 A7 DQ5 VCC VCC DQ2 VCAP A16 DQ6 VSS DQ3 NC A14 A15 NC DQ7 NC[5] HSB A12 A13 WE NC A18 A8 [4] NC BLE OE A0 A1 A2 NC DQ8 BHE A3 A4 CE DQ0 DQ9 DQ10 A5 A6 DQ1 DQ2 VSS DQ11 A17 A7 DQ3 VCC VCC DQ12 VCAP A16 DQ4 VSS DQ14 DQ13 A14 A15 DQ5 DQ6 DQ15 HSB A12 A13 WE DQ7 [4] NC Ordering Information Speed ns Ordering Code 20 CY14B104L-ZS20XCT CY14B104L-ZS20XIT CY14B104L-ZS20XI CY14B104L-BA20XCT CY14B104L-BA20XIT CY14B104L-BA20XI CY14B104L-ZSP20XCT CY14B104L-ZSP20XIT CY14B104L-ZSP20XI CY14B104N-ZS20XCT CY14B104N-ZS20XIT CY14B104N-ZS20XI CY14B104N-BA20XCT CY14B104N-BA20XIT CY14B104N-BA20XI CY14B104N-ZSP20XCT CY14B104N-ZSP20XIT CY14B104N-ZSP20XI 25 CY14B104L-ZS25XCT CY14B104L-ZS25XIT CY14B104L-ZS25XI CY14B104L-BA25XIT CY14B104L-BA25XI CY14B104N-BA25XCT CY14B104L-ZSP25XCT CY14B104L-ZSP25XIT CY14B104L-ZSP25XI CY14B104N-ZS25XCT CY14B104N-ZS25XIT CY14B104N-ZS25XI CY14B104N-BA25XCT CY14B104N-BA25XIT CY14B104N-BA25XI CY14B104N-ZSP25XCT CY14B104N-ZSP25XIT CY14B104N-ZSP25XI CY14B104L, CY14B104N Package Diagram 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 Package Type 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II Ordering Information continued Speed ns Ordering Code Package Diagram Package Type Operating Range 45 CY14B104L-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14B104L-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14B104L-ZS45XI 51-85087 44-pin TSOP II CY14B104L-BA45XCT 51-85128 48-ball FBGA Commercial CY14B104L-BA45XIT 51-85128 48-ball FBGA Industrial CY14B104L-BA45XI 51-85128 48-ball FBGA CY14B104L-ZSP45XCT 51-85160 54-pin TSOP II Commercial CY14B104L-ZSP45XIT 51-85160 54-pin TSOP II Industrial CY14B104L-ZSP45XI 51-85160 54-pin TSOP II CY14B104N-ZS45XCT 51-85087 44-pin TSOP II Commercial CY14B104N-ZS45XIT 51-85087 44-pin TSOP II Industrial CY14B104N-ZS45XI 51-85087 44-pin TSOP II CY14B104N-BA45XCT 51-85128 48-ball FBGA Commercial CY14B104N-BA45XIT 51-85128 48-ball FBGA Removed 48 SSOP Package Added 48 FBGA and 54 TSOPII Packages Updated Part Numbering Nomenclature and Ordering Information Added Soft Sequence Processing Time Waveform B 499597 See ECN Removed 35 ns speed bin Added 55 ns speed bin. Updated AC table for the same Changed “Unlimited” read/write to “infinite” read/write Features section Changed typical ICC at 200-ns cycle time to 8 mA Changed STORE cycles from 500K to 200K cycles Shaded Commercial grade in operating range table Modified Icc/Is specs 48 FBGA package nomenclature changed from BW to BV Modified part nomenclature table. Changes reflected in ordering information table C 517793 See ECN D 774001 See ECN E 914220 See ECN Removed 55ns speed bin Changed pinout for 44TSOPII and 54TSOPII packages Changed ISB to 1mA Changed ICC4 to 3mA Changed VCAP min to 35uF Changed VIH max to Vcc + 0.5V Changed tSTORE to 15ms Changed tPWE to 10ns Changed tSCE to 15ns Changed tSD to 5ns Changed tAW to 10ns Removed tHLBL Added Timing Parameters for BHE and BLE - tDBE, tLZBE, tHZBE, tBW Removed min specification for Vswitch Changed tGLAX to 1ns Added tDELAY max of 70us Changed tSS specification from 70us min to 70us max Changed the data sheet from Advance information to Preliminary 48 FBGA package code changed from BV to BA Removed 48 FBGA package in X8 configuration in ordering information. Changed tDBE to 10ns in 15ns part Changed tHZBE in 15ns part to 7ns and in 25ns part to10ns Changed tBW in 15ns part to 15ns and in 25ns part to 20ns Changed tGLAX to tGHAX Changed the value of ICC3 to 25mA Changed the value of tAW in 15ns part to15ns Changed A18 and A19 Pins in FBGA Pin Configuration to NC Included all the information for 45 ns part in this data sheet Page 22 of 25 [+] Feedback CY14B104L, CY14B104N Document Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Document Number 001-07102 Submission Date Orig. of Change Description of Change F 1889928 See ECN vsutmp8/AESA Added Footnotes 1, 2 and Updated logic block diagram Added 48-FBGA X8 Pin Diagram Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II x8 . Updated pin definitions table. Corrected typo in VIL min spec Changed the value of ICC3 from 25mA to 13mA Changed ISB value from 1mA to 2mA Rearranging of Footnotes. Updated ordering information table G 2267286 See ECN GVCH/PYRS Added BHE and BLE Information in Pin Definitions Table Updated Figure 4 Autostore mode Updated footnote 6 Changed ICC2 & ICC4 from 3 mA to 6 mA Changed ICC3 from 13 mA to 15 mA Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max value Changed ISB from 2 mA to 3 mA Added input leakage current IIX for HSB in DC Electrical Characteristics table Corrected typo in tDBE value from 22 ns to 20 ns for 45 ns part Corrected typo in tHZBE value from 22 ns to 15 ns for 45 ns part Corrected typo in tAW value from 15 ns to 10ns for 15 ns part Changed tRECALL from 100 to 200 us Added footnotes 9 and 25 Reframed footnote 14 and 21 Added footnote 14 to figure 7 SRAM WRITE Cycle #1 H 2483627 I 2519319 See ECN 06/20/08 GVCH/PYRS GVCH/PYRS Removed 8 mA typical ICC at 200 ns cycle time in Feature section Referenced footnote 8 to ICC3 in DC Characteristics table Changed ICC3 from 15 mA to 35 mA Changed Vcap minimum value from 54 uF to 61 uF Changed tAVAV to tRC Figure 11:Changed tSA to tAS and tSCE to tCW Added 20 ns access speed in “Features” Added ICC1 for tRC=20 ns for both industrial and Commercial temperature Grade updated Thermal resistance table values for 48-FBGA, 44-TSOP II and 54-TSOP II Packages Added AC Switching Characteristics specs for 20 ns access speed Added software controlled STORE/RECALL cycle specs for 20 ns access speed Updated ordering information and part numbering nomenclature Page 23 of 25 [+] Feedback CY14B104L, CY14B104N Document Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Document Number 001-07102 Submission Date Orig. of Change Description of Change J 2600941 11/04/08 GVCH/PYRS Removed 15 ns access speed Updated Logic block diagram Updated footnote 1 Added footnote 2 and 5 Pin definition Updated WE, HSB and NC pin description Page 4:Updated SRAM READ, SRAM WRITE, Autostore operation description Page 4:Updated Hardware store operation and Hardware RECALL Power-up description Footnote 1 referenced for Mode selection Table Page 6:updated Data protection description Maximum Ratings Added Max. Accumulated storage time Changed ICC2 from 6mA to 10mA Changed ICC4 from 6mA to 5mA Changed ISB from 3mA to 5mA Updated ICC1, ICC3 , ISBand IOZ Test conditions Changed VCAP max value from 82uf to 180uF Updated footnote 10 and 11 Added footnote 12 Added Data retention and Endurance Table Updated Input Rise and Fall time in AC test Conditions Referenced footnote 15 to tOHA parameter Updated All switching waveforms Added Figure 10 SRAM WRITE CYCLE:BHE and BLE controlled Changed tDELAY to 20ns, 25ns, 25ns for 15ns, 20ns, 45ns part respectively Changed tSTORE from 15ms to 8ms Added VHDIS, tHHHD and tLZHSB parameters Updated footnote 21 Added footnote 24 Software controlled STORE/RECALL cycle table Changed tAS to tSA Changed tGHAX to tHA Added tDHSB parameter Changed tHLHX to tPHSB Updated tSS from 70us to 100us Added Truth table for SRAM operations Updated ordering information and part numbering nomenclature K 2612931 11/26/08 AESA Removed Preliminary form header. *L 2625431 12/19/08 GVCH/DSG Changed tDELAY to 1us min and 70us max for all three access time Page 4 Removed the text relating to write requested after HSB goes LOW are inhibited. Page 5 modified software store description to indicate no further read/writes permitted for tSS duration after sixth read cycle. Added parameter tPURHH to AutoStore power-Up recall table Updated Figures 11, 12 and Added tHLBL parameter Removed tDHSB parameter Updated Figure 14;Hardware store cycle Changed Simtek trademarks to Cypress Page 24 of 25 [+] Feedback CY14B104L, CY14B104N Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General psoc.cypress.com/solutions Low Power/Low Voltage psoc.cypress.com/low-power Precision Analog psoc.cypress.com/precision-analog LCD Drive psoc.cypress.com/lcd-drive CAN 2.0b psoc.cypress.com/can psoc.cypress.com/usb Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Page 25 of 25 AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders. [+] Feedback

PDF Datasheet Preview

CY14B104L, CY14B104N
4 Mbit 512K x 8/256K x 16 nvSRAM
• 20 ns, 25 ns, and 45 ns Access Times
• Internally organized as 512K x 8 CY14B104L or 256K x 16

CY14B104N
• Hands off Automatic STORE on power down with only a small

Capacitor
• STORE to nonvolatile elements initiated by
software, device pin, or on power down
• RECALL to SRAM initiated by software or power up
• Infinite Read, Write, and Recall Cycles
• 200,000 STORE cycles to QuantumTrap
• 20 year data retention
• Single 3V +20% to operation
• Commercial and Industrial Temperatures
• 48-ball FBGA and 44/54-pin TSOP II packages
• Pb-free and RoHS compliance

Functional Description

The Cypress CY14B104L/CY14B104N is a fast static RAM, with a nonvolatile element in each memory cell. The memory is organized as 512K bytes of 8 bits each or 256K words of 16 bits each. The embedded nonvolatile elements incorporate QuantumTrap technology, producing the world’s most reliable nonvolatile memory. The SRAM provides infinite read and write cycles, while independent nonvolatile data resides in the highly reliable QuantumTrap cell. Data transfers from the SRAM to the nonvolatile elements the STORE operation takes place automatically at power down. On power up, data is restored to the SRAM the RECALL operation from the nonvolatile memory. Both the STORE and RECALL operations are also available under software control.

Logic Block Diagram[1, 2, 3]
6725
&21752/
&21752/
' 7 &7

Notes Address A0 - A18 for x8 configuration and Address A0 - A17 for x16 configuration. Data DQ0 - DQ7 for x8 configuration and Data DQ0 - DQ15 for x16 configuration. BHE and BLE are applicable for x16 configuration only.
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

CY14B104L, CY14B104N

Pinouts

Figure Pin Diagram - 48 FBGA
48-FBGA x8

Top View not to scale
48-FBGA x16

Top View not to scale

NC OE A0 A1 A2 NC

A4 CE NC

DQ0 NC A5 A6 NC DQ4

VSS DQ1 A17 A7 DQ5 VCC

VCC DQ2 VCAP A16 DQ6 VSS

DQ3 NC A14 A15 NC DQ7

NC[5] HSB A12 A13 WE NC

A18 A8
[4] NC

BLE OE A0 A1 A2 NC

DQ8 BHE A3 A4 CE DQ0

DQ9 DQ10 A5

A6 DQ1 DQ2

VSS DQ11 A17 A7 DQ3 VCC

VCC DQ12 VCAP A16 DQ4 VSS

DQ14 DQ13 A14 A15 DQ5 DQ6

DQ15 HSB A12 A13 WE DQ7
[4] NC
Ordering Information

Speed ns
Ordering Code
20 CY14B104L-ZS20XCT

CY14B104L-ZS20XIT

CY14B104L-ZS20XI

CY14B104L-BA20XCT

CY14B104L-BA20XIT

CY14B104L-BA20XI

CY14B104L-ZSP20XCT

CY14B104L-ZSP20XIT

CY14B104L-ZSP20XI

CY14B104N-ZS20XCT

CY14B104N-ZS20XIT

CY14B104N-ZS20XI

CY14B104N-BA20XCT

CY14B104N-BA20XIT

CY14B104N-BA20XI

CY14B104N-ZSP20XCT

CY14B104N-ZSP20XIT

CY14B104N-ZSP20XI
25 CY14B104L-ZS25XCT

CY14B104L-ZS25XIT

CY14B104L-ZS25XI

CY14B104L-BA25XIT

CY14B104L-BA25XI

CY14B104N-BA25XCT

CY14B104L-ZSP25XCT

CY14B104L-ZSP25XIT

CY14B104L-ZSP25XI

CY14B104N-ZS25XCT

CY14B104N-ZS25XIT

CY14B104N-ZS25XI

CY14B104N-BA25XCT

CY14B104N-BA25XIT

CY14B104N-BA25XI

CY14B104N-ZSP25XCT

CY14B104N-ZSP25XIT

CY14B104N-ZSP25XI

CY14B104L, CY14B104N

Package Diagram 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160 51-85087 51-85087 51-85087 51-85128 51-85128 51-85128 51-85160 51-85160 51-85160

Package Type
44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II 44-pin TSOP II 44-pin TSOP II 44-pin TSOP II 48-ball FBGA 48-ball FBGA 48-ball FBGA 54-pin TSOP II 54-pin TSOP II 54-pin TSOP II
Ordering Information continued

Speed ns
Ordering Code

Package Diagram

Package Type

Operating Range
45 CY14B104L-ZS45XCT
51-85087 44-pin TSOP II

Commercial

CY14B104L-ZS45XIT
51-85087 44-pin TSOP II

Industrial

CY14B104L-ZS45XI
51-85087 44-pin TSOP II

CY14B104L-BA45XCT
51-85128 48-ball FBGA

Commercial

CY14B104L-BA45XIT
51-85128 48-ball FBGA

Industrial

CY14B104L-BA45XI
51-85128 48-ball FBGA

CY14B104L-ZSP45XCT
51-85160 54-pin TSOP II

Commercial

CY14B104L-ZSP45XIT
51-85160 54-pin TSOP II

Industrial

CY14B104L-ZSP45XI
51-85160 54-pin TSOP II

CY14B104N-ZS45XCT
51-85087 44-pin TSOP II

Commercial

CY14B104N-ZS45XIT
51-85087 44-pin TSOP II

Industrial

CY14B104N-ZS45XI
51-85087 44-pin TSOP II

CY14B104N-BA45XCT
51-85128 48-ball FBGA

Commercial

CY14B104N-BA45XIT
51-85128 48-ball FBGA
Removed 48 SSOP Package Added 48 FBGA and 54 TSOPII Packages Updated Part Numbering Nomenclature and Ordering Information Added Soft Sequence Processing Time Waveform
*B 499597

See ECN

Removed 35 ns speed bin

Added 55 ns speed bin. Updated AC table for the same

Changed “Unlimited” read/write to “infinite” read/write

Features section Changed typical ICC at 200-ns cycle time to 8 mA Changed STORE cycles from 500K to 200K cycles

Shaded Commercial grade in operating range table

Modified Icc/Is specs
48 FBGA package nomenclature changed from BW to BV
Modified part nomenclature table. Changes reflected in ordering information
table
*C 517793

See ECN
*D 774001

See ECN
*E 914220

See ECN

Removed 55ns speed bin Changed pinout for 44TSOPII and 54TSOPII packages Changed ISB to 1mA Changed ICC4 to 3mA Changed VCAP min to 35uF Changed VIH max to Vcc + 0.5V Changed tSTORE to 15ms Changed tPWE to 10ns Changed tSCE to 15ns Changed tSD to 5ns Changed tAW to 10ns Removed tHLBL Added Timing Parameters for BHE and BLE - tDBE, tLZBE, tHZBE, tBW Removed min specification for Vswitch Changed tGLAX to 1ns Added tDELAY max of 70us Changed tSS specification from 70us min to 70us max
Changed the data sheet from Advance information to Preliminary 48 FBGA package code changed from BV to BA Removed 48 FBGA package in X8 configuration in ordering information. Changed tDBE to 10ns in 15ns part Changed tHZBE in 15ns part to 7ns and in 25ns part to10ns Changed tBW in 15ns part to 15ns and in 25ns part to 20ns Changed tGLAX to tGHAX Changed the value of ICC3 to 25mA Changed the value of tAW in 15ns part to15ns Changed A18 and A19 Pins in FBGA Pin Configuration to NC

Included all the information for 45 ns part in this data sheet

Page 22 of 25 [+] Feedback

CY14B104L, CY14B104N

Document Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Document Number 001-07102

Submission Date

Orig. of Change

Description of Change
*F 1889928

See ECN
vsutmp8/AESA
Added Footnotes 1, 2 and Updated logic block diagram Added 48-FBGA X8 Pin Diagram Changed 8Mb Address expansion Pin from Pin 43 to Pin 42 for 44-TSOP II x8 . Updated pin definitions table. Corrected typo in VIL min spec Changed the value of ICC3 from 25mA to 13mA Changed ISB value from 1mA to 2mA Rearranging of Footnotes. Updated ordering information table
*G 2267286

See ECN

GVCH/PYRS

Added BHE and BLE Information in Pin Definitions Table Updated Figure 4 Autostore mode Updated footnote 6 Changed ICC2 & ICC4 from 3 mA to 6 mA Changed ICC3 from 13 mA to 15 mA Changed Vcap from 35uF min and 57uF max value to 54uF min and 82uF max value Changed ISB from 2 mA to 3 mA Added input leakage current IIX for HSB in DC Electrical Characteristics table Corrected typo in tDBE value from 22 ns to 20 ns for 45 ns part Corrected typo in tHZBE value from 22 ns to 15 ns for 45 ns part Corrected typo in tAW value from 15 ns to 10ns for 15 ns part Changed tRECALL from 100 to 200 us Added footnotes 9 and 25 Reframed footnote 14 and 21 Added footnote 14 to figure 7 SRAM WRITE Cycle #1
*H 2483627 *I 2519319

See ECN 06/20/08

GVCH/PYRS GVCH/PYRS

Removed 8 mA typical ICC at 200 ns cycle time in Feature section Referenced footnote 8 to ICC3 in DC Characteristics table Changed ICC3 from 15 mA to 35 mA Changed Vcap minimum value from 54 uF to 61 uF Changed tAVAV to tRC Figure 11:Changed tSA to tAS and tSCE to tCW
Added 20 ns access speed in “Features” Added ICC1 for tRC=20 ns for both industrial and Commercial temperature Grade updated Thermal resistance table values for 48-FBGA, 44-TSOP II and 54-TSOP II Packages Added AC Switching Characteristics specs for 20 ns access speed Added software controlled STORE/RECALL cycle specs for 20 ns access speed Updated ordering information and part numbering nomenclature

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CY14B104L, CY14B104N

Document Title CY14B104L/CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Document Number 001-07102

Submission Date

Orig. of Change

Description of Change
*J 2600941
11/04/08

GVCH/PYRS
Removed 15 ns access speed Updated Logic block diagram Updated footnote 1 Added footnote 2 and 5 Pin definition Updated WE, HSB and NC pin description Page 4:Updated SRAM READ, SRAM WRITE, Autostore operation description Page 4:Updated Hardware store operation and Hardware RECALL Power-up description Footnote 1 referenced for Mode selection Table Page 6:updated Data protection description Maximum Ratings Added Max. Accumulated storage time Changed ICC2 from 6mA to 10mA Changed ICC4 from 6mA to 5mA Changed ISB from 3mA to 5mA Updated ICC1, ICC3 , ISBand IOZ Test conditions Changed VCAP max value from 82uf to 180uF Updated footnote 10 and 11 Added footnote 12 Added Data retention and Endurance Table Updated Input Rise and Fall time in AC test Conditions Referenced footnote 15 to tOHA parameter Updated All switching waveforms Added Figure 10 SRAM WRITE CYCLE:BHE and BLE controlled Changed tDELAY to 20ns, 25ns, 25ns for 15ns, 20ns, 45ns part respectively Changed tSTORE from 15ms to 8ms Added VHDIS, tHHHD and tLZHSB parameters Updated footnote 21 Added footnote 24 Software controlled STORE/RECALL cycle table Changed tAS to tSA Changed tGHAX to tHA Added tDHSB parameter Changed tHLHX to tPHSB Updated tSS from 70us to 100us Added Truth table for SRAM operations Updated ordering information and part numbering nomenclature
*K 2612931 11/26/08

AESA

Removed Preliminary form header.
*L 2625431 12/19/08

GVCH/DSG

Changed tDELAY to 1us min and 70us max for all three access time Page 4 Removed the text relating to write requested after HSB goes LOW are inhibited. Page 5 modified software store description to indicate no further read/writes permitted for tSS duration after sixth read cycle. Added parameter tPURHH to AutoStore power-Up recall table Updated Figures 11, 12 and Added tHLBL parameter Removed tDHSB parameter Updated Figure 14;Hardware store cycle Changed Simtek trademarks to Cypress

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CY14B104L, CY14B104N

Sales, Solutions, and Legal Information

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Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

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Page 25 of 25

AutoStore and QuantumTrap are registered trademarks of Cypress Semiconductor Corporation. All products and company names mentioned in this document are the trademarks of their respective holders.
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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY14B104N-BA20XIT Datasheet file may be downloaded here without warranties.

Datasheet ID: CY14B104N-BA20XIT 507657