CYV15G0402DXB-BGC

CYV15G0402DXB-BGC Datasheet

CYP15G0402DXB CYV15G0402DXB

Part	Datasheet
CYV15G0402DXB-BGC	CYV15G0402DXB-BGC (pdf)

Related Parts	Information
CYP15G0402DX-EVAL	CYP15G0402DX-EVAL
CYP15G0402DXB-BGC	CYP15G0402DXB-BGC

PDF Datasheet Preview
CYP15G0402DXB CYV15G0402DXB Quad HOTLink II SERDES • Second-generation technology • Compliant to multiple standards Fibre Channel, Gigabit Ethernet IEEE802.3z , and DVB-ASI CYV15G0402DXB compliant to SMPTE 259M and SMPTE 292M • Quad-channel transceiver operates from 195 to 1500 Mbps serial data rate Aggregate throughput of 12 Gbps • 10-bit unencoded data transport • Selectable parity check/generate • Four independent 10-bit channels with separate Clock and Data Recovery for each channel • Selectable input clocking options • MultiFrame Receive Framer Comma or full K28.5 detect Single or Multi-Byte framer for byte alignment Low-latency option • Synchronous LVTTL parallel interface • Internal phase-locked loops PLLs with no external PLL components • Optional Phase Align Buffer in Transmit Path • Differential PECL-compatible serial inputs • Differential PECL-compatible serial outputs Source matched for transmission lines No external resistors required Signaling rate controlled edge rates • Compatible with Fiber-optic modules Copper cables Circuit board traces • JTAG boundary scan • Built-In Self-Test BIST for at-speed link testing • Per-channel Link Quality Indicator Analog signal detect Digital signal detect • Low-power 2.5W typical • Single 3.3V supply • 256-ball thermally enhanced BGA • Pb-Free package option available • BiCMOS technology Functional Description The CYP V 15G0402DXB[1] Quad HOTLink II SERDES is a point-to-point communications building block allowing the transfer of preencoded data over high-speed serial links optical fiber, balanced, and unbalanced copper transmission lines at signaling speeds ranging from 195 to 1500 MBaud per serial link. Each transmit channel accepts preencoded 10-bit transmission characters in an Input Register, serializes each character, and drives it out a PECL-compatible differential line driver. Each receive channel accepts a serial data stream at a differential line receiver, deserializes the stream into 10-bit characters, optionally frames these characters to the proper 10-bit character boundaries and presents these characters to an Output register. Figure 1 illustrates typical connections between independent systems and a CYP V 15G0402DXB. The CYV15G0402DXB satisfies the SMPTE-259M and SMPTE-292M compliance as per the EG34-1999 Pathological Test Requirements. CYP V 15G0402DXB System Host With Encoder/Decoder System Host With Encoder/Decoder Serial Links Serial Links Independent Channel Transceiver Independent Channel Transceiver Serial Links Independent Channel Transceiver Independent Serial Links Channel Cable or Transceiver Ordering Information Speed Standard Ordering Code CYP15G0402DXB-BGC CYP15G0402DXB-BGI CYV15G0402DXB-BGC CYV15G0402DXB-BGI CYP15G0402DXB-BGXC CYP15G0402DXB-BGXI CYV15G0402DXB-BGXC CYV15G0402DXB-BGXI Package Name BL256 Package Type 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array Pb-Free 256-ball Thermally Enhanced Ball Grid Array Pb-Free 256-ball Thermally Enhanced Ball Grid Array Pb-Free 256-ball Thermally Enhanced Ball Grid Array Pb-Free 256-ball Thermally Enhanced Ball Grid Array Package Diagram Operating Range Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial 256-lead L2 Ball Grid Array 27 x 27 x mm BL256 51-85123-*E HOTLink is a registered trademark, and HOTLink II and MultiFrame are trademarks, of Cypress Semiconductor Corporation. ESCON is a registered trademark of International Business Machines. All product and company names mentioned in this document are the trademarks of their respective holders. Page 28 of 29 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. [+] Feedback CYP15G0402DXB CYV15G0402DXB Document History Page Document Title:CYP V 15G0402DXB Quad HOTLink II SERDES Document Number 38-02057 Orig. of ECN NO. Issue Date Change Description of Change 116285 07/16/02 SDR New Data Sheet 118985 09/30/02 LNM Changed TXCLKO description Changed TXPERx description introduced SMPTE pathological test clause Removed the LOW setting for FRAMCHAR and related references Changed VODIF and VOLC for CML output Changed the IOST boundary values Changed the tTXCLKR and tTXCLKF min values Changed tTXDS and tTXDH and tTREFDS and tTREFDH Changed and tREFCDV+ Changed the JTAG ID from 0C801069 to 1C801069 122545 12/09/02 CGX Changed Minimum tRISE/tFALL for CML Changed tTXCLKOD+, tTXCLKOD- for LVTTL Changed tRXLOCK Changed tDJ, tRJ Changed tJTOL Changed tTXLOCK Changed tRXCLKH, tRXCLKL Changed Power Specs Changed verbiage...Paragraph Clock/Data Recovery Changed verbiage...Paragraph Range Control Updated differences to pin configuration and pin table Added Power-up Requirements 122211 12/28/02 RBI Minor change Document Control corrected Document History Page 124992 04/15/03 POT Changed CYP15G0402DXB to CYP V 15G0402DXB type corresponding to

PDF Datasheet Preview

CYP15G0402DXB CYV15G0402DXB

Quad HOTLink II SERDES
• Second-generation technology
• Compliant to multiple standards

Fibre Channel, Gigabit Ethernet IEEE802.3z , and DVB-ASI

CYV15G0402DXB compliant to SMPTE 259M and SMPTE 292M
• Quad-channel transceiver operates from 195 to 1500 Mbps serial data rate Aggregate throughput of 12 Gbps
• 10-bit unencoded data transport
• Selectable parity check/generate
• Four independent 10-bit channels with separate Clock
and Data Recovery for each channel
• Selectable input clocking options
• MultiFrame Receive Framer

Comma or full K28.5 detect

Single or Multi-Byte framer for byte alignment

Low-latency option
• Synchronous LVTTL parallel interface
• Internal phase-locked loops PLLs with no external

PLL components
• Optional Phase Align Buffer in Transmit Path
• Differential PECL-compatible serial inputs
• Differential PECL-compatible serial outputs

Source matched for transmission lines

No external resistors required

Signaling rate controlled edge rates
• Compatible with

Fiber-optic modules

Copper cables

Circuit board traces
• JTAG boundary scan
• Built-In Self-Test BIST for at-speed link testing
• Per-channel Link Quality Indicator

Analog signal detect

Digital signal detect
• Low-power 2.5W typical
• Single 3.3V supply
• 256-ball thermally enhanced BGA
• Pb-Free package option available
• BiCMOS technology

Functional Description

The CYP V 15G0402DXB[1] Quad HOTLink II SERDES is a point-to-point communications building block allowing the transfer of preencoded data over high-speed serial links optical fiber, balanced, and unbalanced copper transmission lines at signaling speeds ranging from 195 to 1500 MBaud per serial link.

Each transmit channel accepts preencoded 10-bit transmission characters in an Input Register, serializes each character, and drives it out a PECL-compatible differential line driver. Each receive channel accepts a serial data stream at a differential line receiver, deserializes the stream into 10-bit characters, optionally frames these characters to the proper 10-bit character boundaries and presents these characters to an Output register. Figure 1 illustrates typical connections between independent systems and a CYP V 15G0402DXB.

The CYV15G0402DXB satisfies the SMPTE-259M and SMPTE-292M compliance as per the EG34-1999 Pathological Test Requirements.

CYP V 15G0402DXB

System Host With Encoder/Decoder System Host With Encoder/Decoder

Serial Links Serial Links

Independent Channel

Transceiver

Independent Channel

Transceiver

Serial Links

Independent Channel

Transceiver

Independent

Serial Links

Channel

Cable or

Transceiver
Ordering Information

Speed Standard
Ordering Code CYP15G0402DXB-BGC CYP15G0402DXB-BGI CYV15G0402DXB-BGC CYV15G0402DXB-BGI CYP15G0402DXB-BGXC CYP15G0402DXB-BGXI CYV15G0402DXB-BGXC CYV15G0402DXB-BGXI

Package Name BL256

Package Type 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array 256-ball Thermally Enhanced Ball Grid Array Pb-Free 256-ball Thermally Enhanced Ball Grid Array Pb-Free 256-ball Thermally Enhanced Ball Grid Array Pb-Free 256-ball Thermally Enhanced Ball Grid Array Pb-Free 256-ball Thermally Enhanced Ball Grid Array

Package Diagram

Operating Range

Commercial Industrial Commercial Industrial Commercial Industrial Commercial Industrial
256-lead L2 Ball Grid Array 27 x 27 x mm BL256
51-85123-*E

HOTLink is a registered trademark, and HOTLink II and MultiFrame are trademarks, of Cypress Semiconductor Corporation. ESCON is a registered trademark of International Business Machines. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 28 of 29

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
[+] Feedback

CYP15G0402DXB CYV15G0402DXB

Document History Page

Document Title:CYP V 15G0402DXB Quad HOTLink II SERDES Document Number 38-02057

Orig. of ECN NO. Issue Date Change

Description of Change
116285 07/16/02

SDR New Data Sheet
118985 09/30/02

LNM Changed TXCLKO description

Changed TXPERx description
introduced SMPTE pathological test clause

Removed the LOW setting for FRAMCHAR and related references

Changed VODIF and VOLC for CML output Changed the IOST boundary values Changed the tTXCLKR and tTXCLKF min values Changed tTXDS and tTXDH and tTREFDS and tTREFDH Changed and tREFCDV+ Changed the JTAG ID from 0C801069 to 1C801069
122545 12/09/02 CGX Changed Minimum tRISE/tFALL for CML

Changed tTXCLKOD+, tTXCLKOD- for LVTTL

Changed tRXLOCK

Changed tDJ, tRJ

Changed tJTOL

Changed tTXLOCK

Changed tRXCLKH, tRXCLKL

Changed Power Specs

Changed verbiage...Paragraph Clock/Data Recovery

Changed verbiage...Paragraph Range Control

Updated differences to pin configuration and pin table

Added Power-up Requirements
122211 12/28/02

RBI Minor change Document Control corrected Document History Page
124992 04/15/03

POT Changed CYP15G0402DXB to CYP V 15G0402DXB type corresponding to

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CYV15G0402DXB-BGC Datasheet file may be downloaded here without warranties.

Datasheet ID: CYV15G0402DXB-BGC 507654