74ABT899CSCX

74ABT899CSCX Datasheet

74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker

Part	Datasheet
74ABT899CSCX	74ABT899CSCX (pdf)

Related Parts	Information
74ABT899CQC	74ABT899CQC
74ABT899CSC	74ABT899CSC
74ABT899CQCX	74ABT899CQCX
74ABT899CMSAX	74ABT899CMSAX
74ABT899CMSA	74ABT899CMSA

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74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker 74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker The ABT899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction. The ABT899 features independent latch enables for the Ato-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity. s Latchable transceiver with output sink of 64 mA s Option to select generate parity and check or “feed-through” data/parity in directions A-to-B or B-to-A s Independent latch enables for A-to-B and B-to-A directions s Select pin for ODD/EVEN parity s ERRA and ERRB output pins for parity checking s Ability to simultaneously generate and check parity s May be used in systems applications in place of the 543 and 280 s May be used in system applications in place of the 657 and 373 no need to change T/R to check parity s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and 250 pF loads s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire power up and power down cycle s Nondestructive hot insertion capability s Disable time less than enable time to avoid bus contention Ordering Code: Order Number Package Number Package Description 74ABT899CSC M28B 28-Lead Small Outline Integrated Circuit SOIC , MS-013, Wide Body 74ABT899CMSA MSA28 28-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide 74ABT899CQC V28A 28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagrams Pin Assignment for PLCC Pin Assignment for SOIC and SSOP 1999 Fairchild Semiconductor Corporation DS011509.prf 74ABT899 Pin Descriptions Pin Names Descriptions APAR, BPAR A Bus Data Inputs/Data Outputs B Bus Data Inputs/Data Outputs A and B Bus Parity Inputs/Outputs ODD/EVEN ODD/EVEN Parity Select, Active LOW for EVEN Parity GBA, GAB Output Enables for A or B Bus, Active LOW Select Pin for Feed-Through or Generate Mode, LOW for Generate Mode LEA, LEB Latch Enables for A and B Latches, HIGH for Transparent Mode ERRA, ERRB Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs Functional Description The ABT899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-B and B-to-A directions. • Bus A B communicates to Bus B A , parity is generated and passed on to the B A Bus as BPAR APAR . If LEB LEA is HIGH and the Mode Select SEL is LOW, the parity generated from B[0:7] A[0:7] can be checked and monitored by ERRB ERRA . • Bus A B communicates to Bus B A in a feed-through mode if SEL is HIGH. Parity is still generated and checked as ERRA and ERRB in the feed-through mode can be used as an interrupt to signal a data/parity bit error to the CPU . • Independent Latch Enables LEA and LEB allow other permutations of generating/checking see Function Table below . Function Table Inputs Operation GAB GBA SEL LEA LEB H X Busses A and B are 3-STATE. H L H Generates parity from B[0:7] based on O/E Note Generated parity APAR. Generated parity checked against BPAR and output as ERRB. H L H Generates parity from B[0:7] based on O/E. Generated parity APAR. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. H L X L Generates parity from B latch data based on O/E. Generated parity APAR. Generated parity checked against latched BPAR and output as ERRB. H L H X H BPAR/B[0:7] APAR/A0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. H L H BPAR/B[0:7] APAR/A[0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA. L H L H L Generates parity for A[0:7] based on O/E. Generated parity BPAR. Generated parity checked against APAR and output as ERRA. L H L H Generates parity from A[0:7] based on O/E. Generated parity BPAR. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB. L H L X Generates parity from A latch data based on O/E. Generated parity BPAR. Generated parity checked against latched APAR and output as ERRA. L H L APAR/A[0:7] BPAR/B[0:7] Feed-through mode. Generated parity checked against APAR and output as ERRA.

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74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker
74ABT899 9-Bit Latchable Transceiver with Parity Generator/Checker

The ABT899 is a 9-bit to 9-bit parity transceiver with transparent latches. The device can operate as a feed-through transceiver or it can generate/check parity from the 8-bit data busses in either direction.

The ABT899 features independent latch enables for the Ato-B direction and the B-to-A direction, a select pin for ODD/EVEN parity, and separate error signal output pins for checking parity.
s Latchable transceiver with output sink of 64 mA s Option to select generate parity and check or
“feed-through” data/parity in directions A-to-B or B-to-A s Independent latch enables for A-to-B and B-to-A
directions s Select pin for ODD/EVEN parity s ERRA and ERRB output pins for parity checking
s Ability to simultaneously generate and check parity s May be used in systems applications in place of the
543 and 280 s May be used in system applications in place of the
657 and 373 no need to change T/R to check parity s Guaranteed output skew s Guaranteed multiple output switching specifications s Output switching specified for both 50 pF and
250 pF loads s Guaranteed simultaneous switching noise level and
dynamic threshold performance s Guaranteed latchup protection s High impedance glitch free bus loading during entire
power up and power down cycle s Nondestructive hot insertion capability s Disable time less than enable time to avoid bus
contention
Ordering Code:

Order Number Package Number

Package Description
74ABT899CSC

M28B
28-Lead Small Outline Integrated Circuit SOIC , MS-013, Wide Body
74ABT899CMSA

MSA28
28-Lead Shrink Small Outline Package SSOP , EIAJ TYPE II, 5.3mm Wide
74ABT899CQC

V28A
28-Lead Plastic Lead Chip Carrier PLCC , JEDEC MO-047, Square
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Connection Diagrams

Pin Assignment for PLCC

Pin Assignment for SOIC and SSOP
1999 Fairchild Semiconductor Corporation DS011509.prf
74ABT899

Pin Descriptions

Pin Names

Descriptions

APAR, BPAR

A Bus Data Inputs/Data Outputs B Bus Data Inputs/Data Outputs A and B Bus Parity Inputs/Outputs

ODD/EVEN ODD/EVEN Parity Select, Active LOW for EVEN Parity

GBA, GAB

Output Enables for A or B Bus, Active LOW

Select Pin for Feed-Through or

Generate Mode, LOW for Generate

Mode

LEA, LEB

Latch Enables for A and B Latches, HIGH for Transparent Mode

ERRA, ERRB Error Signals for Checking Generated Parity with Parity In, LOW if Error Occurs

Functional Description

The ABT899 has three principal modes of operation which are outlined below. These modes apply to both the A-to-B and B-to-A directions.
• Bus A B communicates to Bus B A , parity is generated and passed on to the B A Bus as BPAR APAR . If LEB LEA is HIGH and the Mode Select SEL is LOW, the parity generated from B[0:7] A[0:7] can be checked and monitored by ERRB ERRA .
• Bus A B communicates to Bus B A in a feed-through mode if SEL is HIGH. Parity is still generated and checked as ERRA and ERRB in the feed-through mode can be used as an interrupt to signal a data/parity bit error to the CPU .
• Independent Latch Enables LEA and LEB allow other permutations of generating/checking see Function Table below .

Function Table

Inputs

Operation

GAB GBA SEL LEA LEB

H X Busses A and B are 3-STATE.

H L H Generates parity from B[0:7] based on O/E Note Generated parity APAR. Generated parity checked against BPAR and output as ERRB.

H L H Generates parity from B[0:7] based on O/E. Generated parity APAR. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA.

H L X L Generates parity from B latch data based on O/E. Generated parity APAR. Generated parity checked against latched BPAR and output as ERRB.

H L H X H BPAR/B[0:7] APAR/A0:7] Feed-through mode. Generated parity checked against BPAR and output as ERRB.

H L H BPAR/B[0:7] APAR/A[0:7]

Feed-through mode. Generated parity checked against BPAR and output as ERRB. Generated parity also fed back through the A latch for generate/check as ERRA.

L H L H L Generates parity for A[0:7] based on O/E. Generated parity BPAR. Generated parity checked against APAR and output as ERRA.

L H L H Generates parity from A[0:7] based on O/E. Generated parity BPAR. Generated parity checked against APAR and output as ERRA. Generated parity also fed back through the B latch for generate/check as ERRB.

L H L X Generates parity from A latch data based on O/E. Generated parity BPAR. Generated parity checked against latched APAR and output as ERRA.

L H L APAR/A[0:7] BPAR/B[0:7]

Feed-through mode. Generated parity checked against APAR and output as ERRA.

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Datasheet ID: 74ABT899CSCX 513066