CTSLVEL16VVRLG

CTSLVEL16VVRLG Datasheet


CTSLVEL16VV

Part Datasheet
CTSLVEL16VVRLG CTSLVEL16VVRLG CTSLVEL16VVRLG (pdf)
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CTSLVEL16VV

Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable

MLP16

Not recommended for new designs
 Minimizes External Components  Similar Operation as CTSLVEL16VR
except with Selectable Data Input Pairs
 High Bandwidth for  -147 dBc/Hz Typical Noise Floor

BLOCK DIAGRAM

The CTSLVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain output buffer including an enable. Selectable data input pairs permit switching between two different oscillator frequencies. The outputs have a voltage gain several times greater than the Q/ outputs. An enable allows continuous oscillator operation by only controlling the QHG outputs.

The CTSLVEL16VV also provides a reference voltage VBB with internal biasing resistors to each input to minimize external components.

ENGINEERING NOTES

The CTSLVEL16VV is a specialized oscillator gain stage with two selectable data input pairs and a high gain output buffer including an enable. The outputs have a voltage gain several times greater than the outputs.

The CTSLVEL16VV provides two selectable data input pairs that permit switching between two different oscillator frequencies. When the select pin SEL is LOW or open NC data from the is selected. When the SEL pin is HIGH data from the is selected. Allowing continuous oscillator operation, the EN enable works with either data input pair. When EN is HIGH or open NC , input data is passed to both sets of outputs. When EN is LOW, the outputs will be forced LOW/HIGH respectively, while input data will continue to be passed to the outputs. The EN and SEL inputs can be driven with an ECL/PECL signal or a full supply swing CMOS type logic signal.

The CTSLVEL16VV also provides a VBB with a 1.5mA sink/source current. Each data input is separately connected to VBB with a internal bias resistor. Bypassing VBB to ground with a 0.01µF capacitor is recommended.

Each output has a 4mA on-chip pull-down current source. External resistors may also be used to increase pull-down current of the to a maximum of 25mA each includes a 4mA on-chip current source .

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551


Specifications are subject to change without notice. 1

CTSLVEL16VV

Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable

MLP16

Not recommended for new designs

EN High/Open

High/Open Low

CS-SEL Low/Open

High Low/Open

High

Truth Table

High

Timing Diagram

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551


Specifications are subject to change without notice. 2

CTSLVEL16VV

Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable

MLP16

Not recommended for new designs

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551


Specifications are subject to change without notice. 3

CTSLVEL16VV

Dual Frequency PECL/ECL Oscillator Gain Stage & Buffer with Enable

MLP16

Not recommended for new designs
PART ORDERING INFORMATION

Part Number CTSLVEL16VVRLG

Package MLP16

Marking CTSG 16K YYWW

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551


Specifications are subject to change without notice. 8
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Datasheet ID: CTSLVEL16VVRLG 507360