CTSLV394NG

CTSLV394NG Datasheet

CTSLV394

Part	Datasheet
CTSLV394NG	CTSLV394NG (pdf)

PDF Datasheet Preview
CTSLV394 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs MLP8  Selectable Divide Ratio  Selectable Enable Priority and Threshold CMOS or PECL  Tristate Compatible Outputs  Input Buffer Powers Down when Disabled  High BW [1.5GHz ÷1 , 3.0GHz ÷2 ]  3V to 5.5V Power Supply  -145dBc/Hz ÷1 Typ Noise Floor  -151dBc/Hz ÷2 Typ Noise Floor  RoHS Compliant Pb Free Packages BLOCK DIAGRAM The CTSLV394 is a ÷1 or ÷2 clock generation part specifically designed to accommodate Colpitts or Pierce based oscillators. The tri-state compatible outputs allow for on-the-fly switching of multiple oscillators on a common bus. Other features are incorporated to reduce board components. A voltage reference and input biasing allows for easy oscillator interface. The CTSLV394 provides a ÷ 2 mode of operation for more frequency options and is selectable with a single connection. A selectable enable is also provided which doubles as a reset when the CTSLV394 is in ÷2 mode. With a single connection, the enable can be selected to operate as active high or active low. ENGINEERING NOTES The CTSLV394 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open NC , the CTSLV394 functions as a standard receiver. If DIV-SEL is connected to VEE, it functions as a ÷2 divider. Enable EN functionality is selected with the EN-SEL pin/pad which has three valid states open NC , VEE, or connected to VEE via a ± 20% resistor. Leaving EN-SEL open or connecting it to VEE allows the EN pin/pad to function as an active high CMOS/TTL enable. When EN-SEL is open, an internal pull-up resistor is selected which enables the outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal pull-down resistor is selected which disables the outputs whenever EN is left open. Connecting the EN-SEL to VEE with a resistor will allow the EN pin/pad to function as an active low PECL/ECL enable with an internal pull-down resistor. In this mode, outputs are enabled when EN is left open NC . The default logic condition can be overridden by connecting the EN to VCC with an external resistor of If the enable signal is CMOS rail-to-rail and the logic sense is active low EN-SEL connected to VEE with a resistor , the EN pin/pad voltage swing must be reduced using two external resistors. Contact the factory for details. When the CTSLV394 is disabled, the Q and outputs are forced LOW and the input buffer is powered down to minimize feed through. This feature allows tri-state compatible parallel output connections. Multiple CTSLV394 chip outputs can be wired together. Since both outputs are forced LOW in the disable mode, an enabled CTSLV394 can drive the output lines without interference from the unselected units. In addition, the CTSLV394 can be used in parallel connection with PECL/ECL parts whose outputs are high impedance when disabled. The EN pin/pad also functions as a reset when the ÷2 mode is selected. In the ÷2 mode, the counter resets when the outputs are disabled. The CTSLV394 provides a VBB with an internal bias resistor from D to VBB. This feature allows AC coupling with minimal external components. The VBB pin supports 1.5mA sink/source current and should be bypassed to ground or VCC with a capacitor. North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice 1 CTSLV394 LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs MLP8 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings are those values beyond which device life may be impaired. Symbol VCC VI_PECL VEE VI_ECL IHGOUT TA TSTG ESDHBM ESDMM ESDCDM Characteristic PECL Power Supply PECL Input Voltage ECL Power Supply ECL Input Supply Output Current Operating Temperature Range Storage Temperature Range Human Body Model Electro Static Discharge Machine Model Electro Static Discharge Charged Device Model Electro Static Discharge Condition VEE = 0V VEE = 0V VCC = 0V VCC = 0V Continuous Surge - Rating Unit 0 to + V 0 to + V 50 100 -40 to +85 °C -65 to +150 °C 2500 2000 Symbol VOH VOL VBB IIH PART ORDERING INFORMATION CTSLV394NG Package MLP8 Marking J4G / YWW North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice 6

PDF Datasheet Preview

CTSLV394

LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs

MLP8
 Selectable Divide Ratio  Selectable Enable Priority and Threshold

CMOS or PECL  Tristate Compatible Outputs  Input Buffer Powers Down when Disabled  High BW [1.5GHz ÷1 , 3.0GHz ÷2 ]  3V to 5.5V Power Supply  -145dBc/Hz ÷1 Typ Noise Floor  -151dBc/Hz ÷2 Typ Noise Floor  RoHS Compliant Pb Free Packages

BLOCK DIAGRAM

The CTSLV394 is a ÷1 or ÷2 clock generation part specifically designed to accommodate Colpitts or Pierce based oscillators. The tri-state compatible outputs allow for on-the-fly switching of multiple oscillators on a common bus. Other features are incorporated to reduce board components. A voltage reference and input biasing allows for easy oscillator interface.

The CTSLV394 provides a ÷ 2 mode of operation for more frequency options and is selectable with a single connection. A selectable enable is also provided which doubles as a reset when the CTSLV394 is in ÷2 mode. With a single connection, the enable can be selected to operate as active high or active low.

ENGINEERING NOTES

The CTSLV394 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open NC , the CTSLV394 functions as a standard receiver. If DIV-SEL is connected to VEE, it functions as a ÷2 divider.

Enable EN functionality is selected with the EN-SEL pin/pad which has three valid states open NC , VEE, or connected to VEE via a ± 20% resistor. Leaving EN-SEL open or connecting it to VEE allows the EN pin/pad to function as an active high CMOS/TTL enable. When EN-SEL is open, an internal pull-up resistor is selected which enables the outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal pull-down resistor is selected which disables the outputs whenever EN is left open.

Connecting the EN-SEL to VEE with a resistor will allow the EN pin/pad to function as an active low PECL/ECL enable with an internal pull-down resistor. In this mode, outputs are enabled when EN is left open NC . The default logic condition can be overridden by connecting the EN to VCC with an external resistor of If the enable signal is CMOS rail-to-rail and the logic sense is active low EN-SEL connected to VEE with a resistor , the EN pin/pad voltage swing must be reduced using two external resistors. Contact the factory for details.

When the CTSLV394 is disabled, the Q and outputs are forced LOW and the input buffer is powered down to minimize feed through. This feature allows tri-state compatible parallel output connections. Multiple CTSLV394 chip outputs can be wired together. Since both outputs are forced LOW in the disable mode, an enabled CTSLV394 can drive the output lines without interference from the unselected units. In addition, the CTSLV394 can be used in parallel connection with PECL/ECL parts whose outputs are high impedance when disabled.

The EN pin/pad also functions as a reset when the ÷2 mode is selected. In the ÷2 mode, the counter resets when the outputs are disabled.

The CTSLV394 provides a VBB with an internal bias resistor from D to VBB. This feature allows AC coupling with minimal external components. The VBB pin supports 1.5mA sink/source current and should be bypassed to ground or VCC with a capacitor.

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice 1

CTSLV394

LVPECL Divide by 1, Divide by 2 Clock Generator w/ Tri-State Compatible Outputs

MLP8

ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings are those values beyond which device life may be impaired.

Symbol VCC

VI_PECL VEE VI_ECL

IHGOUT

TA TSTG ESDHBM ESDMM ESDCDM

Characteristic PECL Power Supply PECL Input Voltage ECL Power Supply ECL Input Supply

Output Current

Operating Temperature Range Storage Temperature Range Human Body Model Electro Static Discharge Machine Model Electro Static Discharge Charged Device Model Electro Static Discharge

Condition VEE = 0V VEE = 0V VCC = 0V VCC = 0V Continuous

Surge -

Rating Unit
0 to + V
0 to + V
50 100
-40 to +85 °C
-65 to +150 °C
2500
2000

Symbol VOH VOL

VBB IIH
PART ORDERING INFORMATION

CTSLV394NG

Package MLP8

Marking J4G / YWW

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice 6

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CTSLV394NG Datasheet file may be downloaded here without warranties.

Datasheet ID: CTSLV394NG 507356