CTSLV315QG

CTSLV315QG Datasheet

CTSLV315

Part	Datasheet
CTSLV315QG	CTSLV315QG (pdf)

Related Parts	Information
CTSLV315TG	CTSLV315TG

PDF Datasheet Preview
CTSLV315 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator with Gain SON8, MSOP8  2.5V-3.3V Operation  Ultra-Low Phase Noise Floor o LVPECL -167dBc/Hz o LVDS -165dBc/Hz  Configurable o LVPECL or LVDS Output o ÷1 or ÷2 o Enable Active High or Low  1GHz+ Bandwidth  RoHS Compliant Pb Free Packages BLOCK DIAGRAM  The CTSLV315 is a configurable LVPECL, LVDS buffer & translator IC that is optimized for ultra-low phase noise and 2.5V-3.3V nominal supply voltage. It is particularly useful in converting crystal or SAW based oscillators into LVPECL and LVDS outputs for up to 1GHz of bandwidth.  Recommended for applications with signal levels below Vp-p. For applications with higher signal levels that do not require gain, refer to the CTSLV310. CTS encourages the user to try both devices to determine which is best suited for a particular application.  A configurable IC design capable of providing LVPECL or LVDS outputs, ÷1 or ÷2 function, and active high or active low enable selection. See Table 1 for details of the configurations options that provide designers with a single IC buffer/translator solution that is extremely compact, flexible and high performance.  8 configurations which are determined by the static voltage levels of b-0 and b-1. Table 1 details the configurations. Table 1 - Possible IC Configuration Configuration Bits Open Low High Open Low High Open Low High Open Low High Functional Configuration Output Type Enable Polarity Division LVPECL LVDS Not Used Active High Active High Active Low Active Low Active High Active High Active Low Active Low Not Used ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 Not Used North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice. 1 CTSLV315 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator with Gain SON8, MSOP8 Input Termination The D input bias is VDD/2 fed through an internal resistor. For clock applications, an input signal of at least 750m VPP ensures the CTSLV15 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation. LVPECL Output Termination Techniques DC Coupling The LVPECL compatible output stage of the CTSLV315 uses a current drive topology to maximize switching speed as illustrated below. Two current source PMOS transistors M1-M2 feed the output pins. M5 is an NMOS current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This produces an output current of 5.1mA low output state . M3 is off, and the entire 21.1mA flows through the output pin. The associated output voltage swings match LVPECL levels when external resistors terminate the outputs. Both Q and QN should always be terminated identically to avoid waveform distortion and circulating current caused by unsymmetrical loads. This rule should be followed even if only one output is in use. Output Stage Vbp M1 21.1mA 21.1mA External Circuitry 21.1mA - High M4 5.1mA - Low M5 16mA VTT = VDD - 2.0V North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice. 2 CTSLV315 PART ORDERING INFORMATION Part Number CTSLV315QG Package SON8 CTSLV315TG MSOP8 MSOP8 Marking RYW BE5G / YYWW North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice. 7 CTSLV315 Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator with Gain SON8, MSOP8 PACKAGE DIMENSIONS North Americas +1-800-757-6686 • International +1-508-435-6831 • Asia +65-655-17551 • Specifications are subject to change without notice. 8

PDF Datasheet Preview

CTSLV315

Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator with Gain

SON8, MSOP8
 2.5V-3.3V Operation  Ultra-Low Phase Noise Floor
o LVPECL -167dBc/Hz o LVDS -165dBc/Hz  Configurable o LVPECL or LVDS Output o ÷1 or ÷2 o Enable Active High or Low  1GHz+ Bandwidth  RoHS Compliant Pb Free Packages

BLOCK DIAGRAM
 The CTSLV315 is a configurable LVPECL, LVDS buffer & translator IC that is optimized for ultra-low phase noise and 2.5V-3.3V nominal supply voltage. It is particularly useful in converting crystal or SAW based oscillators into LVPECL and LVDS outputs for up to 1GHz of bandwidth.
 Recommended for applications with signal levels below Vp-p. For applications with higher signal levels that do not require gain, refer to the CTSLV310. CTS encourages the user to try both devices to determine which is best suited for a particular application.
 A configurable IC design capable of providing LVPECL or LVDS outputs, ÷1 or ÷2 function, and active high or active low enable selection. See Table 1 for details of the configurations options that provide designers with a single IC buffer/translator solution that is extremely compact, flexible and high performance.
 8 configurations which are determined by the static voltage levels of b-0 and b-1. Table 1 details the configurations.

Table 1 - Possible IC Configuration

Configuration Bits

Open Low High

Open Low High Open Low High Open Low High

Functional Configuration

Output Type Enable Polarity

Division

LVPECL

LVDS Not Used

Active High Active High Active Low Active Low Active High Active High Active Low Active Low Not Used
÷1 ÷2 ÷1 ÷2 ÷1 ÷2 ÷1 ÷2 Not Used

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice. 1

CTSLV315

Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator with Gain

SON8, MSOP8

Input Termination The D input bias is VDD/2 fed through an internal resistor. For clock applications, an input signal of at least 750m VPP ensures the CTSLV15 meets AC specifications. The input should also be AC coupled to maintain a 50% duty cycle on the outputs. The input can be driven to any voltage between 0V and VDD without damage or waveform degradation.

LVPECL Output Termination Techniques DC Coupling The LVPECL compatible output stage of the CTSLV315 uses a current drive topology to maximize switching speed as illustrated below. Two current source PMOS transistors M1-M2 feed the output pins. M5 is an NMOS current source which is switched by M3 and M4. When M4 is on, M5 takes current from M2. This produces an output current of 5.1mA low output state . M3 is off, and the entire 21.1mA flows through the output pin. The associated output voltage swings match LVPECL levels when external resistors terminate the outputs.

Both Q and QN should always be terminated identically to avoid waveform distortion and circulating current caused by unsymmetrical loads. This rule should be followed even if only one output is in use.

Output Stage

Vbp M1
21.1mA
21.1mA

External Circuitry
21.1mA - High

M4 5.1mA - Low

M5 16mA

VTT = VDD - 2.0V

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice. 2

CTSLV315
PART ORDERING INFORMATION

Part Number CTSLV315QG

Package SON8

CTSLV315TG

MSOP8

MSOP8

Marking RYW

BE5G / YYWW

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice. 7

CTSLV315

Ultra-Low Phase Noise LVPECL, LVDS Buffer and Translator with Gain

SON8, MSOP8

PACKAGE DIMENSIONS

North Americas +1-800-757-6686
• International +1-508-435-6831
• Asia +65-655-17551
•

Specifications are subject to change without notice. 8

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CTSLV315QG Datasheet file may be downloaded here without warranties.

Datasheet ID: CTSLV315QG 507351