WM1811AECS/R

WM1811AECS/R Datasheet

WM1811A

Part	Datasheet
WM1811AECS/R	WM1811AECS/R (pdf)

Related Parts	Information
WM1811GECS/R	WM1811GECS/R
CDKWM1811A-S-1	CDKWM1811A-S-1
CRD1700-S-1	CRD1700-S-1
CDBWM1811A-M-1	CDBWM1811A-M-1

PDF Datasheet Preview
WM1811A Multi-Channel Audio Hub CODEC for Smartphones The WM1811A[1] is a highly integrated ultra-low power hi-fi CODEC designed for smartphones and other portable devices rich in multimedia features. An integrated stereo Class D speaker driver and Class W headphone driver minimize power consumption during audio playback. The device requires only two voltage supplies, with all other internal supply rails generated from integrated LDOs. Stereo full duplex asynchronous sample rate conversion and multi-channel digital mixing combined with powerful analogue mixing allow the device to support a huge range of different architectures and use cases. A programmable parametric EQ provides speaker compensation in the digital playback paths. The dynamic range controller can be used in record or playback paths for maintaining a constant signal level, maximizing loudness and protecting speakers against overloading and clipping. A smart digital microphone interface provides power regulation, a low jitter clock output and decimation filters for up to two digital microphones. Microphone activity detection with interrupt is available.Low power jack detection is supported via a dedicated input pin. Impedance sensing and measurement is provided for external accessory / push-button detection. Fully differential internal architecture and on-chip RF noise filters ensure a very high degree of noise immunity. Active ground loop noise rejection and DC offset correction help prevent pop noise and suppress ground noise on the headphone outputs. • 24-bit 2-channel hi-fi DAC and 2-channel hi-fi ADC • 100dB SNR during DAC playback ‘A’ weighted • Smart MIC interface - Power, clocking and data input for up to two digital MICs - High performance analogue MIC interface - MIC activity detect & interrupt allows processor to sleep - Low power jack detection support - Impedance sensing for accessory / push-button detection • 2W stereo 2 x 2W Class D speaker driver • Capless Class W headphone drivers - Integrated charge pump - 5.3mW total power for DAC playback to headphones • 4 Line outputs single-ended or differential • BTL Earpiece driver • Digital audio interfaces for multi-processor architecture - Asynchronous stereo duplex sample rate conversion - Powerful mixing and digital loopback functions • ReTuneTM Mobile 5-band, 4-channel parametric EQ • Dynamic range controller • Dual FLL provides all necessary clocks - Self-clocking modes allow processor to sleep - All standard sample rates from 8kHz to 96kHz • Active noise reduction circuits - DC offset correction removes pops and clicks - Ground loop noise cancellation • Integrated LDO regulators • 80-ball W-CSP package x 0.607mm • Smartphones and music phones • Portable navigation • Tablets, eBooks • Portable Media Players WOLFSON MICROELECTRONICS plc [1] This product is protected by Patents US 7,622,984, US 7,626,445, and GB 2,469,345 WM1811A Production Data TABLE OF CONTENTS 1 FEATURES 1 TABLE OF 2 BLOCK DIAGRAM 6 PIN CONFIGURATION 7 ORDERING 7 PIN 8 ABSOLUTE MAXIMUM RATINGS 11 RECOMMENDED OPERATING 12 ELECTRICAL CHARACTERISTICS 13 INPUT SIGNAL LEVEL 13 INPUT PIN RESISTANCE 14 PROGRAMMABLE GAINS 16 OUTPUT DRIVER CHARACTERISTICS 17 ADC INPUT PATH PERFORMANCE 18 DAC OUTPUT PATH PERFORMANCE 19 BYPASS PATH PERFORMANCE 21 MULTI-PATH 23 DIGITAL INPUT / 25 DIGITAL FILTER CHARACTERISTICS 25 MICROPHONE BIAS 26 MISCELLANEOUS CHARACTERISTICS 27 TERMINOLOGY 28 TYPICAL PERFORMANCE 29 TYPICAL POWER CONSUMPTION 29 TYPICAL SIGNAL LATENCY 30 SIGNAL TIMING REQUIREMENTS 31 SYSTEM CLOCKS & FREQUENCY LOCKED LOOP FLL 31 AUDIO INTERFACE 32 DIGITAL MICROPHONE DMIC INTERFACE DIGITAL AUDIO INTERFACE - MASTER MODE DIGITAL AUDIO INTERFACE - SLAVE DIGITAL AUDIO INTERFACE - TDM MODE CONTROL INTERFACE TIMING 36 DEVICE DESCRIPTION 37 INTRODUCTION 37 ANALOGUE INPUT SIGNAL PATH 39 MICROPHONE INPUTS MICROPHONE BIAS CONTROL MICROPHONE ACCESSORY DETECT LINE AND VOICE CODEC INPUTS INPUT PGA ENABLE INPUT PGA CONFIGURATION INPUT PGA VOLUME INPUT MIXER INPUT MIXER CONFIGURATION AND VOLUME CONTROL DIGITAL MICROPHONE 53 DIGITAL PULL-UP AND Production Data WM1811A ANALOGUE TO DIGITAL CONVERTER ADC 56 ADC CLOCKING CONTROL DIGITAL CORE ARCHITECTURE 58 DIGITAL 60 AUDIO INTERFACE 1 AIF1 OUTPUT DIGITAL SIDETONE VOLUME AND FILTER CONTROL DAC OUTPUT DIGITAL AUDIO INTERFACE 2 AIF2 OUTPUT DIGITAL VOLUME DAC AND AIF2 OUTPUT PATHS DIGITAL VOLUME SOFT MUTE AND SOFT UN-MUTE ULTRASONIC 4FS AIF OUTPUT DYNAMIC RANGE CONTROL 71 DRC COMPRESSION / EXPANSION GAIN DYNAMIC CHARACTERISTICS ANTI-CLIP CONTROL QUICK RELEASE CONTROL SIGNAL ACTIVITY DETECT DRC REGISTER RETUNETM MOBILE PARAMETRIC EQUALIZER EQ 81 DEFAULT MODE 5-BAND PARAMETRIC EQ RETUNETM MOBILE MODE EQ FILTER CHARACTERISTICS 3D STEREO 85 DIGITAL VOLUME AND FILTER CONTROL 86 AIF1 - OUTPUT PATH VOLUME CONTROL AIF1 - OUTPUT PATH HIGH PASS AIF1 - INPUT PATH VOLUME CONTROL AIF1 - INPUT PATH SOFT MUTE CONTROL AIF1 - INPUT PATH NOISE GATE CONTROL AIF1 - INPUT PATH MONO MIX AIF2 - OUTPUT PATH VOLUME CONTROL AIF2 - OUTPUT PATH HIGH PASS AIF2 - INPUT PATH VOLUME CONTROL AIF2 - INPUT PATH SOFT MUTE CONTROL AIF2 - INPUT PATH NOISE GATE CONTROL AIF2- INPUT PATH MONO MIX DIGITAL TO ANALOGUE CONVERTER DAC 97 DAC CLOCKING CONTROL ANALOGUE OUTPUT SIGNAL PATH 99 OUTPUT SIGNAL PATHS HEADPHONE SIGNAL PATHS OUTPUT MIXER CONTROL SPEAKER MIXER CONTROL OUTPUT SIGNAL PATH VOLUME SPEAKER BOOST MIXER EARPIECE DRIVER LINE OUTPUT MIXERS CHARGE 120 DC 122 DC SERVO ENABLE AND START-UP GPIO / INTERRUPT OUTPUTS FROM DC SERVO ANALOGUE OUTPUTS 125 SPEAKER OUTPUT HEADPHONE OUTPUT CONFIGURATIONS WM1811A ORDERING INFORMATION ORDER CODE TEMPERATURERANGE PACKAGE WM1811AECS/R Note Reel quantity = 5000 -40C to +85C 80-ball W-CSP Pb-free, Tape and reel MOISTURE SENSITIVITY LEVEL MSL1 PEAK SOLDERING TEMPERATURE 260C WM1811A Production Data PIN DESCRIPTION A description of each pin on the WM1811A is provided below. Note that a table detailing the associated power domain for every input and output pin is provided on the following page. Note that, where multiple pins share a common name, these pins should be tied together on the PCB. PIN NO NAME ADCDAT1 ADCDAT2 ADCLRCLK1/ GPIO1 ADDR AGND E9, G9 AVDD1 AVDD2 BCLK1 BCLK2 CPCA CPCB CPGND CPVDD CPVOUTN CPVOUTP DACDAT1 DACDAT2 DBVDD1 DBVDD2 DBVDD3 DCVDD The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Supply voltages AVDD1, DBVDD2, DBVDD3 Supply voltages AVDD2, DCVDD, DBVDD1 -0.3V -0.3V +4.5V +2.5V Supply voltages CPVDD Supply voltages SPKVDD1, SPKVDD2, LDO1VDD Voltage range digital inputs DBVDD1 domain -0.3V -0.3V AGND -0.3V +2.2V +7.0V DBVDD1 +0.3V Voltage range digital inputs DBVDD2 domain Voltage range digital inputs DBVDD3 domain AGND -0.3V AGND -0.3V DBVDD2 +0.3V DBVDD3 +0.3V Voltage range digital inputs DMICDAT Voltage range analogue inputs AVDD1 domain Voltage range analogue inputs MICDET, LINEOUTFB AGND -0.3V AGND -0.3V AGND -0.3V AVDD1 +0.3V AVDD1 +0.3V AVDD1 +0.3V Voltage range analogue inputs HPOUT1FB Voltage range analogue inputs JACKDET See note 1 AGND -0.3V CPVOUTN - 0.3V AGND +0.3V AVDD2 +0.3V Ground DGND, CPGND, SPKGND1, SPKGND2, REFGND, HP2GND Operating temperature range, TA Junction temperature, TJMAX Storage temperature after soldering AGND -0.3V -40ºC -40ºC -65ºC AGND +0.3V +85ºC +150ºC +150ºC CPVOUTN is an internal supply rail, generated by the WM1811A Charge Pump. The CPVOUTN voltage may vary between AGND and -CPVDD. WM1811A Production Data RECOMMENDED OPERATING CONDITIONS PARAMETER UNIT Digital supply range Core See notes 7, 8 DCVDD Digital supply range I/O Digital supply range I/O DBVDD1 DBVDD2, DBVDD3 Analogue supply 1 range See notes 3, 4, 5, 6 AVDD1 Analogue supply 2 range AVDD2 Charge Pump supply range Speaker supply range CPVDD SPKVDD1, SPKVDD2 LDO1 supply range Ground LDO1VDD DGND, AGND, CPGND,

PDF Datasheet Preview

WM1811A

Multi-Channel Audio Hub CODEC for Smartphones

The WM1811A[1] is a highly integrated ultra-low power hi-fi CODEC designed for smartphones and other portable devices rich in multimedia features.

An integrated stereo Class D speaker driver and Class W headphone driver minimize power consumption during audio playback.

The device requires only two voltage supplies, with all other internal supply rails generated from integrated LDOs.

Stereo full duplex asynchronous sample rate conversion and multi-channel digital mixing combined with powerful analogue mixing allow the device to support a huge range of different architectures and use cases.

A programmable parametric EQ provides speaker compensation in the digital playback paths. The dynamic range controller can be used in record or playback paths for maintaining a constant signal level, maximizing loudness and protecting speakers against overloading and clipping.

A smart digital microphone interface provides power regulation, a low jitter clock output and decimation filters for up to two digital microphones. Microphone activity detection with interrupt is available.Low power jack detection is supported via a dedicated input pin. Impedance sensing and measurement is provided for external accessory / push-button detection.

Fully differential internal architecture and on-chip RF noise filters ensure a very high degree of noise immunity. Active ground loop noise rejection and DC offset correction help prevent pop noise and suppress ground noise on the headphone outputs.
• 24-bit 2-channel hi-fi DAC and 2-channel hi-fi ADC
• 100dB SNR during DAC playback ‘A’ weighted
• Smart MIC interface
- Power, clocking and data input for up to two digital MICs - High performance analogue MIC interface - MIC activity detect & interrupt allows processor to sleep - Low power jack detection support - Impedance sensing for accessory / push-button detection
• 2W stereo 2 x 2W Class D speaker driver
• Capless Class W headphone drivers - Integrated charge pump - 5.3mW total power for DAC playback to headphones
• 4 Line outputs single-ended or differential
• BTL Earpiece driver
• Digital audio interfaces for multi-processor architecture - Asynchronous stereo duplex sample rate conversion - Powerful mixing and digital loopback functions
• ReTuneTM Mobile 5-band, 4-channel parametric EQ
• Dynamic range controller
• Dual FLL provides all necessary clocks - Self-clocking modes allow processor to sleep - All standard sample rates from 8kHz to 96kHz
• Active noise reduction circuits - DC offset correction removes pops and clicks - Ground loop noise cancellation
• Integrated LDO regulators
• 80-ball W-CSP package x 0.607mm
• Smartphones and music phones
• Portable navigation
• Tablets, eBooks
• Portable Media Players

WOLFSON MICROELECTRONICS plc [1] This product is protected by Patents US 7,622,984, US 7,626,445, and GB 2,469,345

WM1811A

Production Data

TABLE OF CONTENTS
1 FEATURES 1 TABLE OF 2 BLOCK DIAGRAM 6 PIN CONFIGURATION 7 ORDERING 7 PIN 8 ABSOLUTE MAXIMUM RATINGS 11 RECOMMENDED OPERATING 12 ELECTRICAL CHARACTERISTICS 13

INPUT SIGNAL LEVEL 13 INPUT PIN RESISTANCE 14 PROGRAMMABLE GAINS 16 OUTPUT DRIVER CHARACTERISTICS 17 ADC INPUT PATH PERFORMANCE 18 DAC OUTPUT PATH PERFORMANCE 19 BYPASS PATH PERFORMANCE 21 MULTI-PATH 23 DIGITAL INPUT / 25 DIGITAL FILTER CHARACTERISTICS 25 MICROPHONE BIAS 26 MISCELLANEOUS CHARACTERISTICS 27 TERMINOLOGY 28 TYPICAL PERFORMANCE 29 TYPICAL POWER CONSUMPTION 29 TYPICAL SIGNAL LATENCY 30 SIGNAL TIMING REQUIREMENTS 31 SYSTEM CLOCKS & FREQUENCY LOCKED LOOP FLL 31 AUDIO INTERFACE 32

DIGITAL MICROPHONE DMIC INTERFACE

DIGITAL AUDIO INTERFACE - MASTER MODE

DIGITAL AUDIO INTERFACE - SLAVE

DIGITAL AUDIO INTERFACE - TDM MODE

CONTROL INTERFACE TIMING 36 DEVICE DESCRIPTION 37

INTRODUCTION 37 ANALOGUE INPUT SIGNAL PATH 39

MICROPHONE INPUTS

MICROPHONE BIAS CONTROL

MICROPHONE ACCESSORY DETECT

LINE AND VOICE CODEC INPUTS

INPUT PGA ENABLE

INPUT PGA CONFIGURATION

INPUT PGA VOLUME

INPUT MIXER

INPUT MIXER CONFIGURATION AND VOLUME CONTROL

DIGITAL MICROPHONE 53

DIGITAL PULL-UP AND

Production Data

WM1811A

ANALOGUE TO DIGITAL CONVERTER ADC 56

ADC CLOCKING CONTROL

DIGITAL CORE ARCHITECTURE 58 DIGITAL 60

AUDIO INTERFACE 1 AIF1 OUTPUT DIGITAL SIDETONE VOLUME AND FILTER CONTROL DAC OUTPUT DIGITAL AUDIO INTERFACE 2 AIF2 OUTPUT DIGITAL VOLUME DAC AND AIF2 OUTPUT PATHS DIGITAL VOLUME SOFT MUTE AND SOFT UN-MUTE ULTRASONIC 4FS AIF OUTPUT

DYNAMIC RANGE CONTROL 71

DRC COMPRESSION / EXPANSION GAIN DYNAMIC CHARACTERISTICS ANTI-CLIP CONTROL QUICK RELEASE CONTROL SIGNAL ACTIVITY DETECT DRC REGISTER

RETUNETM MOBILE PARAMETRIC EQUALIZER EQ 81

DEFAULT MODE 5-BAND PARAMETRIC EQ RETUNETM MOBILE MODE EQ FILTER CHARACTERISTICS
3D STEREO 85 DIGITAL VOLUME AND FILTER CONTROL 86

AIF1 - OUTPUT PATH VOLUME CONTROL AIF1 - OUTPUT PATH HIGH PASS AIF1 - INPUT PATH VOLUME CONTROL AIF1 - INPUT PATH SOFT MUTE CONTROL AIF1 - INPUT PATH NOISE GATE CONTROL AIF1 - INPUT PATH MONO MIX AIF2 - OUTPUT PATH VOLUME CONTROL AIF2 - OUTPUT PATH HIGH PASS AIF2 - INPUT PATH VOLUME CONTROL AIF2 - INPUT PATH SOFT MUTE CONTROL AIF2 - INPUT PATH NOISE GATE CONTROL AIF2- INPUT PATH MONO MIX

DIGITAL TO ANALOGUE CONVERTER DAC 97

DAC CLOCKING CONTROL

ANALOGUE OUTPUT SIGNAL PATH 99

OUTPUT SIGNAL PATHS HEADPHONE SIGNAL PATHS OUTPUT MIXER CONTROL SPEAKER MIXER CONTROL OUTPUT SIGNAL PATH VOLUME SPEAKER BOOST MIXER EARPIECE DRIVER LINE OUTPUT MIXERS

CHARGE 120 DC 122

DC SERVO ENABLE AND START-UP

GPIO / INTERRUPT OUTPUTS FROM DC SERVO

ANALOGUE OUTPUTS 125

SPEAKER OUTPUT HEADPHONE OUTPUT CONFIGURATIONS

WM1811A
ORDERING INFORMATION

ORDER CODE

TEMPERATURERANGE

PACKAGE

WM1811AECS/R

Note Reel quantity = 5000
-40C to +85C
80-ball W-CSP Pb-free, Tape and reel

MOISTURE SENSITIVITY LEVEL

MSL1

PEAK SOLDERING TEMPERATURE
260C

WM1811A

Production Data

PIN DESCRIPTION

A description of each pin on the WM1811A is provided below. Note that a table detailing the associated power domain for every input and output pin is provided on the following page. Note that, where multiple pins share a common name, these pins should be tied together on the PCB.

PIN NO

NAME

ADCDAT1

ADCDAT2

ADCLRCLK1/

GPIO1

ADDR

AGND

E9, G9

AVDD1

AVDD2

BCLK1

BCLK2

CPCA

CPCB

CPGND

CPVDD

CPVOUTN

CPVOUTP

DACDAT1

DACDAT2

DBVDD1

DBVDD2

DBVDD3

DCVDD
The Moisture Sensitivity Level for each package type is specified in Ordering Information.

CONDITION

Supply voltages AVDD1, DBVDD2, DBVDD3 Supply voltages AVDD2, DCVDD, DBVDD1
-0.3V -0.3V
+4.5V +2.5V

Supply voltages CPVDD Supply voltages SPKVDD1, SPKVDD2, LDO1VDD Voltage range digital inputs DBVDD1 domain
-0.3V -0.3V AGND -0.3V
+2.2V +7.0V DBVDD1 +0.3V

Voltage range digital inputs DBVDD2 domain Voltage range digital inputs DBVDD3 domain

AGND -0.3V AGND -0.3V

DBVDD2 +0.3V DBVDD3 +0.3V

Voltage range digital inputs DMICDAT Voltage range analogue inputs AVDD1 domain Voltage range analogue inputs MICDET, LINEOUTFB

AGND -0.3V AGND -0.3V AGND -0.3V

AVDD1 +0.3V AVDD1 +0.3V AVDD1 +0.3V

Voltage range analogue inputs HPOUT1FB Voltage range analogue inputs JACKDET See note 1

AGND -0.3V CPVOUTN - 0.3V

AGND +0.3V AVDD2 +0.3V

Ground DGND, CPGND, SPKGND1, SPKGND2, REFGND, HP2GND Operating temperature range, TA Junction temperature, TJMAX Storage temperature after soldering

AGND -0.3V -40ºC -40ºC -65ºC

AGND +0.3V +85ºC +150ºC +150ºC

CPVOUTN is an internal supply rail, generated by the WM1811A Charge Pump. The CPVOUTN voltage may vary between AGND and -CPVDD.

WM1811A

Production Data

RECOMMENDED OPERATING CONDITIONS

PARAMETER

UNIT

Digital supply range Core See notes 7, 8

DCVDD

Digital supply range I/O Digital supply range I/O

DBVDD1

DBVDD2, DBVDD3

Analogue supply 1 range See notes 3, 4, 5, 6

AVDD1

Analogue supply 2 range

AVDD2

Charge Pump supply range Speaker supply range

CPVDD

SPKVDD1, SPKVDD2

LDO1 supply range Ground

LDO1VDD

DGND, AGND, CPGND,

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Datasheet ID: WM1811AECS/R 523259