CS61884-IQZ

CS61884-IQZ Datasheet

CS61884

Part	Datasheet
CS61884-IQZ	CS61884-IQZ (pdf)

Related Parts	Information
CS61884-IRZ	CS61884-IRZ
CS61884-IQZR	CS61884-IQZR
CS61884-IRZR	CS61884-IRZR

PDF Datasheet Preview
CS61884 Octal T1/E1/J1 Line Interface Unit Industry-standard Footprint Octal E1/T1/J1 Short-haul Line Interface Unit Low Power No external component changes for 100 Ω/120 Ω/75 Ω operation. Pulse shapes can be customized by the user. Internal AMI, B8ZS, or HDB3 Encoding/Decoding LOS Detection per T1.231, ITU G.775, ETSI 300-233 G.772 Non-Intrusive Monitoring G.703 BITS Clock Recovery Crystal-less Jitter Attenuation Serial/Parallel Microprocessor Control Interfaces Transmitter Short Circuit Current Limiter <50mA TX Drivers with Fast High-Z and Power Down JTAG boundary scan compliant to IEEE 144-Pin LQFP & 160-Pin LFBGA Packages ORDERING INFORMATION CS61884-IQZ 144-pin LQFP, Lead Free CS61884-IRZ 160-pin LFBGA, Lead Free The CS61884 is a full-featured octal E1/T1/J1 short-haul LIU that supports both Mbps or Mbps data transmission. Each channel provides crystal-less jitter attenuation that complies with the most stringent standards. Each channel also provides internal AMI/B8ZS/HDB3 encoding/decoding. To support enhanced system diagnostics, channel zero can be configured for G.772 non-intrusive monitoring of any of the other 7 channels’ receive or transmit paths. The CS61884 makes use of ultra-low-power, matchedimpedance transmitters and receivers to reduce power beyond that achieved by traditional driver designs. By achieving a more precise line match, this technique also provides superior return loss characteristics. Additionally, the internal line matching circuitry reduces the external component count. All transmitters have controls for independent power down and High-Z. Each receiver provides reliable data recovery with over 12 dB of cable attenuation. The receiver also incorporates LOS detection compliant to the most recent specifications. RCLK RPOS RNEG TCLK TPOS TNEG JTAG Serial Port Encoder Decoder Remote Loopback Jitter Attenuator Digital Loopback LOS Receiver Clock Recovery Data Recovery Transmit Control Pulse Shaper Driver JTAG Interface Host Interface Copyright Cirrus Logic, Inc. 2011 All Rights Reserved G.772 Monitor Analog Loopback RTIP RRING TTIP TRING Host Serial/Parallel Port MAR ‘11 DS485F3 CS61884 TABLE OF CONTENTS PINOUT - LQFP 7 PINOUT - LFBGA 8 PIN DESCRIPTIONS 9 Power Supplies 9 Control 10 Address Inputs/Loopbacks 14 Cable Select 15 Status 15 Digital Rx/Tx Data I/O 16 Analog RX/TX Data I/O 19 JTAG Test Interface 21 Miscellaneous 21 OPERATION 22 POWER-UP 22 MASTER CLOCK 22 G.772 MONITORING 22 BUILDING INTEGRATED TIMING SYSTEMS BITS CLOCK MODE 23 TRANSMITTER 24 Bipolar Mode 25 Unipolar Mode 25 RZ Mode 25 Transmitter Powerdown / High-Z 25 Transmit All Ones TAOS 25 Automatic TAOS 26 Driver Failure Monitor 26 Driver Short Circuit Protection 26 RECEIVER 26 Bipolar Output Mode 26 Unipolar Output Mode 26 RZ Output Mode 27 Receiver Powerdown/High-Z 27 Contacting Cirrus Logic Support Visit the Cirrus Logic web site at: IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries "Cirrus" believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE "CRITICAL APPLICATIONS" . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. DS485F3 CS61884 LIST OF FIGURES Figure CS61884 144-LQFP Pinout 7 Figure CS61884 160-Ball LFBGA Pinout 8 Figure G.703 BITS Clock Mode in NRZ Mode 23 Figure G.703 BITS Clock Mode in RZ Mode 23 Figure G.703 BITS Clock Mode in Remote Loopback 23 Figure Pulse Mask at T1/J1 Interface 24 Figure Pulse Mask at E1 Interface 24 Figure Analog Loopback Block Diagram 30 Figure Analog Loopback with TAOS Block Diagram 30 Figure Digital Loopback Block Diagram 31 Figure Digital Loopback with TAOS 31 Figure Remote Loopback Block Diagram 31 Figure Serial Read/Write Format SPOL = 0 33 Figure Arbitrary Waveform UI 43 Figure Test Access Port Architecture 45 Figure TAP Controller State Diagram 46 Figure Internal RX/TX Impedance Matching 51 Figure Internal TX, External RX Impedance Matching 52 Figure Jitter Transfer Characteristic vs. G.736, TBR 12/13 & AT&T 62411 58 Figure Jitter Tolerance Characteristic vs. G.823 & AT&T 62411 58 Figure Recovered Clock and Data Switching Characteristics 60 Figure Transmit Clock and Data Switching Characteristics 60 Figure Signal Rise and Fall Characteristics 60 Figure Serial Port Read Timing Diagram 61 Figure Serial Port Write Timing Diagram 61 Figure Parallel Port Timing - Write Intel Multiplexed Address / Data Bus Mode 63 Figure Parallel Mode Port Timing - Read Intel Multiplexed Address / Data Bus Mode 63 Figure Parallel Port Timing - Write in Motorola Multiplexed Address / Data Bus 64 Figure Parallel Port Timing - Read in Motorola Multiplexed Address / Data Bus 64 Figure Parallel Port Timing - Write in Intel Non-Multiplexed Address / Data Bus Mode 66 Figure Parallel Port Timing - Read in Intel Non-Multiplexed Address / Data Bus Mode 66 Figure Parallel Port Timing - Write in Motorola Non-Multiplexed Address / Data Bus Mode 67 Figure Parallel Port Timing - Read in Motorola Non-Multiplexed Address / Data Bus Mode 67 Figure JTAG Switching Characteristics 68 DS485F3 CS61884 LIST OF TABLES Table Operation Mode Selection 10 Table Mux/Bits Clock Selection 11 Table Cable Impedance Selection 15 Table G.772 Address Selection 22 Table Hardware Mode Line Length Configuration Selection 25 Table Jitter Attenuator Configurations 28 Table Operational Summary 29 Table Host Control Signal Descriptions 32 Table Host Mode Register Set 34 Table JTAG Instructions 47 Table Boundary Scan Register 48 Table Transformer Specifications 53 DS485F3 PINOUT - LQFP CS61884 TNEG4/UBS4 RPOS4/RDATA4 RCLK4 RNEG4/BPV4 LOS4 TXOE CLKE TV+4 TTIP4 TRING4 TGND4 RTIP4 RRING4 TGND5 TRING5 TTIP5 TV+5 RRING5 RTIP5 TV+6 TTIP6 TRING6 TGND6 RTIP6 RRING6 TGND7 TRING7 TTIP7 TV+7 RRING7 ORDERING INFORMATION Model CS61884-IQZ CS61884-IRZ Temperature -40 to +85 °C Package 160-pin LFBGA, 15mm X 15mm 144-pin LQFP, 15mm X 15mm ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number CS61884-IQZ CS61884-IRZ Peak Reflow Temp 260 °C MSL Rating* 3 Max Floor Life 7 Days * MSL Moisture Sensitivity Level as specified by IPC/JEDEC J-STD-020. All devices are now lead Pb free. Date MAR 2011 Changes Removed all lead-containing device ordering information. Removed 160-pin FBGA package option. Corrected formerly named TFBGA to LFBGA. DS485F3

PDF Datasheet Preview

CS61884

Octal T1/E1/J1 Line Interface Unit

Industry-standard Footprint Octal E1/T1/J1 Short-haul Line Interface Unit Low Power No external component changes for 100 Ω/120 Ω/75 Ω
operation. Pulse shapes can be customized by the user. Internal AMI, B8ZS, or HDB3 Encoding/Decoding LOS Detection per T1.231, ITU G.775, ETSI 300-233 G.772 Non-Intrusive Monitoring G.703 BITS Clock Recovery Crystal-less Jitter Attenuation Serial/Parallel Microprocessor Control Interfaces Transmitter Short Circuit Current Limiter <50mA TX Drivers with Fast High-Z and Power Down JTAG boundary scan compliant to IEEE 144-Pin LQFP & 160-Pin LFBGA Packages
ORDERING INFORMATION

CS61884-IQZ
144-pin LQFP, Lead Free

CS61884-IRZ
160-pin LFBGA, Lead Free

The CS61884 is a full-featured octal E1/T1/J1 short-haul LIU that supports both Mbps or Mbps data transmission. Each channel provides crystal-less jitter attenuation that complies with the most stringent standards. Each channel also provides internal AMI/B8ZS/HDB3 encoding/decoding. To support enhanced system diagnostics, channel zero can be configured for G.772 non-intrusive monitoring of any of the other 7 channels’ receive or transmit paths.

The CS61884 makes use of ultra-low-power, matchedimpedance transmitters and receivers to reduce power beyond that achieved by traditional driver designs. By achieving a more precise line match, this technique also provides superior return loss characteristics. Additionally, the internal line matching circuitry reduces the external component count. All transmitters have controls for independent power down and High-Z.

Each receiver provides reliable data recovery with over 12 dB of cable attenuation. The receiver also incorporates LOS detection compliant to the most recent specifications.

RCLK RPOS RNEG

TCLK TPOS TNEG

JTAG Serial Port

Encoder

Decoder

Remote Loopback

Jitter Attenuator

Digital Loopback

LOS Receiver

Clock Recovery

Data Recovery

Transmit Control

Pulse Shaper

Driver

JTAG Interface

Host Interface

Copyright Cirrus Logic, Inc. 2011 All Rights Reserved

G.772 Monitor Analog Loopback

RTIP RRING

TTIP TRING

Host Serial/Parallel

Port

MAR ‘11 DS485F3

CS61884

TABLE OF CONTENTS

PINOUT - LQFP 7 PINOUT - LFBGA 8 PIN DESCRIPTIONS 9

Power Supplies 9 Control 10 Address Inputs/Loopbacks 14 Cable Select 15 Status 15 Digital Rx/Tx Data I/O 16 Analog RX/TX Data I/O 19 JTAG Test Interface 21 Miscellaneous 21 OPERATION 22 POWER-UP 22 MASTER CLOCK 22 G.772 MONITORING 22 BUILDING INTEGRATED TIMING SYSTEMS BITS CLOCK MODE 23 TRANSMITTER 24 Bipolar Mode 25 Unipolar Mode 25 RZ Mode 25 Transmitter Powerdown / High-Z 25 Transmit All Ones TAOS 25 Automatic TAOS 26 Driver Failure Monitor 26 Driver Short Circuit Protection 26 RECEIVER 26 Bipolar Output Mode 26 Unipolar Output Mode 26 RZ Output Mode 27 Receiver Powerdown/High-Z 27

Contacting Cirrus Logic Support

Visit the Cirrus Logic web site at:

IMPORTANT NOTICE

Cirrus Logic, Inc. and its subsidiaries "Cirrus" believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE "CRITICAL APPLICATIONS" . CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
DS485F3

CS61884

LIST OF FIGURES

Figure CS61884 144-LQFP Pinout 7 Figure CS61884 160-Ball LFBGA Pinout 8 Figure G.703 BITS Clock Mode in NRZ Mode 23 Figure G.703 BITS Clock Mode in RZ Mode 23 Figure G.703 BITS Clock Mode in Remote Loopback 23 Figure Pulse Mask at T1/J1 Interface 24 Figure Pulse Mask at E1 Interface 24 Figure Analog Loopback Block Diagram 30 Figure Analog Loopback with TAOS Block Diagram 30 Figure Digital Loopback Block Diagram 31 Figure Digital Loopback with TAOS 31 Figure Remote Loopback Block Diagram 31 Figure Serial Read/Write Format SPOL = 0 33 Figure Arbitrary Waveform UI 43 Figure Test Access Port Architecture 45 Figure TAP Controller State Diagram 46 Figure Internal RX/TX Impedance Matching 51 Figure Internal TX, External RX Impedance Matching 52 Figure Jitter Transfer Characteristic vs. G.736, TBR 12/13 & AT&T 62411 58 Figure Jitter Tolerance Characteristic vs. G.823 & AT&T 62411 58 Figure Recovered Clock and Data Switching Characteristics 60 Figure Transmit Clock and Data Switching Characteristics 60 Figure Signal Rise and Fall Characteristics 60 Figure Serial Port Read Timing Diagram 61 Figure Serial Port Write Timing Diagram 61 Figure Parallel Port Timing - Write Intel Multiplexed Address / Data Bus Mode 63 Figure Parallel Mode Port Timing - Read Intel Multiplexed Address / Data Bus Mode 63 Figure Parallel Port Timing - Write in Motorola Multiplexed Address / Data Bus 64 Figure Parallel Port Timing - Read in Motorola Multiplexed Address / Data Bus 64 Figure Parallel Port Timing - Write in Intel Non-Multiplexed Address / Data Bus Mode 66 Figure Parallel Port Timing - Read in Intel Non-Multiplexed Address / Data Bus Mode 66 Figure Parallel Port Timing - Write in Motorola Non-Multiplexed Address / Data Bus Mode 67 Figure Parallel Port Timing - Read in Motorola Non-Multiplexed Address / Data Bus Mode 67 Figure JTAG Switching Characteristics 68

DS485F3

CS61884

LIST OF TABLES

Table Operation Mode Selection 10 Table Mux/Bits Clock Selection 11 Table Cable Impedance Selection 15 Table G.772 Address Selection 22 Table Hardware Mode Line Length Configuration Selection 25 Table Jitter Attenuator Configurations 28 Table Operational Summary 29 Table Host Control Signal Descriptions 32 Table Host Mode Register Set 34 Table JTAG Instructions 47 Table Boundary Scan Register 48 Table Transformer Specifications 53

DS485F3

PINOUT - LQFP

CS61884

TNEG4/UBS4

RPOS4/RDATA4

RCLK4

RNEG4/BPV4

LOS4

TXOE

CLKE

TV+4

TTIP4

TRING4

TGND4

RTIP4

RRING4

TGND5

TRING5

TTIP5

TV+5

RRING5

RTIP5

TV+6

TTIP6

TRING6

TGND6

RTIP6

RRING6

TGND7

TRING7

TTIP7

TV+7

RRING7
ORDERING INFORMATION

Model CS61884-IQZ CS61884-IRZ

Temperature -40 to +85 °C

Package 160-pin LFBGA, 15mm X 15mm 144-pin LQFP, 15mm X 15mm

ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION

Model Number CS61884-IQZ CS61884-IRZ

Peak Reflow Temp 260 °C

MSL Rating* 3

Max Floor Life 7 Days
* MSL Moisture Sensitivity Level as specified by IPC/JEDEC J-STD-020. All devices are now lead Pb free.

Date MAR 2011

Changes
Removed all lead-containing device ordering information. Removed 160-pin FBGA package option. Corrected formerly named TFBGA to LFBGA.

DS485F3

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CS61884-IQZ Datasheet file may be downloaded here without warranties.

Datasheet ID: CS61884-IQZ 523211