CS61880-IQZR

CS61880-IQZR Datasheet

CS61880

Part	Datasheet
CS61880-IQZR	CS61880-IQZR (pdf)

Related Parts	Information
CS61880-IQZ	CS61880-IQZ

PDF Datasheet Preview
CS61880 Octal E1 Line Interface Unit Octal E1 Short-haul Line Interface Unit Low Power No External Component Changes for 120 / 75 Operation Pulse Shapes can be customized by the user Internal AMI, or HDB3 Encoding/Decoding LOS Detection per ITU G.775 or ETSI 300- 233 G.772 Non-Intrusive Monitoring G.703 BITS Clock Recovery Crystal-less Jitter Attenuation Serial/Parallel Microprocessor Control Interfaces Transmitter Short Circuit Current Limiter <50 mA TX Drivers with Fast High-Z and Power Down JTAG Boundary Scan compliant to IEEE 144-Pin LQFP or 160-Pin FBGA Package ORDERING INFORMATION CS61880-IQ CS61880-IB 144-pin LQFP 160-pin FBGA The CS61880 is a full-featured Octal E1 short-haul LIU that supports Mbps data transmission for both E1 75 and E1 120 applications. Each channel provides crystal-less jitter attenuation that complies with the most stringent standards. Each channel also provides internal AMI/HDB3 encoding/decoding. To support enhanced system diagnostics, channel zero can be configured for G.772 non-intrusive monitoring of any of the other 7 channels’ receive or transmit paths. The CS61880 makes use of ultra low power matched impedance transmitters and receivers to reduce power beyond that achieved by traditional driver designs. By achieving a more precise line match, this technique also provides superior return loss characteristics. Additionally, the internal line matching circuitry reduces the external component count. All transmitters have controls for independent power down and High-Z. Each receiver provides reliable data recovery with over 12 dB of cable attenuation. The receiver also incorporates LOS detection compliant to the most recent specifications. RCLK RPOS RNEG TCLK TPOS TNEG JTAG Serial Port Encoder Decoder Remote Loopback Jitter Attenuator Digital Loopback Clock Recovery Receiver Data Recovery Transmit Control Pulse Shaper Driver JTAG Interface Host Interface G.772 Monitor Analog Loopback RTIP RRING TTIP TRING Host Serial/Parallel Port Preliminary Product Information This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright Cirrus Logic, Inc. 2003 All Rights Reserved JUL ‘03 DS450PP3 CS61880 TABLE OF CONTENTS PIN OUT - 144-PIN LQFP PACKAGE 7 PIN OUT - 160-BALL FBGA PACKAGE 8 PIN DESCRIPTIONS 9 Power Supplies 9 Control 10 Address Inputs/Loopbacks 14 Cable Select 15 Status 15 Digital Rx/Tx Data I/O 16 Analog RX/TX Data I/O 19 JTAG Test Interface 21 Miscellaneous 21 OPERATION 22 POWER-UP 22 MASTER CLOCK 22 G.772 MONITORING 22 BUILDING INTEGRATED TIMING SYSTEMS BITS CLOCK MODE 23 TRANSMITTER 24 Bipolar Mode 24 Unipolar Mode 24 RZ Mode 25 Transmitter Powerdown / High-Z 25 Transmit All Ones TAOS 25 Automatic TAOS 25 Driver Failure Monitor 25 Driver Short Circuit Protection 25 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to: IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries “Cirrus” believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

PDF Datasheet Preview

CS61880

Octal E1 Line Interface Unit

Octal E1 Short-haul Line Interface Unit Low Power No External Component Changes for 120 / 75 Operation Pulse Shapes can be customized by the user Internal AMI, or HDB3 Encoding/Decoding LOS Detection per ITU G.775 or ETSI 300- 233 G.772 Non-Intrusive Monitoring G.703 BITS Clock Recovery Crystal-less Jitter Attenuation Serial/Parallel Microprocessor Control Interfaces Transmitter Short Circuit Current Limiter <50 mA TX Drivers with Fast High-Z and Power Down JTAG Boundary Scan compliant to IEEE 144-Pin LQFP or 160-Pin FBGA Package
ORDERING INFORMATION CS61880-IQ

CS61880-IB
144-pin LQFP 160-pin FBGA

The CS61880 is a full-featured Octal E1 short-haul LIU that supports Mbps data transmission for both E1 75 and E1 120 applications. Each channel provides crystal-less jitter attenuation that complies with the most stringent standards. Each channel also provides internal AMI/HDB3 encoding/decoding. To support enhanced system diagnostics, channel zero can be configured for G.772 non-intrusive monitoring of any of the other 7 channels’ receive or transmit paths.

The CS61880 makes use of ultra low power matched impedance transmitters and receivers to reduce power beyond that achieved by traditional driver designs. By achieving a more precise line match, this technique also provides superior return loss characteristics. Additionally, the internal line matching circuitry reduces the external component count. All transmitters have controls for independent power down and High-Z.

Each receiver provides reliable data recovery with over 12 dB of cable attenuation. The receiver also incorporates LOS detection compliant to the most recent specifications.

RCLK RPOS RNEG

TCLK TPOS TNEG

JTAG Serial Port

Encoder

Decoder

Remote Loopback

Jitter Attenuator

Digital Loopback

Clock Recovery

Receiver

Data Recovery

Transmit Control

Pulse Shaper

Driver

JTAG Interface

Host Interface

G.772 Monitor Analog Loopback

RTIP RRING

TTIP TRING

Host Serial/Parallel

Port

Preliminary Product Information

This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.

Copyright Cirrus Logic, Inc. 2003

All Rights Reserved

JUL ‘03 DS450PP3

CS61880

TABLE OF CONTENTS

PIN OUT - 144-PIN LQFP PACKAGE 7 PIN OUT - 160-BALL FBGA PACKAGE 8 PIN DESCRIPTIONS 9

Power Supplies 9 Control 10 Address Inputs/Loopbacks 14 Cable Select 15 Status 15 Digital Rx/Tx Data I/O 16 Analog RX/TX Data I/O 19 JTAG Test Interface 21 Miscellaneous 21 OPERATION 22 POWER-UP 22 MASTER CLOCK 22 G.772 MONITORING 22 BUILDING INTEGRATED TIMING SYSTEMS BITS CLOCK MODE 23 TRANSMITTER 24 Bipolar Mode 24 Unipolar Mode 24 RZ Mode 25 Transmitter Powerdown / High-Z 25 Transmit All Ones TAOS 25 Automatic TAOS 25 Driver Failure Monitor 25 Driver Short Circuit Protection 25

Contacting Cirrus Logic Support

For all product questions and inquiries contact a Cirrus Logic Sales Representative.

To find the one nearest to you go to:

IMPORTANT NOTICE
“Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries “Cirrus” believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind express or implied . Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale.

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Datasheet ID: CS61880-IQZR 523209