CS47L85-CWZR

CS47L85-CWZR Datasheet

CS47L85

Part	Datasheet
CS47L85-CWZR	CS47L85-CWZR (pdf)

Related Parts	Information
CDB47L85-M-1	CDB47L85-M-1

PDF Datasheet Preview
CS47L85 Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub • 900 MIPS, 900MMAC multicore audio-signal processor • Sensor hub capability, with event time-stamp functions • Programmable wideband, multimic audio processing Cirrus adaptive ambient noise cancelation Transmit-path noise reduction and echo cancelation Wind noise, sidetone, and other programmable filters • Multichannel asynchronous sample rate conversion • Integrated multichannel 24-bit hi-fi audio hub codec Six ADCs, 100-dB SNR mic input 48 kHz Eight DACs, 121-dB SNR headphone playback 48 kHz • Up to 9 analog or 12 digital microphone inputs • Multipurpose headphone/earpiece/line output drivers 30 mW into 32-Ω load at THD+N • Class D speaker, and digital PDM output interfaces • audio and control interface • Four full digital audio interfaces Standard sample rates from 8 to 192 kHz Multichannel TDM support on AIF1 and AIF2 • Flexible clocking, derived from MCLKn, AIFn, or SLIMbus • Low-power frequency-locked loops FLLs support reference clocks down to 32 kHz • Configurable functions on up to 40 GPIO pins • Integrated regulators and charge pumps • Small W-CSP package, 0.4-mm staggered ball array • Smartphones and multimedia handsets • Tablets and Mobile Internet Devices MIDs MICVDD CP2VOUT CP2CA CP2CB CP1C1A CP1C1B CP1VOUT1P CP1VOUT1N CP1C2A CP1C2B CP1VOUT2P CP1VOUT2N FLLVDD CPVDD1 CPVDD2 CPGND DCVDD DBVDD1 DBVDD2 DBVDD3 DBVDD4 DGND LDOVDD LDOVOUT LDOENA SPKVDDL SPKGNDLP SPKGNDLN SPKVDDR SPKGNDRP SPKGNDRN SUBGND JACKDET1 JACKDET2 MICDET1 HPDETL HPDETR MICBIAS1 MICBIAS2 MICBIAS3 MICBIAS4 AVDD AGND VREFC IN1ALN/DMICCLK1, IN1BN IN1ALP, IN1BP IN1RN/DMICDAT1 IN1RP IN2ALN/DMICCLK2, IN2BLN IN2ALP, IN2BLP IN2ARN/DMICDAT2 IN2ARP, IN2BR IN3LN/DMICCLK3 IN3LP IN3RN/DMICDAT3 IN3RP DMICCLKn x3 DMICDATn MCLK1 MCLK2 LDO and MICBIAS Generators Reference Generator Input Select 6 x ADC 3 x Stereo Digital Mic Interface Charge Pumps CS47L85 LDO1 Digital Core Programmable multicore DSP sensor hub Stereo adaptive RX ambient noise cancelation Advanced multimic TX noise reduction Advanced multimic acoustic-echo cancelation Advanced always-on buffering Trigger word detection & ASR assist Speaker protection 5-Band equaliser EQ Dynamic range control DRC Low-Pass / High-Pass Filter LHPF Asynchronous sample rate conversion Automatic sample rate detection Accessory Detect PDM Driver Digital Mic Interface AIFnBCLK AIFnLRCLK SLIMCLK Clocking Control PWM signal generator Haptic control signal generator SYSCLK, ASYNCCLK, DSPCLK Digital Audio Interfaces AIF1, AIF2, AIF3, AIF4 SLIMbus Interface AEC Echo Cancellation Loopback PIN 7 ORDERING INFORMATION 8 PIN DESCRIPTION 8 ABSOLUTE MAXIMUM 15 RECOMMENDED OPERATING CONDITIONS 16 ELECTRICAL CHARACTERISTICS 17 TERMINOLOGY 28 THERMAL CHARACTERISTICS 29 TYPICAL 30 TYPICAL POWER TYPICAL SIGNAL LATENCY SIGNAL TIMING REQUIREMENTS 32 SYSTEM CLOCK & FREQUENCY LOCKED LOOP AUDIO INTERFACE DIGITAL MICROPHONE DMIC INTERFACE 34 DIGITAL SPEAKER PDM INTERFACE 35 DIGITAL AUDIO INTERFACE - MASTER MODE 36 DIGITAL AUDIO INTERFACE - SLAVE 37 DIGITAL AUDIO INTERFACE - TDM 38 CONTROL INTERFACE 2-WIRE I2C CONTROL MODE 39 4-WIRE SPI CONTROL MODE 40 SLIMBUS INTERFACE TIMING JTAG INTERFACE TIMING DEVICE DESCRIPTION 44 INTRODUCTION 44 HI-FI AUDIO 44 DIGITAL AUDIO CORE 45 DIGITAL INTERFACES 45 OTHER FEATURES 45 INPUT SIGNAL ANALOGUE MICROPHONE 49 ANALOGUE LINE INPUT 50 DIGITAL MICROPHONE 50 INPUT SIGNAL PATH ENABLE 52 INPUT SIGNAL PATH SAMPLE RATE 53 INPUT SIGNAL PATH CONFIGURATION 54 INPUT SIGNAL PATH DIGITAL VOLUME 61 INPUT SIGNAL PATH ANC CONTROL 67 DIGITAL MICROPHONE PIN CONFIGURATION 67 DIGITAL DIGITAL CORE MIXERS 70 DIGITAL CORE 74 DIGITAL CORE OUTPUT MIXERS 75 5-BAND PARAMETRIC EQUALISER EQ 78 DYNAMIC RANGE CONTROL DRC 82 LOW PASS / HIGH PASS DIGITAL FILTER 94 DIGITAL CORE DSP 96 SPDIF OUTPUT GENERATOR 97 TONE GENERATOR 99 NOISE GENERATOR 100 CS47L85 HAPTIC SIGNAL GENERATOR 101 PWM 104 SAMPLE RATE CONTROL 106 ASYNCHRONOUS SAMPLE RATE CONVERTER ASRC 116 ISOCHRONOUS SAMPLE RATE CONVERTER ISRC 120 DSP FIRMWARE DSP FIRMWARE MEMORY AND REGISTER MAPPING 127 DSP FIRMWARE 130 DSP DIRECT MEMORY ACCESS DMA CONTROL 134 DSP 137 DSP DEBUG 139 VIRTUAL DSP 139 DSP PERIPHERAL CONTROL MASTER INTERFACES 140 EVENT LOGGERS 146 GENERAL PURPOSE 155 DSP 159 AMBIENT NOISE CANCELLATION DIGITAL AUDIO INTERFACE MASTER AND SLAVE MODE OPERATION 167 AUDIO DATA 167 AIF TIMESLOT CONFIGURATION 169 TDM OPERATION BETWEEN THREE OR MORE DEVICES 171 DIGITAL AUDIO INTERFACE AIF SAMPLE RATE 173 AIF PIN CONFIGURATION 173 AIF MASTER / SLAVE CONTROL 174 AIF SIGNAL PATH 177 AIF BCLK AND LRCLK CONTROL 180 AIF DIGITAL AUDIO DATA CONTROL 185 AIF TDM AND TRI-STATE CONTROL 189 SLIMBUS INTERFACE SLIMBUS 191 SLIMBUS FRAME 191 CONTROL SPACE 191 DATA SPACE 192 SLIMBUS CONTROL SEQUENCES DEVICE MANAGEMENT & CONFIGURATION 193 INFORMATION MANAGEMENT 193 VALUE MANAGEMENT INCLUDING REGISTER ACCESS 194 FRAME & CLOCKING MANAGEMENT 194 DATA CHANNEL CONFIGURATION 194 SLIMBUS INTERFACE CONTROL SLIMBUS DEVICE PARAMETERS 195 SLIMBUS MESSAGE SUPPORT 195 SLIMBUS PORT NUMBER CONTROL 198 SLIMBUS SAMPLE RATE 198 SLIMBUS SIGNAL PATH ENABLE 199 SLIMBUS CONTROL REGISTER ACCESS 200 SLIMBUS CLOCKING CONTROL 202 OUTPUT SIGNAL OUTPUT SIGNAL PATH ENABLE 206 OUTPUT SIGNAL PATH SAMPLE RATE 208 OUTPUT SIGNAL PATH CONTROL 208 OUTPUT SIGNAL PATH DIGITAL FILTER CONTROL 210 OUTPUT SIGNAL PATH DIGITAL VOLUME 212 CS47L85 OUTPUT SIGNAL PATH NOISE GATE CONTROL 218 OUTPUT SIGNAL PATH AEC LOOPBACK 220 HEADPHONE OUTPUTS AND MONO MODE 221 SPEAKER OUTPUTS ANALOGUE 222 SPEAKER OUTPUTS DIGITAL PDM 224 EXTERNAL ACCESSORY JACK 227 JACK POP SUPPRESSION MICDET CLAMP AND GP 229 CONTROL SEQUENCE FOR JACK DETECT & MICDET CLAMP 232 MICROPHONE DETECT 233 HEADPHONE DETECT 238 LOW POWER SLEEP GENERAL PURPOSE INPUT / OUTPUT GPIO 245 GPIO FUNCTION 247 PIN-SPECIFIC ALTERNATIVE FUNCTION 250 BUTTON DETECT GPIO 251 LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT GPIO OUTPUT 251 DSP GPIO LOW LATENCY DSP INPUT/OUTPUT 251 INTERRUPT IRQ STATUS 251 FREQUENCY LOCKED LOOP FLL CLOCK OUTPUT 252 FREQUENCY LOCKED LOOP FLL STATUS OUTPUT 253 OPCLK AND OPCLK_ASYNC CLOCK OUTPUT 253 PULSE WIDTH MODULATION PWM SIGNAL OUTPUT 254 SPDIF AUDIO OUTPUT 254 ASYNCHRONOUS SAMPLE RATE CONVERTER ASRC LOCK STATUS OUTPUT 255 OVER-TEMPERATURE, SHORT CIRCUIT PROTECTION, AND SPEAKER SHUTDOWN STATUS OUTPUT 255 GENERAL PURPOSE TIMER STATUS OUTPUT 255 EVENT LOGGER FIFO BUFFER STATUS OUTPUT 256 GENERAL PURPOSE SWITCH 256 ORDERING INFORMATION ORDER CODE TEMPERATURE RANGE PACKAGE CS47L85-CWZR Note Reel quantity = 4500 -40C to +85C W-CSP Pb-free, Tape and reel MOISTURE SENSITIVITY LEVEL MSL1 PEAK SOLDERING TEMPERATURE 260C PIN DESCRIPTION A description of each pin on the CS47L85 is provided below. Note that a table detailing the associated power domain for every input and output pin is provided on the following page. Note that, where multiple pins share a common name, these pins should be tied together on the PCB. All Digital Output pins are CMOS outputs, unless otherwise stated. PIN NO H2 D14 H13 G12 G11 N13 L11 N4 L4 NAME AGND1 AGND2 AIF1BCLK/ GPIO16 TYPE Supply Digital Input / Output AIF1LRCLK/ GPIO18 Digital Input / Output AIF1RXDAT/ GPIO17 AIF1TXDAT/ GPIO15 Digital Input / Output Digital Input / Output AIF2BCLK/ GPIO20 Digital Input / Output AIF2LRCLK/ GPIO22 Digital Input / Output AIF2RXDAT/ GPIO21 AIF2TXDAT/ GPIO19 Digital Input / Output Digital Input / Output AIF3BCLK/ GPIO24 Digital Input / Output AIF3LRCLK/ GPIO26 Digital Input / Output AIF3RXDAT/GPIO2 5 AIF3TXDAT/GPIO2 3 Digital Input / Output Digital Input / Output AIF4BCLK/ GPIO28 Digital Input / Output The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Supply voltages DCVDD, FLLVDD -0.3V 1.6V Supply voltages CPVDD1, CPVDD2 -0.3V 2.5V Supply voltages DBVDD1, DBVDD2, DBVDD3, DBVDD4, LDOVDD, AVDD, MICVDD -0.3V 5.0V Supply voltages SPKVDDL, SPKVDDR -0.3V 6.0V Voltage range digital inputs DBVDD1 domain SUBGND - 0.3V DBVDD1 + 0.3V Voltage range digital inputs DBVDD2 domain SUBGND - 0.3V DBVDD2 + 0.3V Voltage range digital inputs DBVDD3 domain SUBGND - 0.3V DBVDD3 + 0.3V Voltage range digital inputs DMICDAT1, DMICDAT2, DMICDAT3 SUBGND - 0.3V MICVDD + 0.3V Voltage range digital inputs DMICDAT4, DMICDAT5, DMICDAT6 SUBGND - 0.3V DBVDD4 + 0.3V Voltage range analogue inputs IN1Axx, IN2Axx, IN3xx SUBGND - 0.3V MICVDD + 0.3V Voltage range analogue inputs IN1Bx, IN2Bxx SUBGND - 0.9V MICVDD + 0.3V Voltage range analogue inputs HPOUT1FB1, HPOUT1FB2, HPOUTnFB SUBGND - 0.3V SUBGND + 0.3V Voltage range analogue inputs MICDETn SUBGND - 0.3V MICVDD + 0.3V Note that, register addresses from R12288 0x3000 upwards are formatted as 32-bit words. When writing to these addresses, the Slice Size should be a multiple of 4 bytes, and the Byte Address should be aligned with the 32-bit data word boundaries i.e., an even number . The byte ordering for these register addresses is described in Table REGISTER ADDRESS < 0x3000 BYTE SEQUENCE Base Address 0xYYYYZZ Bytes 2 and 1 0xVVVV Base Address + 1 Bytes 4 and 3 Base Address + 2 Bytes 6 and 5 Base Address + 3 Bytes 8 and 7 Base Address + 4 Bytes 10 and 9 Base Address + 5 Bytes 12 and 11 Base Address + 6 Bytes 14 and 13 Base Address + 7 Bytes 16 and 15 Table 64 SLIMbus Register Write Sequence - 16-bit Register Space < 0x3000 REGISTER ADDRESS 0x3000 BYTE SEQUENCE Base Address 0xYYYYZZ Bytes 4, 3, 2, 1 Base Address + 2 Bytes 8, 7, 6, 5 Base Address + 4 Bytes 12, 11, 10, 9 Base Address + 6 Bytes 16, 15, 14, 13 Table 65 SLIMbus Register Write Sequence - 32-bit Register Space 0x3000 Register Read operations are implemented using the “CHANGE_VALUE” and “REQUEST_VALUE” messages. A maximum of two messages may be required, depending on circumstances the “CHANGE_VALUE” message selects the register page bits [23:8] of the Control Register address the “REQUEST_VALUE” message contains bits [7:0] of the register address. The first message may be omitted if the register page is unchanged from the previous Read or Write operation. The required SLIMbus parameters are described in Table 66 and Table 67, for the generic case of reading the contents of control register address 0xYYYYZZ. The CS47L85 SLIMbus interface supports Register Read operations of 2-bytes i.e., one 16-bit data word only. Register addresses from R12288 0x3000 upwards are formatted as 32-bit words when reading from these addresses, the 2-byte data slice will represent the 2 lower bytes of the selected 32-bit word. The 2 upper bytes of the respective register can be accessed by adding ‘2’ to the Byte Address value described in Table Read Message 1 CHANGE_VALUE PARAMETER VALUE Source Address 0xSS Destination Address 0xLL

PDF Datasheet Preview

CS47L85

Low-Power Smart Codec with Seven DSP Cores, Voice and Media Enhancement, and Integrated Sensor Hub
• 900 MIPS, 900MMAC multicore audio-signal processor
• Sensor hub capability, with event time-stamp functions
• Programmable wideband, multimic audio processing

Cirrus adaptive ambient noise cancelation Transmit-path noise reduction and echo cancelation Wind noise, sidetone, and other programmable filters
• Multichannel asynchronous sample rate conversion
• Integrated multichannel 24-bit hi-fi audio hub codec Six ADCs, 100-dB SNR mic input 48 kHz Eight DACs, 121-dB SNR headphone playback 48 kHz
• Up to 9 analog or 12 digital microphone inputs
• Multipurpose headphone/earpiece/line output drivers 30 mW into 32-Ω load at THD+N
• Class D speaker, and digital PDM output interfaces
• audio and control interface
• Four full digital audio interfaces

Standard sample rates from 8 to 192 kHz Multichannel TDM support on AIF1 and AIF2
• Flexible clocking, derived from MCLKn, AIFn, or SLIMbus
• Low-power frequency-locked loops FLLs support reference clocks down to 32 kHz
• Configurable functions on up to 40 GPIO pins
• Integrated regulators and charge pumps
• Small W-CSP package, 0.4-mm staggered ball array
• Smartphones and multimedia handsets
• Tablets and Mobile Internet Devices MIDs

MICVDD CP2VOUT CP2CA CP2CB CP1C1A CP1C1B CP1VOUT1P CP1VOUT1N CP1C2A CP1C2B CP1VOUT2P CP1VOUT2N FLLVDD CPVDD1 CPVDD2 CPGND DCVDD DBVDD1 DBVDD2 DBVDD3 DBVDD4 DGND LDOVDD LDOVOUT LDOENA SPKVDDL SPKGNDLP SPKGNDLN SPKVDDR SPKGNDRP SPKGNDRN SUBGND JACKDET1 JACKDET2 MICDET1 HPDETL HPDETR

MICBIAS1 MICBIAS2 MICBIAS3 MICBIAS4

AVDD AGND VREFC

IN1ALN/DMICCLK1, IN1BN IN1ALP, IN1BP

IN1RN/DMICDAT1 IN1RP

IN2ALN/DMICCLK2, IN2BLN IN2ALP, IN2BLP

IN2ARN/DMICDAT2 IN2ARP, IN2BR

IN3LN/DMICCLK3 IN3LP

IN3RN/DMICDAT3 IN3RP

DMICCLKn x3 DMICDATn

MCLK1 MCLK2

LDO and MICBIAS Generators

Reference Generator

Input Select 6 x ADC 3 x Stereo Digital Mic Interface

Charge Pumps

CS47L85

LDO1

Digital Core

Programmable multicore DSP sensor hub Stereo adaptive RX ambient noise cancelation

Advanced multimic TX noise reduction Advanced multimic acoustic-echo cancelation

Advanced always-on buffering Trigger word detection & ASR assist

Speaker protection
5-Band equaliser EQ Dynamic range control DRC Low-Pass / High-Pass Filter LHPF Asynchronous sample rate conversion Automatic sample rate detection

Accessory Detect

PDM Driver

Digital Mic Interface

AIFnBCLK AIFnLRCLK

SLIMCLK

Clocking Control

PWM signal generator Haptic control signal generator

SYSCLK, ASYNCCLK, DSPCLK

Digital Audio Interfaces AIF1, AIF2, AIF3, AIF4

SLIMbus Interface

AEC Echo Cancellation Loopback
PIN 7 ORDERING INFORMATION 8 PIN DESCRIPTION 8 ABSOLUTE MAXIMUM 15 RECOMMENDED OPERATING CONDITIONS 16 ELECTRICAL CHARACTERISTICS 17

TERMINOLOGY 28

THERMAL CHARACTERISTICS 29 TYPICAL 30

TYPICAL POWER TYPICAL SIGNAL LATENCY

SIGNAL TIMING REQUIREMENTS 32

SYSTEM CLOCK & FREQUENCY LOCKED LOOP AUDIO INTERFACE

DIGITAL MICROPHONE DMIC INTERFACE 34 DIGITAL SPEAKER PDM INTERFACE 35 DIGITAL AUDIO INTERFACE - MASTER MODE 36 DIGITAL AUDIO INTERFACE - SLAVE 37 DIGITAL AUDIO INTERFACE - TDM 38

CONTROL INTERFACE
2-WIRE I2C CONTROL MODE 39 4-WIRE SPI CONTROL MODE 40

SLIMBUS INTERFACE TIMING JTAG INTERFACE TIMING

DEVICE DESCRIPTION 44

INTRODUCTION 44

HI-FI AUDIO 44 DIGITAL AUDIO CORE 45 DIGITAL INTERFACES 45 OTHER FEATURES 45

INPUT SIGNAL

ANALOGUE MICROPHONE 49 ANALOGUE LINE INPUT 50 DIGITAL MICROPHONE 50 INPUT SIGNAL PATH ENABLE 52 INPUT SIGNAL PATH SAMPLE RATE 53 INPUT SIGNAL PATH CONFIGURATION 54 INPUT SIGNAL PATH DIGITAL VOLUME 61 INPUT SIGNAL PATH ANC CONTROL 67 DIGITAL MICROPHONE PIN CONFIGURATION 67

DIGITAL

DIGITAL CORE MIXERS 70 DIGITAL CORE 74 DIGITAL CORE OUTPUT MIXERS 75 5-BAND PARAMETRIC EQUALISER EQ 78 DYNAMIC RANGE CONTROL DRC 82 LOW PASS / HIGH PASS DIGITAL FILTER 94 DIGITAL CORE DSP 96 SPDIF OUTPUT GENERATOR 97 TONE GENERATOR 99 NOISE GENERATOR 100

CS47L85

HAPTIC SIGNAL GENERATOR 101 PWM 104 SAMPLE RATE CONTROL 106 ASYNCHRONOUS SAMPLE RATE CONVERTER ASRC 116 ISOCHRONOUS SAMPLE RATE CONVERTER ISRC 120

DSP FIRMWARE

DSP FIRMWARE MEMORY AND REGISTER MAPPING 127 DSP FIRMWARE 130 DSP DIRECT MEMORY ACCESS DMA CONTROL 134 DSP 137 DSP DEBUG 139 VIRTUAL DSP 139

DSP PERIPHERAL CONTROL

MASTER INTERFACES 140 EVENT LOGGERS 146 GENERAL PURPOSE 155 DSP 159

AMBIENT NOISE CANCELLATION DIGITAL AUDIO INTERFACE

MASTER AND SLAVE MODE OPERATION 167 AUDIO DATA 167 AIF TIMESLOT CONFIGURATION 169 TDM OPERATION BETWEEN THREE OR MORE DEVICES 171

DIGITAL AUDIO INTERFACE

AIF SAMPLE RATE 173 AIF PIN CONFIGURATION 173 AIF MASTER / SLAVE CONTROL 174 AIF SIGNAL PATH 177 AIF BCLK AND LRCLK CONTROL 180 AIF DIGITAL AUDIO DATA CONTROL 185 AIF TDM AND TRI-STATE CONTROL 189

SLIMBUS INTERFACE

SLIMBUS 191 SLIMBUS FRAME 191 CONTROL SPACE 191 DATA SPACE 192

SLIMBUS CONTROL SEQUENCES

DEVICE MANAGEMENT & CONFIGURATION 193 INFORMATION MANAGEMENT 193 VALUE MANAGEMENT INCLUDING REGISTER ACCESS 194 FRAME & CLOCKING MANAGEMENT 194 DATA CHANNEL CONFIGURATION 194

SLIMBUS INTERFACE CONTROL

SLIMBUS DEVICE PARAMETERS 195 SLIMBUS MESSAGE SUPPORT 195 SLIMBUS PORT NUMBER CONTROL 198 SLIMBUS SAMPLE RATE 198 SLIMBUS SIGNAL PATH ENABLE 199 SLIMBUS CONTROL REGISTER ACCESS 200 SLIMBUS CLOCKING CONTROL 202

OUTPUT SIGNAL

OUTPUT SIGNAL PATH ENABLE 206 OUTPUT SIGNAL PATH SAMPLE RATE 208 OUTPUT SIGNAL PATH CONTROL 208 OUTPUT SIGNAL PATH DIGITAL FILTER CONTROL 210 OUTPUT SIGNAL PATH DIGITAL VOLUME 212

CS47L85

OUTPUT SIGNAL PATH NOISE GATE CONTROL 218 OUTPUT SIGNAL PATH AEC LOOPBACK 220 HEADPHONE OUTPUTS AND MONO MODE 221 SPEAKER OUTPUTS ANALOGUE 222 SPEAKER OUTPUTS DIGITAL PDM 224

EXTERNAL ACCESSORY

JACK 227 JACK POP SUPPRESSION MICDET CLAMP AND GP 229 CONTROL SEQUENCE FOR JACK DETECT & MICDET CLAMP 232 MICROPHONE DETECT 233 HEADPHONE DETECT 238

LOW POWER SLEEP GENERAL PURPOSE INPUT / OUTPUT

GPIO 245 GPIO FUNCTION 247 PIN-SPECIFIC ALTERNATIVE FUNCTION 250 BUTTON DETECT GPIO 251 LOGIC ‘1’ AND LOGIC ‘0’ OUTPUT GPIO OUTPUT 251 DSP GPIO LOW LATENCY DSP INPUT/OUTPUT 251 INTERRUPT IRQ STATUS 251 FREQUENCY LOCKED LOOP FLL CLOCK OUTPUT 252 FREQUENCY LOCKED LOOP FLL STATUS OUTPUT 253 OPCLK AND OPCLK_ASYNC CLOCK OUTPUT 253 PULSE WIDTH MODULATION PWM SIGNAL OUTPUT 254 SPDIF AUDIO OUTPUT 254 ASYNCHRONOUS SAMPLE RATE CONVERTER ASRC LOCK STATUS OUTPUT 255 OVER-TEMPERATURE, SHORT CIRCUIT PROTECTION, AND SPEAKER SHUTDOWN STATUS OUTPUT 255 GENERAL PURPOSE TIMER STATUS OUTPUT 255 EVENT LOGGER FIFO BUFFER STATUS OUTPUT 256 GENERAL PURPOSE SWITCH 256
ORDERING INFORMATION

ORDER CODE

TEMPERATURE RANGE

PACKAGE

CS47L85-CWZR

Note Reel quantity = 4500
-40C to +85C

W-CSP Pb-free, Tape and reel

MOISTURE SENSITIVITY LEVEL

MSL1

PEAK SOLDERING TEMPERATURE
260C

PIN DESCRIPTION

A description of each pin on the CS47L85 is provided below. Note that a table detailing the associated power domain for every input and output pin is provided on the following page. Note that, where multiple pins share a common name, these pins should be tied together on the PCB. All Digital Output pins are CMOS outputs, unless otherwise stated.

PIN NO H2 D14 H13

G12 G11

N13 L11

N4 L4

NAME AGND1 AGND2 AIF1BCLK/ GPIO16

TYPE Supply Digital Input / Output

AIF1LRCLK/ GPIO18

Digital Input / Output

AIF1RXDAT/ GPIO17

AIF1TXDAT/ GPIO15

Digital Input / Output Digital Input / Output

AIF2BCLK/ GPIO20

Digital Input / Output

AIF2LRCLK/ GPIO22

Digital Input / Output

AIF2RXDAT/ GPIO21

AIF2TXDAT/ GPIO19

Digital Input / Output Digital Input / Output

AIF3BCLK/ GPIO24

Digital Input / Output

AIF3LRCLK/ GPIO26

Digital Input / Output

AIF3RXDAT/GPIO2 5

AIF3TXDAT/GPIO2 3

Digital Input / Output Digital Input / Output

AIF4BCLK/ GPIO28

Digital Input / Output
The Moisture Sensitivity Level for each package type is specified in Ordering Information.

CONDITION

Supply voltages DCVDD, FLLVDD
-0.3V
1.6V

Supply voltages CPVDD1, CPVDD2
-0.3V
2.5V

Supply voltages DBVDD1, DBVDD2, DBVDD3, DBVDD4, LDOVDD, AVDD, MICVDD
-0.3V
5.0V

Supply voltages SPKVDDL, SPKVDDR
-0.3V
6.0V

Voltage range digital inputs DBVDD1 domain

SUBGND - 0.3V

DBVDD1 + 0.3V

Voltage range digital inputs DBVDD2 domain

SUBGND - 0.3V

DBVDD2 + 0.3V

Voltage range digital inputs DBVDD3 domain

SUBGND - 0.3V

DBVDD3 + 0.3V

Voltage range digital inputs DMICDAT1, DMICDAT2, DMICDAT3

SUBGND - 0.3V

MICVDD + 0.3V

Voltage range digital inputs DMICDAT4, DMICDAT5, DMICDAT6

SUBGND - 0.3V

DBVDD4 + 0.3V

Voltage range analogue inputs IN1Axx, IN2Axx, IN3xx

SUBGND - 0.3V

MICVDD + 0.3V

Voltage range analogue inputs IN1Bx, IN2Bxx

SUBGND - 0.9V

MICVDD + 0.3V

Voltage range analogue inputs HPOUT1FB1, HPOUT1FB2, HPOUTnFB

SUBGND - 0.3V

SUBGND + 0.3V

Voltage range analogue inputs MICDETn

SUBGND - 0.3V

MICVDD + 0.3V
Note that, register addresses from R12288 0x3000 upwards are formatted as 32-bit words. When writing to these addresses, the Slice Size should be a multiple of 4 bytes, and the Byte Address should be aligned with the 32-bit data word boundaries i.e., an even number . The byte ordering for these register addresses is described in Table

REGISTER ADDRESS < 0x3000

BYTE SEQUENCE

Base Address 0xYYYYZZ

Bytes 2 and 1 0xVVVV

Base Address + 1

Bytes 4 and 3

Base Address + 2

Bytes 6 and 5

Base Address + 3

Bytes 8 and 7

Base Address + 4

Bytes 10 and 9

Base Address + 5

Bytes 12 and 11

Base Address + 6

Bytes 14 and 13

Base Address + 7

Bytes 16 and 15

Table 64 SLIMbus Register Write Sequence - 16-bit Register Space < 0x3000

REGISTER ADDRESS 0x3000

BYTE SEQUENCE

Base Address 0xYYYYZZ

Bytes 4, 3, 2, 1

Base Address + 2

Bytes 8, 7, 6, 5

Base Address + 4

Bytes 12, 11, 10, 9

Base Address + 6

Bytes 16, 15, 14, 13

Table 65 SLIMbus Register Write Sequence - 32-bit Register Space 0x3000

Register Read operations are implemented using the “CHANGE_VALUE” and “REQUEST_VALUE” messages. A maximum of two messages may be required, depending on circumstances the “CHANGE_VALUE” message selects the register page bits [23:8] of the Control Register address the “REQUEST_VALUE” message contains bits [7:0] of the register address. The first message may be omitted if the register page is unchanged from the previous Read or Write operation.

The required SLIMbus parameters are described in Table 66 and Table 67, for the generic case of reading the contents of control register address 0xYYYYZZ.

The CS47L85 SLIMbus interface supports Register Read operations of 2-bytes i.e., one 16-bit data word only. Register addresses from R12288 0x3000 upwards are formatted as 32-bit words when reading from these addresses, the 2-byte data slice will represent the 2 lower bytes of the selected 32-bit word. The 2 upper bytes of the respective register can be accessed by adding ‘2’ to the Byte Address value described in Table

Read Message 1 CHANGE_VALUE

PARAMETER

VALUE

Source Address
0xSS

Destination Address
0xLL

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CS47L85-CWZR Datasheet file may be downloaded here without warranties.

Datasheet ID: CS47L85-CWZR 523190