ADM1067ASUZ

ADM1067ASUZ Datasheet


ADM1067

Part Datasheet
ADM1067ASUZ ADM1067ASUZ ADM1067ASUZ (pdf)
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Data Sheet

Complete supervisory and sequencing solution for up to 10 supplies
10 supply fault detectors enable supervision of supplies to accuracy at all voltages at 25°C accuracy across all voltages and temperatures
5 selectable input attenuators allow supervision of supplies to V on VH 6 V on VP1 to VP4 VPx
5 dual-function inputs, VX1 to VX5 VXx High impedance input to supply fault detector with thresholds between V and V General-purpose logic input
10 programmable driver outputs, PDO1 to PDO10 PDOx Open-collector with external pull-up Push/pull output, driven to VDDCAP or VPx Open collector with weak pull-up to VDDCAP or VPx Internally charge-pumped high drive for use with external N-FET PDO1 to PDO6 only

Sequencing engine SE implements state machine control of PDO outputs State changes conditional on input events Enables complex control of boards Power-up and power-down sequence control Fault event handling Interrupt generation on warnings Watchdog function can be integrated in SE Program software control of sequencing through SMBus

Open-loop margining solution for 6 voltage rails 6 voltage output 8-bit DACs V to V allow voltage
adjustment via dc-to-dc converter trim/feedback node Device powered by the highest of VPx, VH for improved
redundancy User EEPROM 256 bytes Industry-standard 2-wire bus interface SMBus Guaranteed PDO low with VH, VPx = V Available in 40-lead, 6 mm x 6 mm LFCSP and
48-lead, 7 mm x 7 mm TQFP packages

Central office systems Servers/routers Multivoltage system line cards DSP/FPGA supply sequencing In-circuit testing of margined supplies

Super Sequencer with Open-Loop Margining DACs

ADM1067

FUNCTIONAL BLOCK DIAGRAM

REFOUT REFGND SDA SCL A1 A0

ADM1067

VREF

SMBus INTERFACE

EEPROM

VX1 VX2 VX3 VX4 VX5

VP1 VP2 VP3 VP4

VH AGND VDDCA P

DUALFUNCTION

INPUTS LOGIC INPUTS

OR SFDs

PROGRAMMABLE RESET

GENERATORS SFDs

SEQUENCING ENGINE

CONFIGURABLE OUTPUT DRIVERS

HV CAPABLE OF DRIVING GATES

OF N-FET

CONFIGURABLE OUTPUT DRIVERS

LV CAPABLE OF DRIVING LOGIC SIGNALS

VDD ARBITRATOR

VOUT DAC

VOUT DAC

VOUT DAC

VOUT DAC

VOUT DAC

VOUT DAC
Overview 18 SMBus Jump Unconditional 18 Sequencing Engine Application Example 19 Fault and Status 20 Supply Margining 21 Overview 21 Open-Loop Supply Margining 21 Writing to the DACs 21 Choosing the Size of the Attenuation Resistor 22 DAC Limiting and Other Safety Features 22 Applications Diagram 23 Communicating with the 24 Configuration Download at Power-Up 24 Updating the Configuration 24 Updating the Sequencing 25 Internal 25 EEPROM 25 Serial Bus 25 SMBus Protocols for RAM and EEPROM.............................. 28 Write Operations 28 Read Operations 30 Outline Dimensions 31 Ordering Guide 31

Data Sheet
ADM1067
0 Initial Version

ADM1067

Data Sheet

Supply margining can be performed with a minimum of external components. The margining capability can be used for in-circuit testing of a board during production for example, to verify board functionality at −5% of nominal supplies , or it can be used dynamically to accurately control the output voltage of a dc-to-dc converter.

The device also provides up to 10 programmable inputs for monitoring undervoltage faults, overvoltage faults, or out-ofwindow faults on up to 10 supplies. In addition, 10 programmable outputs can be used as logic enables.

Six of these programmable outputs can also provide up to a 12 V output for driving the gate of an N-FET that can be placed in the path of a supply.

The logical core of the device is a sequencing engine. This statemachine-based construction provides up to 63 different states. This design enables very flexible sequencing of the outputs, based on the condition of the inputs.

The device is controlled via configuration data that can be programmed into an EEPROM. The entire configuration can be programmed using an intuitive GUI-based software package provided by Analog Devices, Inc.

DETAILED BLOCK DIAGRAM

REFOUT REFGND SDA SCL A1 A0

VREF

SMBus INTERFACE

DEVICE CONTROLLER

OSC EEPROM

VX1 VX2 VX3 VX4

VP1 VP2 VP3 VP4

VH AGND VDDCAP

ADM1067

GPI SIGNAL CONDITIONING

GPI SIGNAL CONDITIONING

SELECTABLE ATTENUATOR

SELECTABLE ATTENUATOR

VDD ARBITRATOR

CONFIGURABLE OUTPUT DRIVER

SEQUENCING ENGINE

CONFIGURABLE OUTPUT DRIVER

CONFIGURABLE OUTPUT DRIVER

CONFIGURABLE OUTPUT DRIVER

MUP VCCP

REG 5.25V CHARGE PUMP

VOUT DAC

VOUT DAC

VOUT DAC

VOUT DAC

VOUT DAC

VOUT DAC

DAC1

DAC2

DAC3

Figure

DAC4
ORDERING GUIDE

Model1 ADM1067ACPZ ADM1067ASUZ EVAL-ADM1067TQEBZ
1 Z = RoHS Compliant Part.
0° MIN

SEATING PLANE
0° MAX COPLANARITY

VIEW A

ROTATED 90° CCW

BSC SQ
37 36

PIN 1

TOP VIEW PINS DOWN

BSC SQ
12 13
25 24

VIEW A

BSC LEAD PITCH

COMPLIANT TO JEDEC STANDARDS MS-026ABC

Figure 48-Lead Thin Plastic Quad Flat Package [TQFP] SU-48

Dimensions shown in millimeters

Temperature Range −40°C to +85°C −40°C to +85°C

Package Description 40-Lead Frame Chip Scale Package [LFCSP_WQ] 48-Lead Thin Quad Flat Package [TQFP] Evaluation Kit TQFP Version
05-06-2011-A

ADM1067

Package Option CP-40-9 SU-48

Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D04635-0-1/15 E
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Datasheet ID: ADM1067ASUZ 517831