CS42428-CQZR

CS42428-CQZR Datasheet

CS42428

Part	Datasheet
CS42428-CQZR	CS42428-CQZR (pdf)

Related Parts	Information
CS42428-CQZ	CS42428-CQZ
CS42428-DQZR	CS42428-DQZR
CS42428-DQZ	CS42428-DQZ

PDF Datasheet Preview
CS42428 114 dB, 192 kHz 8-Ch Codec with PLL ! Eight 24-bit D/A, two 24-bit A/D Converters ! 114 dB DAC / 114 dB ADC Dynamic Range ! -100 dB THD+N ! System Sampling Rates up to 192 kHz ! Integrated Low-Jitter PLL for Increased System Jitter Tolerance ! PLL Clock or System Clock Selection ! 7 Configurable General-Purpose Outputs ! ADC High-Pass Filter for DC Offset Calibration ! Expandable ADC Channels and One-Line Mode Support ! Digital Output Volume Control with Soft Ramp ! Digital +/-15 dB Input Gain Adjust for ADC ! Differential Analog Architecture ! Supports Logic Levels between V and 5 V The CS42428 codec provides two analog-to-digital and eight digital-to-analog delta-sigma converters, as well as an integrated PLL. The CS42428 integrated PLL provides a low-jitter system clock. The internal stereo ADC is capable of independent channel gain control for single-ended or differential analog inputs. All eight channels of DAC provide digital volume control and differential analog outputs. The general-purpose outputs may be driven high or low, or mapped to a variety of DAC mute controls or ADC overflow indicators. The CS42428 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, digital speaker and automotive audio systems. The CS42428 is available in a 64-pin LQFP package in both Commercial -10° to 70° C and Automotive -40° to 85° C grades. The CDB42428 Customer Demonstration board is also available for device evaluation. Refer to “Ordering Information” on page GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 GPO7 MUTEC AINL+ AINL- AINR+ AINR- AOUTA1+ AOUTA1- AOUTB1+ AOUTB1- AOUTA2+ AOUTA2- AOUTB2+ AOUTB2- AOUTA3+ AOUTA3- AOUTB3+ AOUTB3- AOUTA4+ AOUTA4- AOUTB4+ AOUTB4- VA AGND GPO ADC#1 ADC#2 Analog Filter REFGND VQ FILT+ OMCK RMCK LPFLT VLC DGND VD Mute Internal Voltage Reference Mult/Div PLL Control Port AD0/CS AD1/CDIN SDA/CDOUT SCL/CCLK Digital Filter Volume Control DAC Serial Audio Port Digital Filter Digital Filter DAC#1 DAC#2 DAC#3 DAC#4 DAC#5 DAC#6 DAC#7 DAC#8 Gain & Clip Gain & Clip ADC Serial Audio Port Level Translator Level Translator ADCIN1 ADCIN2 ADC_SDOUT ADC_LRCK ADC_SCLK DAC_LRCK DAC_SCLK DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4 Copyright Cirrus Logic, Inc. 2005 All Rights Reserved NOVEMBER '05 DS605F1 CS42428 TABLE OF CONTENTS CHARACTERISTICS AND SPECIFICATIONS 6 SPECIFIED OPERATING CONDITIONS 6 ABSOLUTE MAXIMUM RATINGS 6 ANALOG INPUT CHARACTERISTICS 7 A/D DIGITAL FILTER CHARACTERISTICS 8 ANALOG OUTPUT CHARACTERISTICS 9 D/A DIGITAL FILTER CHARACTERISTICS 10 SWITCHING CHARACTERISTICS 11 SWITCHING CHARACTERISTICS - CONTROL PORT - FORMAT 12 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT 13 DC ELECTRICAL CHARACTERISTICS 14 DIGITAL INTERFACE CHARACTERISTICS 15 PIN DESCRIPTIONS 16 TYPICAL CONNECTION DIAGRAMS 18 APPLICATIONS 20 Overview 20 Analog Inputs 20 Line-Level Inputs 20 High-Pass Filter and DC Offset Calibration 21 Analog Outputs 21 Line-Level Outputs and Filtering 21 Interpolation Filter 21 Digital Volume and Mute Control 22 ATAPI Specification 22 Clock Generation 23 PLL and Jitter Attenuation 23 OMCK System Clock Mode 24 Master Mode 24 Slave Mode 24 Digital Interfaces 25 Serial Audio Interface Signals 25 Serial Audio Interface Formats 27 ADCIN1/ADCIN2 Serial Data Format 30 One-Line Mode OLM Configurations 31 DS605F1 LIST OF FIGURES Figure 1.Serial Audio Port Master Mode Timing 11 Figure 2.Serial Audio Port Slave Mode Timing 11 Figure 3.Control Port Timing - Format 12 Figure 4.Control Port Timing - SPI Format 13 Figure 5.Typical Connection Diagram 18 Figure 6.Typical Connection Diagram using the PLL 19 Figure 7.Full-Scale Analog Input 20 Figure 8.Full-Scale Output 21 Figure 9.ATAPI Block Diagram x = channel pair 1, 2, 3, 4 22 Figure 10.Clock Generation 23 Figure 11.Right-Justified Serial Audio Formats 27 Figure Serial Audio Formats 28 Figure 13.Left-Justified Serial Audio Formats 28 Figure 14.One Line Mode #1 Serial Audio Format 29 Figure 15.One Line Mode #2 Serial Audio Format 29 DS605F1 CS42428 Figure 16.ADCIN1/ADCIN2 Serial Audio Format 30 Figure 17.OLM Configuration #1 31 Figure 18.OLM Configuration #2 32 Figure 19.OLM Configuration #3 33 Figure 20.OLM Configuration #4 34 Figure 21.Control Port Timing in SPI Mode 35 Figure 22.Control Port Timing, Write 36 Figure 23.Control Port Timing, Read 36 Figure 24.Recommended Analog Input Buffer 61 Figure 25.Recommended Analog Output Buffer 61 Figure 26.Recommended Layout Example 63 Figure 27.Single-Speed Mode Stopband Rejection 64 Figure 28.Single-Speed Mode Transition Band 64 Figure 29.Single-Speed Mode Transition Band Detail 64 Figure 30.Single-Speed Mode Passband Ripple 64 Figure 31.Double-Speed Mode Stopband Rejection 64 Figure 32.Double-Speed Mode Transition Band 64 Figure 33.Double-Speed Mode Transition Band Detail 65 Figure 34.Double-Speed Mode Passband Ripple 65 Figure 35.Quad-Speed Mode Stopband Rejection 65 Figure 36.Quad-Speed Mode Transition Band 65 Figure 37.Quad-Speed Mode Transition Band Detail 65 Figure 38.Quad-Speed Mode Passband Ripple 65 Figure 39.Single-Speed fast Stopband Rejection 66 Figure 40.Single-Speed fast Transition Band 66 Figure 41.Single-Speed fast Transition Band detail 66 Figure 42.Single-Speed fast Passband Ripple 66 Figure 43.Single-Speed slow Stopband Rejection 66 Figure 44.Single-Speed slow Transition Band 66 Figure 45.Single-Speed slow Transition Band detail 67 Figure 46.Single-Speed slow Passband Ripple 67 Figure 47.Double-Speed fast Stopband Rejection 67 Figure 48.Double-Speed fast Transition Band 67 Figure 49.Double-Speed fast Transition Band detail 67 Figure 50.Double-Speed fast Passband Ripple 67 Figure 51.Double-Speed slow Stopband Rejection 68 Figure 52.Double-Speed slow Transition Band 68 Figure 53.Double-Speed slow Transition Band detail 68 Figure 54.Double-Speed slow Passband Ripple 68 Figure 55.Quad-Speed fast Stopband Rejection 68 Figure 56.Quad-Speed fast Transition Band 68 Figure 57.Quad-Speed fast Transition Band detail 69 Figure 58.Quad-Speed fast Passband Ripple 69 Figure 59.Quad-Speed slow Stopband Rejection 69 Figure 60.Quad-Speed slow Transition Band 69 Figure 61.Quad-Speed slow Transition Band detail 69 Figure 62.Quad-Speed slow Passband Ripple 69 DS605F1 CS42428 LIST OF TABLES Table Common OMCK Clock Frequencies 24 Table Common PLL Output Clock 24 Table Slave Mode Clock Ratios 25 Table Serial Audio Port Channel Allocations 26 Table DAC De-Emphasis 44 Table Digital Interface Formats 45 Table ADC One-Line 45 Table DAC One-Line 45 Table RMCK Divider Settings 48 Table OMCK Frequency Settings 48 Table Master Clock Source 49 Table PLL Clock Frequency 50 Table Example Digital Volume Settings 53 Table ATAPI Decode 54 Table Example ADC Input Gain Settings 55 Table PLL External Component Values 62 DS605F1 CS42428 CHARACTERISTICS AND SPECIFICATIONS All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C. SPECIFIED OPERATING CONDITIONS AGND=DGND=0, all voltages with respect to ground OMCK=12.288 MHz Master Mode Parameter Symbol Min Typ DC Power Supply Analog Digital VD Serial Port Interface VLS Control Port Interface VLC Ambient Operating Temperature power applied CS42428-CQZ CS42428-DQZ +70 +85 Units °C °C ABSOLUTE MAXIMUM RATINGS AGND = DGND = 0 V all voltages with respect to ground. Parameters DC Power Supply Analog Digital Serial Port Interface Control Port Interface Input Current Note 1 Analog Input Voltage Note 2 Digital Input Voltage Note 2 Serial Port Interface Control Port Interface Ambient Operating Temperature power applied CS42428-CQZ CS42428-DQZ 13.ORDERING INFORMATION Product Package Pb-Free CS42428 114 dB, 192 kHz 8-Ch Codec with PLL 64-pin LQFP CDB42428 CS42428 Evaluation Board Grade Commercial Automotive - Temp Range -10° to +70° C -40° to +85° C - Container Order # Tray CS42428-CQZ Tape & Reel CS42428-CQZR Tray CS42428-DQZ Tape & Reel CS42428-DQZR CDB42428 14.REFERENCES 1 Cirrus Logic, Audio Quality Measurement Specification, Version 2 Cirrus Logic, AN18 Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version February 3 Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September 4 Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the Audio Engineering Society, November 5 Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 6 Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 7 Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters,by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 8 Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 9 Philips Semiconductor, The I2C-Bus Specification Version January DS605F1 CS42428 15.REVISION HISTORY Release A1 A2 F1 Date May 2003 August 2004 November 2005 Changes Advance Release Added lead free part numbers. Final Release table on page Updated ADC Input Impedance and Offset Error specifications in the Analog Input Characteristics table on page Updated the DAC Full-Scale Voltage, Output Impedance, and Gain Drift specifications in the Analog Output Characteristics table on page Updated specification conditions for the analog input characteristics on page Updated specification conditions for the analog output characteristics on page Updated specification of tds, tdh, tdpd, and tlrpd in the Switching Characteristics table on page Corrected reference to the SW_CTRL[1:0] bits in section on page Moved the VQ and FILT+ specifications from the Analog Input DS605F1

PDF Datasheet Preview

CS42428
114 dB, 192 kHz 8-Ch Codec with PLL
! Eight 24-bit D/A, two 24-bit A/D Converters ! 114 dB DAC / 114 dB ADC Dynamic Range ! -100 dB THD+N ! System Sampling Rates up to 192 kHz ! Integrated Low-Jitter PLL for Increased System

Jitter Tolerance ! PLL Clock or System Clock Selection ! 7 Configurable General-Purpose Outputs ! ADC High-Pass Filter for DC Offset Calibration ! Expandable ADC Channels and One-Line

Mode Support ! Digital Output Volume Control with Soft Ramp ! Digital +/-15 dB Input Gain Adjust for ADC ! Differential Analog Architecture ! Supports Logic Levels between V and 5 V

The CS42428 codec provides two analog-to-digital and eight digital-to-analog delta-sigma converters, as well as an integrated PLL.

The CS42428 integrated PLL provides a low-jitter system clock. The internal stereo ADC is capable of independent channel gain control for single-ended or differential analog inputs. All eight channels of DAC provide digital volume control and differential analog outputs. The general-purpose outputs may be driven high or low, or mapped to a variety of DAC mute controls or ADC overflow indicators.

The CS42428 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, digital speaker and automotive audio systems.
The CS42428 is available in a 64-pin LQFP package in both Commercial -10° to 70° C and Automotive -40° to 85° C grades. The CDB42428 Customer Demonstration board is also available for device evaluation. Refer to “Ordering Information” on page

GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 GPO7 MUTEC

AINL+ AINL-

AINR+ AINR-

AOUTA1+ AOUTA1-

AOUTB1+ AOUTB1-

AOUTA2+ AOUTA2-

AOUTB2+ AOUTB2-

AOUTA3+ AOUTA3-

AOUTB3+ AOUTB3-

AOUTA4+ AOUTA4-

AOUTB4+ AOUTB4-

VA AGND GPO

ADC#1 ADC#2

Analog Filter

REFGND VQ FILT+ OMCK

RMCK LPFLT VLC DGND VD

Mute

Internal Voltage Reference

Mult/Div PLL

Control Port

AD0/CS AD1/CDIN SDA/CDOUT SCL/CCLK

Digital Filter Volume Control DAC Serial Audio Port

Digital Filter Digital Filter

DAC#1 DAC#2 DAC#3 DAC#4 DAC#5 DAC#6 DAC#7 DAC#8

Gain & Clip Gain & Clip

ADC Serial Audio Port

Level Translator

Level Translator

ADCIN1 ADCIN2 ADC_SDOUT ADC_LRCK

ADC_SCLK

DAC_LRCK DAC_SCLK DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4

Copyright Cirrus Logic, Inc. 2005 All Rights Reserved

NOVEMBER '05 DS605F1

CS42428

TABLE OF CONTENTS

CHARACTERISTICS AND SPECIFICATIONS 6 SPECIFIED OPERATING CONDITIONS 6 ABSOLUTE MAXIMUM RATINGS 6 ANALOG INPUT CHARACTERISTICS 7 A/D DIGITAL FILTER CHARACTERISTICS 8 ANALOG OUTPUT CHARACTERISTICS 9 D/A DIGITAL FILTER CHARACTERISTICS 10 SWITCHING CHARACTERISTICS 11 SWITCHING CHARACTERISTICS - CONTROL PORT - FORMAT 12 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT 13 DC ELECTRICAL CHARACTERISTICS 14 DIGITAL INTERFACE CHARACTERISTICS 15

PIN DESCRIPTIONS 16 TYPICAL CONNECTION DIAGRAMS 18 APPLICATIONS 20

Overview 20 Analog Inputs 20

Line-Level Inputs 20 High-Pass Filter and DC Offset Calibration 21 Analog Outputs 21 Line-Level Outputs and Filtering 21 Interpolation Filter 21 Digital Volume and Mute Control 22 ATAPI Specification 22 Clock Generation 23 PLL and Jitter Attenuation 23 OMCK System Clock Mode 24 Master Mode 24 Slave Mode 24 Digital Interfaces 25 Serial Audio Interface Signals 25 Serial Audio Interface Formats 27 ADCIN1/ADCIN2 Serial Data Format 30 One-Line Mode OLM Configurations 31

DS605F1
LIST OF FIGURES

Figure 1.Serial Audio Port Master Mode Timing 11 Figure 2.Serial Audio Port Slave Mode Timing 11 Figure 3.Control Port Timing - Format 12 Figure 4.Control Port Timing - SPI Format 13 Figure 5.Typical Connection Diagram 18 Figure 6.Typical Connection Diagram using the PLL 19 Figure 7.Full-Scale Analog Input 20 Figure 8.Full-Scale Output 21 Figure 9.ATAPI Block Diagram x = channel pair 1, 2, 3, 4 22 Figure 10.Clock Generation 23 Figure 11.Right-Justified Serial Audio Formats 27 Figure Serial Audio Formats 28 Figure 13.Left-Justified Serial Audio Formats 28 Figure 14.One Line Mode #1 Serial Audio Format 29 Figure 15.One Line Mode #2 Serial Audio Format 29

DS605F1

CS42428

Figure 16.ADCIN1/ADCIN2 Serial Audio Format 30 Figure 17.OLM Configuration #1 31 Figure 18.OLM Configuration #2 32 Figure 19.OLM Configuration #3 33 Figure 20.OLM Configuration #4 34 Figure 21.Control Port Timing in SPI Mode 35 Figure 22.Control Port Timing, Write 36 Figure 23.Control Port Timing, Read 36 Figure 24.Recommended Analog Input Buffer 61 Figure 25.Recommended Analog Output Buffer 61 Figure 26.Recommended Layout Example 63 Figure 27.Single-Speed Mode Stopband Rejection 64 Figure 28.Single-Speed Mode Transition Band 64 Figure 29.Single-Speed Mode Transition Band Detail 64 Figure 30.Single-Speed Mode Passband Ripple 64 Figure 31.Double-Speed Mode Stopband Rejection 64 Figure 32.Double-Speed Mode Transition Band 64 Figure 33.Double-Speed Mode Transition Band Detail 65 Figure 34.Double-Speed Mode Passband Ripple 65 Figure 35.Quad-Speed Mode Stopband Rejection 65 Figure 36.Quad-Speed Mode Transition Band 65 Figure 37.Quad-Speed Mode Transition Band Detail 65 Figure 38.Quad-Speed Mode Passband Ripple 65 Figure 39.Single-Speed fast Stopband Rejection 66 Figure 40.Single-Speed fast Transition Band 66 Figure 41.Single-Speed fast Transition Band detail 66 Figure 42.Single-Speed fast Passband Ripple 66 Figure 43.Single-Speed slow Stopband Rejection 66 Figure 44.Single-Speed slow Transition Band 66 Figure 45.Single-Speed slow Transition Band detail 67 Figure 46.Single-Speed slow Passband Ripple 67 Figure 47.Double-Speed fast Stopband Rejection 67 Figure 48.Double-Speed fast Transition Band 67 Figure 49.Double-Speed fast Transition Band detail 67 Figure 50.Double-Speed fast Passband Ripple 67 Figure 51.Double-Speed slow Stopband Rejection 68 Figure 52.Double-Speed slow Transition Band 68 Figure 53.Double-Speed slow Transition Band detail 68 Figure 54.Double-Speed slow Passband Ripple 68 Figure 55.Quad-Speed fast Stopband Rejection 68 Figure 56.Quad-Speed fast Transition Band 68 Figure 57.Quad-Speed fast Transition Band detail 69 Figure 58.Quad-Speed fast Passband Ripple 69 Figure 59.Quad-Speed slow Stopband Rejection 69 Figure 60.Quad-Speed slow Transition Band 69 Figure 61.Quad-Speed slow Transition Band detail 69 Figure 62.Quad-Speed slow Passband Ripple 69

DS605F1

CS42428

LIST OF TABLES

Table Common OMCK Clock Frequencies 24 Table Common PLL Output Clock 24 Table Slave Mode Clock Ratios 25 Table Serial Audio Port Channel Allocations 26 Table DAC De-Emphasis 44 Table Digital Interface Formats 45 Table ADC One-Line 45 Table DAC One-Line 45 Table RMCK Divider Settings 48 Table OMCK Frequency Settings 48 Table Master Clock Source 49 Table PLL Clock Frequency 50 Table Example Digital Volume Settings 53 Table ATAPI Decode 54 Table Example ADC Input Gain Settings 55 Table PLL External Component Values 62

DS605F1

CS42428

CHARACTERISTICS AND SPECIFICATIONS

All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.

SPECIFIED OPERATING CONDITIONS

AGND=DGND=0, all voltages with respect to ground OMCK=12.288 MHz Master Mode

Parameter

Symbol Min Typ

DC Power Supply

Analog

Digital VD

Serial Port Interface VLS

Control Port Interface VLC

Ambient Operating Temperature power applied

CS42428-CQZ

CS42428-DQZ
+70 +85

Units
°C °C

ABSOLUTE MAXIMUM RATINGS

AGND = DGND = 0 V all voltages with respect to ground.

Parameters

DC Power Supply

Analog Digital Serial Port Interface Control Port Interface

Input Current

Note 1

Analog Input Voltage

Note 2

Digital Input Voltage Note 2

Serial Port Interface Control Port Interface

Ambient Operating Temperature power applied

CS42428-CQZ CS42428-DQZ
13.ORDERING INFORMATION

Product

Package Pb-Free

CS42428
114 dB, 192 kHz 8-Ch Codec with PLL
64-pin LQFP

CDB42428 CS42428 Evaluation Board

Grade Commercial

Automotive -

Temp Range -10° to +70° C
-40° to +85° C -

Container

Order #

Tray CS42428-CQZ

Tape & Reel CS42428-CQZR

Tray CS42428-DQZ

Tape & Reel CS42428-DQZR

CDB42428
14.REFERENCES
1 Cirrus Logic, Audio Quality Measurement Specification, Version
2 Cirrus Logic, AN18 Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version February
3 Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September
4 Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the Audio Engineering Society, November
5 Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October
6 Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October
7 Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters,by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October
8 Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October
9 Philips Semiconductor, The I2C-Bus Specification Version January

DS605F1

CS42428
15.REVISION HISTORY

Release A1 A2 F1

Date May 2003 August 2004 November 2005

Changes Advance Release Added lead free part numbers. Final Release
table on page Updated ADC Input Impedance and Offset Error specifications in the

Analog Input Characteristics table on page Updated the DAC Full-Scale Voltage, Output Impedance, and Gain Drift
specifications in the Analog Output Characteristics table on page Updated specification conditions for the analog input characteristics on
page Updated specification conditions for the analog output characteristics on
page Updated specification of tds, tdh, tdpd, and tlrpd in the Switching

Characteristics table on page Corrected reference to the SW_CTRL[1:0] bits in section on page Moved the VQ and FILT+ specifications from the Analog Input

DS605F1

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CS42428-CQZR Datasheet file may be downloaded here without warranties.

Datasheet ID: CS42428-CQZR 523169