CS42418-CQZ

CS42418-CQZ Datasheet

CS42418

Part	Datasheet
CS42418-CQZ	CS42418-CQZ (pdf)

Related Parts	Information
CS42418-CQZR	CS42418-CQZR
CS42418-CQZ/C1	CS42418-CQZ/C1
CS42418-CQZR/C1	CS42418-CQZR/C1

PDF Datasheet Preview
CS42418 110 dB, 192-kHz 8-Ch CODEC with PLL Eight 24-bit D/A, two 24-bit A/D Converters 110 dB DAC / 114 dB ADC Dynamic Range -100 dB THD+N System Sampling Rates up to 192 kHz Integrated Low-Jitter PLL for Increased System Jitter Tolerance PLL Clock or System Clock Selection 7 Configurable General-Purpose Outputs ADC High-Pass Filter for DC Offset Calibration Expandable ADC Channels and One-Line Mode Support Digital Output Volume Control with Soft Ramp Digital ±15 dB Input Gain Adjust for ADC Differential Analog Architecture Supports Logic Levels between V and 5 V The CS42418 provides two analog-to-digital and eight digital-to-analog delta-sigma converters, as well as an integrated PLL. The CS42418 integrated PLL provides a low-jitter system clock. The internal stereo ADC is capable of independent channel gain control for single-ended or differential analog inputs. All eight channels of DAC provide digital volume control and differential analog outputs. The general-purpose outputs may be driven high or low, or mapped to a variety of DAC mute controls or ADC overflow indicators. The CS42418 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, and digital speakers. The CS42418 is available in a 64-pin LQFP package in Commercial -10° to +70° C grades. The CDB42428 Customer Demonstration board is also available for device evaluation. Refer to “Ordering Information” on page GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 GPO7 MUTEC VA AGND GPO AINL+ AINLAINR+ AINR- AOUTA1+ AOUTA1AOUTB1+ AOUTB1AOUTA2+ AOUTA2AOUTB2+ AOUTB2AOUTA3+ AOUTA3AOUTB3+ AOUTB3AOUTA4+ AOUTA4AOUTB4+ AOUTB4- Analog Filter ADC#1 ADC#2 REFGND VQ FILT+ OMCK RMCK LPFLT VLC DGND VD Mute Internal Voltage Reference Mult/Div PLL Control Port AD0/CS AD1/CDIN SDA/CDOUT SCL/CCLK Digital Filter Volume Control DAC Serial Audio Port Digital Filter Digital Filter DAC#1 DAC#2 DAC#3 DAC#4 DAC#5 DAC#6 DAC#7 DAC#8 Gain & Clip Gain & Clip ADC Serial Audio Port Level Translator Level Translator ADCIN1 ADCIN2 ADC_SDOUT ADC_LRCK ADC_SCLK DAC_LRCK DAC_SCLK DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4 Copyright Cirrus Logic, Inc. 2014 All Rights Reserved MAR '14 DS603F2 CS42418 TABLE OF CONTENTS CHARACTERISTICS AND SPECIFICATIONS 6 SPECIFIED OPERATING CONDITIONS 6 ABSOLUTE MAXIMUM RATINGS 6 ANALOG INPUT CHARACTERISTICS 7 A/D DIGITAL FILTER CHARACTERISTICS 8 ANALOG OUTPUT CHARACTERISTICS 9 D/A DIGITAL FILTER CHARACTERISTICS 10 SWITCHING CHARACTERISTICS 11 SWITCHING CHARACTERISTICS - CONTROL PORT - FORMAT 12 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT 13 DC ELECTRICAL CHARACTERISTICS 14 DIGITAL INTERFACE CHARACTERISTICS 15 PIN DESCRIPTIONS 16 TYPICAL CONNECTION DIAGRAMS 18 APPLICATIONS 20 Overview 20 Analog Inputs 20 Line-Level Inputs 20 High-Pass Filter and DC Offset Calibration 21 Analog Outputs 21 Line-Level Outputs and Filtering 21 Interpolation Filter 21 Digital Volume and Mute Control 22 ATAPI Specification 22 Clock Generation 23 PLL and Jitter Attenuation 23 OMCK System Clock Mode 24 Master Mode 24 Slave Mode 24 Digital Interfaces 25 Serial Audio Interface Signals 25 Serial Audio Interface Formats 27 ADCIN1/ADCIN2 Serial Data Format 30 One-Line Mode OLM Configurations 31 DS603F2 CS42418 Clock Control address 06h 48 OMCK/PLL_CLK Ratio address 07h Read Only 49 Clock Status address 08h Read Only 50 Volume Transition Control address 0Dh 51 Channel Mute address 0Eh 52 Volume Control addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h 53 Channel Invert address 17h 53 Mixing Control Pair 1 Channels A1 & B1 address 18h LIST OF FIGURES Figure Serial Audio Port Master Mode Timing 11 Figure Serial Audio Port Slave Mode Timing 11 Figure Control Port Timing - Format 12 Figure Control Port Timing - SPI Format 13 Figure Typical Connection Diagram 18 Figure Typical Connection Diagram using the PLL 19 Figure Full-Scale Analog Input 20 Figure Full-Scale Output 21 Figure ATAPI Block Diagram x = channel pair 1, 2, 3, 4 22 Figure Clock Generation 23 Figure Right-Justified Serial Audio Formats 27 Figure Serial Audio Formats 28 Figure Left-Justified Serial Audio Formats 28 Figure One Line Mode #1 Serial Audio Format 29 Figure One Line Mode #2 Serial Audio Format 29 DS603F2 CS42418 Figure ADCIN1/ADCIN2 Serial Audio Format 30 Figure OLM Configuration #1 31 Figure OLM Configuration #2 32 Figure OLM Configuration #3 33 Figure OLM Configuration #4 35 Figure Control Port Timing in SPI Mode 35 Figure Control Port Timing, Write 36 Figure Control Port Timing, Read 36 Figure Recommended Analog Input Buffer 61 Figure Recommended Analog Output Buffer 61 Figure Recommended Layout Example 63 Figure Single-Speed Mode Stopband Rejection 64 Figure Single-Speed Mode Transition Band 64 Figure Single-Speed Mode Transition Band Detail 64 Figure Single-Speed Mode Passband Ripple 64 Figure Double-Speed Mode Stopband Rejection 64 Figure Double-Speed Mode Transition Band 64 Figure Double-Speed Mode Transition Band Detail 65 Figure Double-Speed Mode Passband Ripple 65 Figure Quad-Speed Mode Stopband Rejection 65 Figure Quad-Speed Mode Transition Band 65 Figure Quad-Speed Mode Transition Band Detail 65 Figure Quad-Speed Mode Passband Ripple 65 Figure Single-Speed fast Stopband Rejection 66 Figure Single-Speed fast Transition Band 66 Figure Single-Speed fast Transition Band detail 66 Figure Single-Speed fast Passband Ripple 66 Figure Single-Speed slow Stopband Rejection 66 Figure Single-Speed slow Transition Band 66 Figure Single-Speed slow Transition Band detail 67 Figure Single-Speed slow Passband Ripple 67 Figure Double-Speed fast Stopband Rejection 67 Figure Double-Speed fast Transition Band 67 Figure Double-Speed fast Transition Band detail 67 Figure Double-Speed fast Passband Ripple 67 Figure Double-Speed slow Stopband Rejection 68 Figure Double-Speed slow Transition Band 68 Figure Double-Speed slow Transition Band detail 68 Figure Double-Speed slow Passband Ripple 68 Figure Quad-Speed fast Stopband Rejection 68 Figure Quad-Speed fast Transition Band 68 Figure Quad-Speed fast Transition Band detail 69 Figure Quad-Speed fast Passband Ripple 69 Figure Quad-Speed slow Stopband Rejection 69 Figure Quad-Speed slow Transition Band 69 Figure Quad-Speed slow Transition Band detail 69 Figure Quad-Speed slow Passband Ripple 69 DS603F2 CS42418 LIST OF TABLES Table Common OMCK Clock Frequencies 24 Table Common PLL Output Clock 24 Table Slave Mode Clock Ratios 25 Table Serial Audio Port Channel Allocations 26 Table DAC De-Emphasis 44 Table Digital Interface Formats 45 Table ADC One-Line 45 Table DAC One-Line 45 Table RMCK Divider Settings 48 Table OMCK Frequency Settings 48 Table Master Clock Source 49 Table PLL Clock Frequency 50 Table Example Digital Volume Settings 53 Table ATAPI Decode 54 Table Example ADC Input Gain Settings 55 Table PLL External Component Values 62 DS603F2 CS42418 CHARACTERISTICS AND SPECIFICATIONS All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C. SPECIFIED OPERATING CONDITIONS AGND=DGND=0, all voltages with respect to ground OMCK=12.288 MHz Master Mode Parameter Symbol Min Typ DC Power Supply Analog Digital Serial Port Interface VLS Control Port Interface VLC Ambient Operating Temperature power applied Units C ABSOLUTE MAXIMUM RATINGS AGND = DGND = 0 V all voltages with respect to ground. Parameters DC Power Supply Analog Digital Serial Port Interface Control Port Interface Input Current Note 1 Analog Input Voltage Note 2 Digital Input Voltage Note 2 Serial Port Interface Control Port Interface Ambient Operating Temperature power applied Storage Temperature VA VD VLS VLC Iin VIN VIND-S VIND-C TA Tstg AGND-0.7 13.ORDERING INFORMATION Product Package CS42418 110 dB, 192 kHz 64-pin 8-Ch Codec LQFP with PLL CDB42428 CS42418 Evaluation Board Pb-Free Grade Yes Commercial Temp Range -10° to +70° C Container Order # Tray CS42418-CQZ Tape & Reel CS42418-CQZR CDB42428 14.REFERENCES 1 Cirrus Logic, Audio Quality Measurement Specification, Version 2 Cirrus Logic, AN18 Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version February 3 Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September 4 Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the Audio Engineering Society, November 5 Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October 6 Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October 7 Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters,by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October 8 Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October 9 Philips Semiconductor, The I2C-Bus Specification Version January DS603F2 CS42418 15.REVISION HISTORY Release November 2005 March 2014 Changes • Updated registers and on page • Updated registers and on page • Updated PLL components in Table 16 on page • Added OMCK Frequency specification in the Switching Characteristics table on page • Updated ADC Input Impedance and Offset Error specifications in the Analog Input Characteristics table on page • Updated the DAC Full-Scale Voltage, Output Impedance, and Gain Drift specifications in the Analog Output Characteristics table on page • Updated specification conditions for the analog input characteristics on page • Updated specification conditions for the analog output characteristics on page • Updated specification of tds, tdh, tdpd, and tlrpd in the Switching Characteristics table on page

PDF Datasheet Preview

CS42418
110 dB, 192-kHz 8-Ch CODEC with PLL

Eight 24-bit D/A, two 24-bit A/D Converters 110 dB DAC / 114 dB ADC Dynamic Range -100 dB THD+N System Sampling Rates up to 192 kHz Integrated Low-Jitter PLL for Increased System

Jitter Tolerance PLL Clock or System Clock Selection 7 Configurable General-Purpose Outputs ADC High-Pass Filter for DC Offset Calibration Expandable ADC Channels and One-Line

Mode Support Digital Output Volume Control with Soft Ramp Digital ±15 dB Input Gain Adjust for ADC Differential Analog Architecture Supports Logic Levels between V and 5 V

The CS42418 provides two analog-to-digital and eight digital-to-analog delta-sigma converters, as well as an integrated PLL.

The CS42418 integrated PLL provides a low-jitter system clock. The internal stereo ADC is capable of independent channel gain control for single-ended or differential analog inputs. All eight channels of DAC provide digital volume control and differential analog outputs. The general-purpose outputs may be driven high or low, or mapped to a variety of DAC mute controls or ADC overflow indicators.

The CS42418 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, and digital speakers.
The CS42418 is available in a 64-pin LQFP package in Commercial -10° to +70° C grades. The CDB42428 Customer Demonstration board is also available for device evaluation. Refer to “Ordering Information” on page

GPO1 GPO2 GPO3 GPO4 GPO5 GPO6 GPO7

MUTEC

VA AGND GPO

AINL+ AINLAINR+ AINR-

AOUTA1+ AOUTA1AOUTB1+ AOUTB1AOUTA2+ AOUTA2AOUTB2+ AOUTB2AOUTA3+ AOUTA3AOUTB3+ AOUTB3AOUTA4+ AOUTA4AOUTB4+ AOUTB4-

Analog Filter

ADC#1 ADC#2

REFGND VQ FILT+ OMCK

RMCK LPFLT VLC DGND VD

Mute

Internal Voltage Reference

Mult/Div PLL

Control Port

AD0/CS AD1/CDIN SDA/CDOUT SCL/CCLK

Digital Filter Volume Control DAC Serial Audio Port

Digital Filter Digital Filter

DAC#1 DAC#2 DAC#3 DAC#4 DAC#5 DAC#6 DAC#7 DAC#8

Gain & Clip Gain & Clip

ADC Serial Audio Port

Level Translator

Level Translator

ADCIN1 ADCIN2 ADC_SDOUT ADC_LRCK

ADC_SCLK

DAC_LRCK DAC_SCLK DAC_SDIN1 DAC_SDIN2 DAC_SDIN3 DAC_SDIN4

Copyright Cirrus Logic, Inc. 2014 All Rights Reserved

MAR '14 DS603F2

CS42418

TABLE OF CONTENTS

CHARACTERISTICS AND SPECIFICATIONS 6 SPECIFIED OPERATING CONDITIONS 6 ABSOLUTE MAXIMUM RATINGS 6 ANALOG INPUT CHARACTERISTICS 7 A/D DIGITAL FILTER CHARACTERISTICS 8 ANALOG OUTPUT CHARACTERISTICS 9 D/A DIGITAL FILTER CHARACTERISTICS 10 SWITCHING CHARACTERISTICS 11 SWITCHING CHARACTERISTICS - CONTROL PORT - FORMAT 12 SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT 13 DC ELECTRICAL CHARACTERISTICS 14 DIGITAL INTERFACE CHARACTERISTICS 15

PIN DESCRIPTIONS 16 TYPICAL CONNECTION DIAGRAMS 18 APPLICATIONS 20

Overview 20 Analog Inputs 20

Line-Level Inputs 20 High-Pass Filter and DC Offset Calibration 21 Analog Outputs 21 Line-Level Outputs and Filtering 21 Interpolation Filter 21 Digital Volume and Mute Control 22 ATAPI Specification 22 Clock Generation 23 PLL and Jitter Attenuation 23 OMCK System Clock Mode 24 Master Mode 24 Slave Mode 24 Digital Interfaces 25 Serial Audio Interface Signals 25 Serial Audio Interface Formats 27 ADCIN1/ADCIN2 Serial Data Format 30 One-Line Mode OLM Configurations 31

DS603F2

CS42418

Clock Control address 06h 48 OMCK/PLL_CLK Ratio address 07h Read Only 49 Clock Status address 08h Read Only 50 Volume Transition Control address 0Dh 51 Channel Mute address 0Eh 52 Volume Control addresses 0Fh, 10h, 11h, 12h, 13h, 14h, 15h, 16h 53 Channel Invert address 17h 53 Mixing Control Pair 1 Channels A1 & B1 address 18h
LIST OF FIGURES

Figure Serial Audio Port Master Mode Timing 11 Figure Serial Audio Port Slave Mode Timing 11 Figure Control Port Timing - Format 12 Figure Control Port Timing - SPI Format 13 Figure Typical Connection Diagram 18 Figure Typical Connection Diagram using the PLL 19 Figure Full-Scale Analog Input 20 Figure Full-Scale Output 21 Figure ATAPI Block Diagram x = channel pair 1, 2, 3, 4 22 Figure Clock Generation 23 Figure Right-Justified Serial Audio Formats 27 Figure Serial Audio Formats 28 Figure Left-Justified Serial Audio Formats 28 Figure One Line Mode #1 Serial Audio Format 29 Figure One Line Mode #2 Serial Audio Format 29

DS603F2

CS42418

Figure ADCIN1/ADCIN2 Serial Audio Format 30 Figure OLM Configuration #1 31 Figure OLM Configuration #2 32 Figure OLM Configuration #3 33 Figure OLM Configuration #4 35 Figure Control Port Timing in SPI Mode 35 Figure Control Port Timing, Write 36 Figure Control Port Timing, Read 36 Figure Recommended Analog Input Buffer 61 Figure Recommended Analog Output Buffer 61 Figure Recommended Layout Example 63 Figure Single-Speed Mode Stopband Rejection 64 Figure Single-Speed Mode Transition Band 64 Figure Single-Speed Mode Transition Band Detail 64 Figure Single-Speed Mode Passband Ripple 64 Figure Double-Speed Mode Stopband Rejection 64 Figure Double-Speed Mode Transition Band 64 Figure Double-Speed Mode Transition Band Detail 65 Figure Double-Speed Mode Passband Ripple 65 Figure Quad-Speed Mode Stopband Rejection 65 Figure Quad-Speed Mode Transition Band 65 Figure Quad-Speed Mode Transition Band Detail 65 Figure Quad-Speed Mode Passband Ripple 65 Figure Single-Speed fast Stopband Rejection 66 Figure Single-Speed fast Transition Band 66 Figure Single-Speed fast Transition Band detail 66 Figure Single-Speed fast Passband Ripple 66 Figure Single-Speed slow Stopband Rejection 66 Figure Single-Speed slow Transition Band 66 Figure Single-Speed slow Transition Band detail 67 Figure Single-Speed slow Passband Ripple 67 Figure Double-Speed fast Stopband Rejection 67 Figure Double-Speed fast Transition Band 67 Figure Double-Speed fast Transition Band detail 67 Figure Double-Speed fast Passband Ripple 67 Figure Double-Speed slow Stopband Rejection 68 Figure Double-Speed slow Transition Band 68 Figure Double-Speed slow Transition Band detail 68 Figure Double-Speed slow Passband Ripple 68 Figure Quad-Speed fast Stopband Rejection 68 Figure Quad-Speed fast Transition Band 68 Figure Quad-Speed fast Transition Band detail 69 Figure Quad-Speed fast Passband Ripple 69 Figure Quad-Speed slow Stopband Rejection 69 Figure Quad-Speed slow Transition Band 69 Figure Quad-Speed slow Transition Band detail 69 Figure Quad-Speed slow Passband Ripple 69

DS603F2

CS42418

LIST OF TABLES

Table Common OMCK Clock Frequencies 24 Table Common PLL Output Clock 24 Table Slave Mode Clock Ratios 25 Table Serial Audio Port Channel Allocations 26 Table DAC De-Emphasis 44 Table Digital Interface Formats 45 Table ADC One-Line 45 Table DAC One-Line 45 Table RMCK Divider Settings 48 Table OMCK Frequency Settings 48 Table Master Clock Source 49 Table PLL Clock Frequency 50 Table Example Digital Volume Settings 53 Table ATAPI Decode 54 Table Example ADC Input Gain Settings 55 Table PLL External Component Values 62

DS603F2

CS42418

CHARACTERISTICS AND SPECIFICATIONS

All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25° C.

SPECIFIED OPERATING CONDITIONS

AGND=DGND=0, all voltages with respect to ground OMCK=12.288 MHz Master Mode

Parameter

Symbol Min Typ

DC Power Supply

Analog

Digital

Serial Port Interface VLS

Control Port Interface VLC

Ambient Operating Temperature power applied

Units
C

ABSOLUTE MAXIMUM RATINGS

AGND = DGND = 0 V all voltages with respect to ground.

Parameters

DC Power Supply

Analog Digital Serial Port Interface Control Port Interface

Input Current

Note 1

Analog Input Voltage

Note 2

Digital Input Voltage Note 2

Serial Port Interface Control Port Interface

Ambient Operating Temperature power applied

Storage Temperature

VA VD VLS VLC

Iin VIN VIND-S VIND-C TA Tstg

AGND-0.7
13.ORDERING INFORMATION

Product

Package

CS42418 110 dB, 192 kHz
64-pin
8-Ch Codec

LQFP
with PLL

CDB42428 CS42418 Evaluation Board

Pb-Free Grade Yes Commercial

Temp Range -10° to +70° C

Container

Order #

Tray

CS42418-CQZ

Tape & Reel CS42418-CQZR

CDB42428
14.REFERENCES
1 Cirrus Logic, Audio Quality Measurement Specification, Version
2 Cirrus Logic, AN18 Layout and Design Rules for Data Converters and Other Mixed Signal Devices, Version February
3 Cirrus Logic, Techniques to Measure and Maximize the Performance of a 120 dB, 96 kHz A/D Converter Integrated Circuit, by Steven Harris, Steven Green and Ka Leung. Presented at the 103rd Convention of the Audio Engineering Society, September
4 Cirrus Logic, A Stereo 16-bit Delta-Sigma A/D Converter for Digital Audio, by D.R. Welland, B.P. Del Signore, E.J. Swanson, T. Tanaka, K. Hamashita, S. Hara, K. Takasuka. Paper presented at the 85th Convention of the Audio Engineering Society, November
5 Cirrus Logic, The Effects of Sampling Clock Jitter on Nyquist Sampling Analog-to-Digital Converters, and on Oversampling Delta Sigma ADC's, by Steven Harris. Paper presented at the 87th Convention of the Audio Engineering Society, October
6 Cirrus Logic, An 18-Bit Dual-Channel Oversampling Delta-Sigma A/D Converter, with 19-Bit Mono Application Example, by Clif Sanchez. Paper presented at the 87th Convention of the Audio Engineering Society, October
7 Cirrus Logic, How to Achieve Optimum Performance from Delta-Sigma A/D and D/A Converters,by Steven Harris. Presented at the 93rd Convention of the Audio Engineering Society, October
8 Cirrus Logic, A Fifth-Order Delta-Sigma Modulator with 110 dB Audio Dynamic Range, by I. Fujimori, K. Hamashita and E.J. Swanson. Paper presented at the 93rd Convention of the Audio Engineering Society, October
9 Philips Semiconductor, The I2C-Bus Specification Version January

DS603F2

CS42418
15.REVISION HISTORY

Release

November 2005

March 2014

Changes
• Updated registers and on page
• Updated registers and on page
• Updated PLL components in Table 16 on page
• Added OMCK Frequency specification in the Switching Characteristics table on page
• Updated ADC Input Impedance and Offset Error specifications in the Analog Input

Characteristics table on page
• Updated the DAC Full-Scale Voltage, Output Impedance, and Gain Drift specifications in the

Analog Output Characteristics table on page
• Updated specification conditions for the analog input characteristics on page
• Updated specification conditions for the analog output characteristics on page
• Updated specification of tds, tdh, tdpd, and tlrpd in the Switching Characteristics table on page

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Datasheet ID: CS42418-CQZ 523167