CS4234-ENZR

CS4234-ENZR Datasheet

CS4234

Part	Datasheet
CS4234-ENZR	CS4234-ENZR (pdf)

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CS4234 4 In/5 Out CODEC with Programmable Class H Controller DAC Features Advanced multibit modulator 24-bit resolution Differential or single-ended outputs -109 dB dynamic range A-weighted -90 dB THD+N 2 Vrms full-scale output into AC load Rail-to-rail operation Programmable group delay in 4-channel audio output path ADC Features Advanced multibit modulator 24-bit resolution Differential inputs -105 dB dynamic range A-weighted -88 dB THD+N 2 Vrms full-scale input System Features TDM, left justified, and I2S serial inputs and outputs Nondelayed low-latency path Supports sample rates up to 96 kHz Class H Controller Features Can be used with any integrated Class AB amplifier IC or discrete amplifier solution. Increases efficiency of Class AB amplifiers Creates audio tracking reference signal for external switch-mode power supply Internal envelope tracking of up to 32 channels Input path for externally generated tracking signal Common Applications Discrete Class H automotive audio amplifiers Automotive head units with internal Class H amplifiers Audio mixing consoles Audio effects processors Tracking SMPS Enable AIN1 ± AIN2 ± AIN3 ± AIN4 ± Multi-bit ADC 5th DAC Input Advisory Digital Filters VL to VDC SDOUTx SDIN 2 Gain / Volume Max Detect Envelope Tracking Mute, Invert , Noise Gate TPS GAIN DAC Volume VD VDC VA VDC DC Offset Mode Select Master Vol Cntrl Select Master Volume Filter Select -1 -2 This product is available in a 40-pin QFN package in Automotive -40 °C to +105 °C temperature grade. See “Ordering Information” on page 74 for complete details. DS899F2 CS4234 TABLE OF CONTENTS PIN DESCRIPTIONS 6 I/O Pin Characteristics 7 TYPICAL CONNECTION DIAGRAM 8 CHARACTERISTICS AND SPECIFICATIONS 9 DS899F2 CS4234 Interrupt Notification 2 Address 22h Read Only 69 ADC FILTER PLOTS 70 DAC FILTER PLOTS 71 PACKAGE DIMENSIONS 73 ORDERING INFORMATION 74 APPENDIX A INTERNAL TRACKING POWER SUPPLY SIGNAL 74 LIST OF FIGURES Figure CS4234 Pinout 6 Figure Typical Connection Diagram 8 Figure Test Circuit for ADC Performance Testing 13 Figure PSRR Test Configuration 13 Figure Equivalent Output Test Load 15 Figure TDM Serial Audio Interface Timing 19 Figure PCM Serial Audio Interface Timing 19 Figure Control Port Timing 20 Figure System Level Initialization and Power-up / Power-down Sequence 23 Figure DAC DC Loading 24 Figure Timing, Write 25 Figure Timing, Read 25 Figure Master Mode Clocking 27 Figure TDM System Clock Format 28 Figure 32-bit Receiver Channel Block 29 Figure Serial Data Coding and Extraction Options within the TDM Streams 30 Figure Left Justified Format 31 Figure Format 31 Figure Audio Path Routing 32 Figure Conventional SDOUT1 Left vs. Sidechain SDOUT1 Right Configuration 33 Figure DAC1-4, Low Latency, and DAC5 Path Serial Data Source Selection 34 Figure Example Serial Data Source Selection 35 Figure ADC Path 38 Figure DAC1-4 Path 39 Figure De-emphasis Curve 40 Figure Low-latency Path 40 Figure DAC5 Path 41 Figure Volume Implementation for the DAC1-4 and Low-latency Path 43 Figure Volume Implementation for the DAC5 Path 43 Figure Soft Ramp Behavior 45 Figure Interrupt Behavior and Example Interrupt Service Routine 49 Figure ADC Stopband Rejection 70 Figure ADC Transition Band 70 Figure ADC Transition Band Detail 70 Figure ADC Passband Ripple 70 Figure ADC HPF 48 kHz 70 Figure ADC HPF 96 kHz 70 Figure SSM DAC Stopband Rejection 71 Figure SSM DAC Transition Band 71 Figure SSM DAC Transition Band Detail 71 DS899F2 CS4234 Figure SSM DAC Passband Ripple 71 Figure DSM DAC Stopband Rejection 72 Figure DSM DAC Transition Band 72 Figure DSM DAC Transition Band Detail 72 Figure DSM DAC Passband Ripple 72 Figure Package Drawing 73 Figure Progression of the Tracking Signal Through the DAC5 Path 75 Figure Directly Proportional vs. Indirectly Proportional Modes of Operation 77 Figure DAC5 TPS Modes of Operation 78 Figure DAC5 Volume and TPS Offset Controls 78 LIST OF TABLES Table Speed Modes 26 Table Common Clock Frequencies 27 Table Master Mode Left Justified and Clock Ratios 27 Table Slave Mode Left Justified and Clock Ratios 28 Table Slave Mode TDM Clock Ratios 28 Table Unmasking SDIN1 Data from DAC5 Path 36 Table Unmasking SDIN2 Data from DAC5 Path 37 Table Soft Ramp Rates 46 Table Noise Gate Bit Depth Settings 46 Table Error Reporting and Interrupt Behavior Details 47 DS899F2 PIN DESCRIPTIONS CS4234 40 SCL 39 AD0 38 AD1 37 AD2/SDOUT2 36 INT 35 RST 34 AOUT5+ 33 AOUT532 AOUT1+ 31 AOUT1- SDA 1 SDIN1 2 SDIN2 3 FS/LRCK 4 MCLK 5 SCLK 6 SDOUT1 7 VL 8 GND 9 VDREG 10 Top-Down Though Package View 30 AOUT2+ 29 AOUT228 AOUT3+ 27 AOUT326 AOUT4+ 25 AOUT424 VBIAS 23 VREF 22 VQ 21 GND AIN4+ 11 AIN4- 12 AIN3+ 13 AIN3- 14 AIN2+ 15 AIN2- 16 AIN1+ 17 AIN1- 18 FILT+ 19 VA 20 Figure CS4234 Pinout Pin Name SDA SDINx FS/LRCK MCLK SCLK SDOUT1 VL GND VDREG AINx+ AINx- FILT+ VA VQ VREF Pin # Pin Description 1 Serial Control Data Input/Output - Bidirectional data I/O for the control port. 2,3 Serial Data Input - Input channels serial audio and low latency data. Frame Synchronization Clock/Left/Right Clock Input/Output - Determines which channel or frame is currently active on the serial audio data line. 5 Master Clock Input -Clock source for the internal logic, processing, and modulators. 6 Serial Clock Input/Output -Serial Clock for the serial data port. Serial Data Output 1 Output - ADC data output into a multi-slot TDM stream or AIN1 and AIN2 ADC data output in Left Justified and modes. 8 Interface Power Input - Positive power for the digital interface level shifters. 9,21 Ground Input - Ground reference for the I/O and digital, analog sections. 10 Digital Power Output - Internally generated positive power supply for digital section. 10.ORDERING INFORMATION CS4234 Product CS4234 Description Package Pb-Free 4 In/5 Out CODEC with Programmable 40-QFN Yes Group Delay Grade Automotive Temp Range Container -40° to +105°C Rail Tape and Reel Order# CS4234-ENZ CS4234-ENZR 11.APPENDIX A INTERNAL TRACKING POWER SUPPLY SIGNAL The tracking signal for a Class H amplifier tracks the envelope of the maximum of any arbitrary number of input signals up to 32 channels for the CS4234 . This tracking signal is used to modulate the output voltage of a switch mode power supply SMPS , which serves as the rail voltages for an audio amplifier. The main goal in any tracking algorithm is to maximize the efficiency of the Class H amplifier by creating a signal that causes the rails of the SMPS, sometimes referred to as a tracking power supply or TPS, to track the amplified audio signal as closely as possible. However, the tracking algorithm must also ensure that the amplifier never clips due to the rail voltage being brought too low relative to the output voltage swing of the audio amplifier. In order to track the output voltage swing of the amplifier without causing clipping, three controls are provided to ensure the tracking signal stays above higher amplitude and ahead of occurs earlier in time the output voltage swing of the amplifier. These controls and their respective effects on the tracking signal output on DAC5 are detailed in Figure 47 and listed in the following sections. With the exception of the Gain Matching control, the appropriate levels for the tracking controls are usually determined experimentally, on an application by application basis. The reason is because the transitioning speed, or bandwidth, of the SMPS is heavily influenced by the capacitance connected to the output nets of the SMPS, the topology of the SMPS, the modulation technique, and the bandwidth of the error amplifier in the feedback loop. DS899F2 DS899F2 Figure Progression of the Tracking Signal Through the DAC5 Path Signal Color Key Signal Coming into the Block Signal Going out of the Block for simplicity only Ch. 1 is tracked Abs. Max 0V Envelope of Abs. Max Envelope of Abs. Max with Gain Applied via DAC5 Volume Control Register Envelope of Abs. Max with Gain and DC Offset Applied via TPS OFFSET Register Signals Coming into the Tracking Engine Ch. 1 Ch. 2 Ch. 3 Ch. 4 Ch. n Tracking S MPS Enable AIN1 ± AIN2 ± AIN3 ± AIN4 ± Multi-bit ADC 5th DAC I nput Advisory Digital Filters VL t o VDC S DO UTx

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CS4234
4 In/5 Out CODEC with Programmable Class H Controller

DAC Features

Advanced multibit modulator 24-bit resolution Differential or single-ended outputs -109 dB dynamic range A-weighted -90 dB THD+N 2 Vrms full-scale output into AC load Rail-to-rail operation Programmable group delay in 4-channel audio
output path

ADC Features

Advanced multibit modulator 24-bit resolution Differential inputs -105 dB dynamic range A-weighted -88 dB THD+N 2 Vrms full-scale input

System Features

TDM, left justified, and I2S serial inputs and outputs Nondelayed low-latency path Supports sample rates up to 96 kHz

Class H Controller Features

Can be used with any integrated Class AB amplifier IC or discrete amplifier solution.

Increases efficiency of Class AB amplifiers Creates audio tracking reference signal for external
switch-mode power supply Internal envelope tracking of up to 32 channels Input path for externally generated tracking signal

Common Applications

Discrete Class H automotive audio amplifiers Automotive head units with internal Class H
amplifiers Audio mixing consoles Audio effects processors

Tracking

SMPS Enable

AIN1 ±

AIN2 ± AIN3 ± AIN4 ±

Multi-bit ADC
5th DAC Input Advisory

Digital Filters

VL to VDC

SDOUTx

SDIN 2

Gain / Volume

Max Detect

Envelope Tracking

Mute, Invert , Noise Gate

TPS GAIN

DAC Volume

VD VDC

VA VDC

DC Offset

Mode Select

Master Vol Cntrl

Select

Master Volume

Filter Select
-1 -2
This product is available in a 40-pin QFN package in Automotive -40 °C to +105 °C temperature grade. See “Ordering Information” on page 74 for complete details.

DS899F2

CS4234

TABLE OF CONTENTS

PIN DESCRIPTIONS 6 I/O Pin Characteristics 7

TYPICAL CONNECTION DIAGRAM 8 CHARACTERISTICS AND SPECIFICATIONS 9

DS899F2

CS4234
Interrupt Notification 2 Address 22h Read Only 69 ADC FILTER PLOTS 70 DAC FILTER PLOTS 71 PACKAGE DIMENSIONS 73 ORDERING INFORMATION 74 APPENDIX A INTERNAL TRACKING POWER SUPPLY SIGNAL 74

LIST OF FIGURES

Figure CS4234 Pinout 6 Figure Typical Connection Diagram 8 Figure Test Circuit for ADC Performance Testing 13 Figure PSRR Test Configuration 13 Figure Equivalent Output Test Load 15 Figure TDM Serial Audio Interface Timing 19 Figure PCM Serial Audio Interface Timing 19 Figure Control Port Timing 20 Figure System Level Initialization and Power-up / Power-down Sequence 23 Figure DAC DC Loading 24 Figure Timing, Write 25 Figure Timing, Read 25 Figure Master Mode Clocking 27 Figure TDM System Clock Format 28 Figure 32-bit Receiver Channel Block 29 Figure Serial Data Coding and Extraction Options within the TDM Streams 30 Figure Left Justified Format 31 Figure Format 31 Figure Audio Path Routing 32 Figure Conventional SDOUT1 Left vs. Sidechain SDOUT1 Right Configuration 33 Figure DAC1-4, Low Latency, and DAC5 Path Serial Data Source Selection 34 Figure Example Serial Data Source Selection 35 Figure ADC Path 38 Figure DAC1-4 Path 39 Figure De-emphasis Curve 40 Figure Low-latency Path 40 Figure DAC5 Path 41 Figure Volume Implementation for the DAC1-4 and Low-latency Path 43 Figure Volume Implementation for the DAC5 Path 43 Figure Soft Ramp Behavior 45 Figure Interrupt Behavior and Example Interrupt Service Routine 49 Figure ADC Stopband Rejection 70 Figure ADC Transition Band 70 Figure ADC Transition Band Detail 70 Figure ADC Passband Ripple 70 Figure ADC HPF 48 kHz 70 Figure ADC HPF 96 kHz 70 Figure SSM DAC Stopband Rejection 71 Figure SSM DAC Transition Band 71 Figure SSM DAC Transition Band Detail 71

DS899F2

CS4234

Figure SSM DAC Passband Ripple 71 Figure DSM DAC Stopband Rejection 72 Figure DSM DAC Transition Band 72 Figure DSM DAC Transition Band Detail 72 Figure DSM DAC Passband Ripple 72 Figure Package Drawing 73 Figure Progression of the Tracking Signal Through the DAC5 Path 75 Figure Directly Proportional vs. Indirectly Proportional Modes of Operation 77 Figure DAC5 TPS Modes of Operation 78 Figure DAC5 Volume and TPS Offset Controls 78

LIST OF TABLES

Table Speed Modes 26 Table Common Clock Frequencies 27 Table Master Mode Left Justified and Clock Ratios 27 Table Slave Mode Left Justified and Clock Ratios 28 Table Slave Mode TDM Clock Ratios 28 Table Unmasking SDIN1 Data from DAC5 Path 36 Table Unmasking SDIN2 Data from DAC5 Path 37 Table Soft Ramp Rates 46 Table Noise Gate Bit Depth Settings 46 Table Error Reporting and Interrupt Behavior Details 47

DS899F2

PIN DESCRIPTIONS

CS4234
40 SCL 39 AD0 38 AD1 37 AD2/SDOUT2 36 INT 35 RST 34 AOUT5+ 33 AOUT532 AOUT1+ 31 AOUT1-

SDA 1 SDIN1 2

SDIN2 3 FS/LRCK 4

MCLK 5 SCLK 6 SDOUT1 7

VL 8 GND 9 VDREG 10

Top-Down

Though Package View
30 AOUT2+ 29 AOUT228 AOUT3+ 27 AOUT326 AOUT4+ 25 AOUT424 VBIAS 23 VREF 22 VQ 21 GND

AIN4+ 11 AIN4- 12 AIN3+ 13 AIN3- 14 AIN2+ 15 AIN2- 16 AIN1+ 17 AIN1- 18 FILT+ 19

VA 20

Figure CS4234 Pinout

Pin Name SDA SDINx

FS/LRCK

MCLK SCLK

SDOUT1

VL GND VDREG

AINx+

AINx-

FILT+ VA VQ VREF

Pin #

Pin Description
1 Serial Control Data Input/Output - Bidirectional data I/O for the control port.
2,3 Serial Data Input - Input channels serial audio and low latency data.

Frame Synchronization Clock/Left/Right Clock Input/Output - Determines which channel or frame is currently active on the serial audio data line.
5 Master Clock Input -Clock source for the internal logic, processing, and modulators.
6 Serial Clock Input/Output -Serial Clock for the serial data port.

Serial Data Output 1 Output - ADC data output into a multi-slot TDM stream or AIN1 and AIN2 ADC data output in Left Justified and modes.
8 Interface Power Input - Positive power for the digital interface level shifters.
9,21 Ground Input - Ground reference for the I/O and digital, analog sections.
10 Digital Power Output - Internally generated positive power supply for digital section.
10.ORDERING INFORMATION

CS4234

Product CS4234

Description Package Pb-Free
4 In/5 Out CODEC with Programmable 40-QFN Yes

Group Delay

Grade Automotive

Temp Range Container
-40° to +105°C

Rail

Tape and Reel

Order# CS4234-ENZ

CS4234-ENZR
11.APPENDIX A INTERNAL TRACKING POWER SUPPLY SIGNAL

The tracking signal for a Class H amplifier tracks the envelope of the maximum of any arbitrary number of input signals up to 32 channels for the CS4234 . This tracking signal is used to modulate the output voltage of a switch mode power supply SMPS , which serves as the rail voltages for an audio amplifier. The main goal in any tracking algorithm is to maximize the efficiency of the Class H amplifier by creating a signal that causes the rails of the SMPS, sometimes referred to as a tracking power supply or TPS, to track the amplified audio signal as closely as possible. However, the tracking algorithm must also ensure that the amplifier never clips due to the rail voltage being brought too low relative to the output voltage swing of the audio amplifier.

In order to track the output voltage swing of the amplifier without causing clipping, three controls are provided to ensure the tracking signal stays above higher amplitude and ahead of occurs earlier in time the output voltage swing of the amplifier. These controls and their respective effects on the tracking signal output on DAC5 are detailed in Figure 47 and listed in the following sections.

With the exception of the Gain Matching control, the appropriate levels for the tracking controls are usually determined experimentally, on an application by application basis. The reason is because the transitioning speed, or bandwidth, of the SMPS is heavily influenced by the capacitance connected to the output nets of the SMPS, the topology of the SMPS, the modulation technique, and the bandwidth of the error amplifier in the feedback loop.

DS899F2

DS899F2

Figure Progression of the Tracking Signal Through the DAC5 Path

Signal Color Key Signal Coming into the Block Signal Going out of the Block
for simplicity only Ch. 1 is tracked

Abs. Max 0V

Envelope of Abs. Max

Envelope of Abs. Max with Gain Applied via DAC5 Volume Control Register

Envelope of Abs. Max with Gain and DC Offset Applied via TPS OFFSET Register

Signals Coming into the Tracking Engine

Ch. 1

Ch. 2 Ch. 3 Ch. 4

Ch. n

Tracking

S MPS

Enable

AIN1 ±

AIN2 ± AIN3 ±

AIN4 ±

Multi-bit ADC
5th DAC I nput Advisory

Digital Filters

VL t o VDC

S DO UTx

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Datasheet ID: CS4234-ENZR 523162