CD4518BM CD4518BC CD4520BM CD4520BC Dual Synchronous Up Counters Datasheet

CD4518BM CD4518BC CD4520BM CD4520BC Dual Synchronous Up Counters

The CD4518BM CD4518BC dual BCD counter and the CD4520BM CD4520BC dual binary counter are implemented with complementary MOS (CMOS) circuits constructed with N-channel and P-channel enhancement mode transistors.

Each counter consists of two identical independent synchronous 4-stage counters The counter stages are toggle flip-flops which increment on either the positive-edge of CLOCK or negative-edge of ENABLE simplifying cascading of multiple stages Each counter can be asynchronously cleared by a high level on the RESET line All inputs are protected against static discharge by diode clamps to both VDD and VSS.

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