PEX8505-AA25BI G

PEX8505-AA25BI G Datasheet

PEX 8505 General Features

Part	Datasheet
PEX8505-AA25BI G	PEX8505-AA25BI G (pdf)

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Version 2008 PEX 8505 General Features o 5-lane PCI Express switch - Gen 1 2.5Gbps Integrated SerDes o Up to five ports x1, x2 o 15mm x 15mm, 196-ball PBGA pkg. o Typical Power Watts PEX 8505 Key Features o Standards Compliant - PCI Express Base Specification, r1.1 - PCI Power Management Interface Specification r1.2 o High Performance - Cut-thru with low packet latency - Max Payload Size of 1024 Bytes - Non-blocking internal architecture - Full line rate on all ports o PCI Express Power Management - Link power management states L0, L0s, L1, L2/L3 Ready and L3 - Device states D0 and D3hot o Quality of Service QoS - One Virtual Channel per port - Eight Traffic Classes per port - Weighted Round-Robin Ingress Port Arbitration o Reliability, Availability, Serviceability - Three Standard Hot-Plug Controllers supporting PCI SHPC spec r1.0 - Transaction layer end-to-end CRC - Poison bit support - Basic and Advanced Error Reporting support - Per port error diagnostics • Bad DLLPs • Bad TLPs • CRC errors and more - Fatal Error FATAL_ERR# signal legacy SERR equivalent - INTA# signal - Port status bits - Eight software controllable General Purpose Output GPO signals - JTAG boundary scan PEX 8505 Flexible & Versatile PCI Switch Port Configurations The PEX 8505 offers five lanes and up to five ports supporting x1 and x2 lane widths. The PEX 8505 features a flexible central packet memory that allocates a memory buffer for each port as required by the application or endpoint. This buffer allocation along with the device's flexible packet flow control minimizes bottlenecks when the upstream and aggregated downstream bandwidths do not match. High Performance The PEX 8505 architecture supports packet cut-thru with low latency 138ns . This, combined with large packet memory up to 1024 byte maximum payload size and non-blocking internal switch architecture, provides full line rate on all ports for performance hungry applications such as docking stations, control planes, embedded systems and AMC modules. End-to-End Packet Integrity The PEX 8505 provides end-to-end CRC protection ECRC and Poison-bit support to enable designs that require end-to-end data integrity. These features are optional in the PCI Express specification, but PLX provides them across its entire ExpressLane switch product line. Configuration Flexibility The PEX 8505 provides several ways to configure its operations. The device can be configured through strapping pins, I2C interface, CPU configuration cycles, or an optional serial EEPROM. This allows for easy debug during the development phase, performance monitoring during the operation phase, and driver or software upgrade. Low Power with Granular SerDes Control The PEX 8505 provides low power capability that is fully compliant with the PCI Express power management specification. For even lower power, the SerDes physical links can be programmed for desired power or turned off when unused. Port Configurations The lane width of each port can be individually configured through auto-negotiation, hardware strapping, host software configuration, I2C interface, or through an optional EEPROM. The PEX 8505 supports three port configurations 1 One x1 upstream port and four x1 downstream ports 2 One x2 upstream port and three x1 downstream ports 3 One x2 upstream port, one x2 downstream port, one x1 downstream port PEX 8505 PEX 8505 PEX 8505 SerDes Power and Signal Management The ExpressLane PEX 8505 supports software control of the SerDes outputs to allow optimization of power and signal strength in a system. The PLX SerDes implementation supports four levels of power off, low, typical, and high. The SerDes block also supports loop-back modes and advanced reporting of error conditions, which enables efficient debug and management of the entire system. Port Arbitration The PEX 8505 switch supports hardware fixed and Weighted Round-Robin Ingress Port Arbitration. This allows fine tuning of Quality of Service and efficient use of packet buffers and the system bandwidth. Suitable for control plane applications, multi-function printers, DVRs, industrial control systems, medical imaging systems, embedded systems & AMC modules, the PEX 8505 can be configured for a wide variety of form factors and applications. Control Plane Application The PEX 8505 is ideal for migrating existing PCI control planes in routers to high-speed PCI Express interface to meet increased packet processing needs. Figure 2 shows a controller card with a PEX 8505 connecting the Control Processor to as many as four devices each via a x1 port. This usage model provides connectivity to multiple devices giving the processor control over multiple devices in mid-range routers. x2 x1 Figure Port Configurations Hot-Plug for High Availability Hot-Plug capability allows users to replace hardware modules and perform maintenance without powering down the system. The PEX 8505 Hot-Plug capability and Advanced Error Reporting features make it suitable for High Availability HA applications. Ports 1, 2 & 3 include a Standard HotPlug Controller. If the PEX 8505 is used in an application where one or more of its downstream ports connect to PCI Express slots, Hot-Plug Controllers on the three downstream ports can be used to manage the hot plug event of its associated slot. Fully Compliant Power Management For applications that require power management, the ExpressLane PEX 8505 devices support both link L0, L0s, L1, L2/L3 Ready and L3 and device D0 and D3hot power management states, in compliance with the PCI Express power management specification. ASIC FPGA FPGA PEX 8505 Control Processor Memory ASIC Figure Control Plane I/O Expansion The PEX 8505 can be used in I/O expansion applications. Together with a PCI Express-to-PCI bridge, the PEX 8505 is capable of providing legacy PCI I/O expansion support. Each x1 port in the PEX 8505 provides 250MB/s bandwidth per direction and it is more than capable of supporting the various bus widths and bus speeds of legacy PCI. Please visit the for additional information on PLX’s PCI Express bridge family. South Bridge Product Ordering Information Part Number PEX 8505-AA25BI PEX 8505-AA25BI G PEX 8505-AA RDK Kit Description 5-Lane, 5-port PCI Express Switch 5-Lane, 5-port PCI Express Switch Pb-Free PEX 8505 Rapid Development Kit Base Board x1 PCIe Cable x1 PCIe Cable Adapter and RDK Port Expander Please visit the PLX Web site at or contact PLX sales at 408-774-9060 for sampling. 2008 PLX Technology, Inc. All rights reserved. PLX and the PLX logo are registered trademarks of PLX Technology, Inc. ExpressLane is a trademark of PLX Technology, Inc., which may be registered in some jurisdiction. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology, Inc. reserves the right, without notice, to make changes in product design or specification. 8505-SIL-PB-1.2 04/08

PDF Datasheet Preview

Version 2008

PEX 8505 General Features
o 5-lane PCI Express switch - Gen 1 2.5Gbps Integrated SerDes
o Up to five ports x1, x2 o 15mm x 15mm, 196-ball PBGA pkg. o Typical Power Watts

PEX 8505 Key Features
o Standards Compliant - PCI Express Base Specification, r1.1 - PCI Power Management Interface Specification r1.2
o High Performance - Cut-thru with low packet latency - Max Payload Size of 1024 Bytes - Non-blocking internal architecture - Full line rate on all ports
o PCI Express Power Management - Link power management states L0, L0s, L1, L2/L3 Ready and L3 - Device states D0 and D3hot
o Quality of Service QoS - One Virtual Channel per port - Eight Traffic Classes per port - Weighted Round-Robin Ingress Port Arbitration
o Reliability, Availability, Serviceability - Three Standard Hot-Plug Controllers supporting PCI SHPC spec r1.0 - Transaction layer end-to-end CRC - Poison bit support - Basic and Advanced Error Reporting support - Per port error diagnostics
• Bad DLLPs
• Bad TLPs
• CRC errors and more - Fatal Error FATAL_ERR# signal legacy SERR equivalent - INTA# signal - Port status bits - Eight software controllable General Purpose Output GPO signals - JTAG boundary scan

PEX 8505

Flexible & Versatile PCI Switch

Port Configurations The PEX 8505 offers five lanes and up to five ports supporting x1 and x2 lane widths. The PEX 8505 features a flexible central packet memory that allocates a memory buffer for each port as required by the application or endpoint. This buffer allocation along with the device's flexible packet flow control minimizes bottlenecks when the upstream and aggregated downstream bandwidths do not match.

High Performance The PEX 8505 architecture supports packet cut-thru with low latency 138ns . This, combined with large packet memory up to 1024 byte maximum payload size and non-blocking internal switch architecture, provides full line rate on all ports for performance hungry applications such as docking stations, control planes, embedded systems and AMC modules.

End-to-End Packet Integrity The PEX 8505 provides end-to-end CRC protection ECRC and Poison-bit support to enable designs that require end-to-end data integrity. These features are optional in the PCI Express specification, but PLX provides them across its entire ExpressLane switch product line.

Configuration Flexibility The PEX 8505 provides several ways to configure its operations. The device can be configured through strapping pins, I2C interface, CPU configuration cycles, or an optional serial EEPROM. This allows for easy debug during the development phase, performance monitoring during the operation phase, and driver or software upgrade.

Low Power with Granular SerDes Control The PEX 8505 provides low power capability that is fully compliant with the PCI Express power management specification. For even lower power, the SerDes physical links can be programmed for desired power or turned off when unused.

Port Configurations The lane width of each port can be individually configured through auto-negotiation, hardware strapping, host software configuration, I2C interface, or through an optional EEPROM.

The PEX 8505 supports three port configurations 1 One x1 upstream port and four x1 downstream ports 2 One x2 upstream port and three x1 downstream ports 3 One x2 upstream port, one x2 downstream port, one x1
downstream port

PEX 8505

PEX 8505

PEX 8505

SerDes Power and Signal Management The ExpressLane PEX 8505 supports software control of the SerDes outputs to allow optimization of power and signal strength in a system. The PLX SerDes implementation supports four levels of power off, low, typical, and high. The SerDes block also supports loop-back modes and advanced reporting of error conditions, which enables efficient debug and management of the entire system.

Port Arbitration The PEX 8505 switch supports hardware fixed and Weighted Round-Robin Ingress Port Arbitration. This allows fine tuning of Quality of Service and efficient use of packet buffers and the system bandwidth.

Suitable for control plane applications, multi-function printers, DVRs, industrial control systems, medical imaging systems, embedded systems & AMC modules, the PEX 8505 can be configured for a wide variety of form factors and applications.

Control Plane Application The PEX 8505 is ideal for migrating existing PCI control planes in routers to high-speed PCI Express interface to meet increased packet processing needs. Figure 2 shows a controller card with a PEX 8505 connecting the Control Processor to as many as four devices each via a x1 port. This usage model provides connectivity to multiple devices giving the processor control over multiple devices in mid-range routers.
x2 x1

Figure Port Configurations

Hot-Plug for High Availability Hot-Plug capability allows users to replace hardware modules and perform maintenance without powering down the system. The PEX 8505 Hot-Plug capability and Advanced Error Reporting features make it suitable for High Availability HA applications. Ports 1, 2 & 3 include a Standard HotPlug Controller. If the PEX 8505 is used in an application where one or more of its downstream ports connect to PCI Express slots, Hot-Plug Controllers on the three downstream ports can be used to manage the hot plug event of its associated slot.

Fully Compliant Power Management For applications that require power management, the ExpressLane PEX 8505 devices support both link L0, L0s, L1, L2/L3 Ready and L3 and device D0 and D3hot power management states, in compliance with the PCI Express power management specification.

ASIC

FPGA

FPGA

PEX 8505

Control Processor

Memory

ASIC

Figure Control Plane

I/O Expansion The PEX 8505 can be used in I/O expansion applications. Together with a PCI Express-to-PCI bridge, the PEX 8505 is capable of providing legacy PCI I/O expansion support. Each x1 port in the PEX 8505 provides 250MB/s bandwidth per direction and it is more than capable of supporting the various bus widths and bus speeds of legacy PCI. Please visit the for additional information on PLX’s PCI Express bridge family.

South Bridge
Product Ordering Information

Part Number PEX 8505-AA25BI PEX 8505-AA25BI G

PEX 8505-AA RDK Kit

Description 5-Lane, 5-port PCI Express Switch 5-Lane, 5-port PCI Express Switch Pb-Free PEX 8505 Rapid Development Kit Base Board x1 PCIe Cable x1 PCIe Cable Adapter and RDK Port Expander

Please visit the PLX Web site at or contact PLX sales at 408-774-9060 for sampling.
2008 PLX Technology, Inc. All rights reserved. PLX and the PLX logo are registered trademarks of PLX Technology, Inc. ExpressLane is a trademark of PLX Technology, Inc., which may be registered in some jurisdiction. All other product names that appear in this material are for identification purposes only and are acknowledged to be trademarks or registered trademarks of their respective companies. Information supplied by PLX is believed to be accurate and reliable, but PLX Technology, Inc. assumes no responsibility for any errors that may appear in this material. PLX Technology, Inc. reserves the right, without notice, to make changes in product design or specification.
8505-SIL-PB-1.2
04/08

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PEX8505-AA25BI G Datasheet file may be downloaded here without warranties.

Datasheet ID: PEX8505-AA25BI G 520504