PEX8548-AA25BI

PEX8548-AA25BI Datasheet

ExpressLane PEX 8548-AA

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PEX8548-AA25BI	PEX8548-AA25BI (pdf)

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ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book Version January 2008 Website Technical Support Phone 800 759-3735 408 774-9060 FAX 408 774-2169 Copyright 2008 by PLX Technology, Inc. All Rights Reserved Version January, 2008 PLX Technology, Inc. Copyright Information Copyright 2007 2008 PLX Technology, Inc. All Rights Reserved. The information in this document is proprietary and confidential to PLX Technology. No part of this document may be reproduced in any form or by any means or used to make any derivative work such as translation, transformation, or adaptation without written permission from PLX Technology. PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, such information is preliminary, and no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product s and/or the program s described in this documentation at any time. PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology products. PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX Technology, Inc. PCI Express is a trademark of the PCI Special Interest Group PCI-SIG . EUI-64 is a trademark of The Institute of Electrical and Electronics Engineers, Inc. IEEE All product names are trademarks, registered trademarks, or service marks of their respective owners. Document Number 8548-AA-SIL-DB-P1-1.5 ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved January, 2008 Version Date July, 2007 August, 2007 August, 2007 December, 2007 December, 2007 January, 2008 Description of Changes PEX 8548S Only • Global Changed “PBGA” to “HS BGA” Heat Slug BGA • Chapter 3 Changed J21 Ball from “VSS” to “VTT_PEX17” • Chapter 3 Changed K21 Ball from “VTT_PEX16/VTT_PEX17” to “VTT_PEX16” • Chapter 17 Added Thermal specifications, and changed Mechanical Dimensions illustration Global Applied miscellaneous corrections, changes, and enhancements throughout data book. PEX 8548S Only • Chapter 3 Removed J21 from VSS ball list Table 3-10 • Chapter 17 Updated Thermal specification illustration Figure 17-2 Global • Chapter 13 Corrected register offset 24Ch[15:12] and 254h[15:12] descriptions • Chapter 14 Updated I2C_ADDR[2:0]/I2C Slave Address values in Notes and tables, and other table values affected by the change ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved January, 2008 Audience The information in this data book is subject to change without notice. This PLX data book to be updated periodically as new information is made available. This data book provides functional details of PLX Technology’s ExpressLane PEX 8548-AA 48-Lane/ 9-Port PCI Express Gen 1 Switch, for hardware designers and software/firmware engineers. Supplemental Documentation ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved A.1 Product Ordering Information 421 A.2 United States and International Representatives and Distributors 422 A.3 Technical Support 422 ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved Registers Power Management Capability Registers 179 40h Power Management Capability 44h Power Management Status and Control Message Signaled Interrupt Capability Registers 182 48h MSI Control and Capability Header 4Ch MSI Address 50h MSI Upper Address 54h MSI Data 58h MSI Mask. PCI Express Capability Registers 184 68h PCI Express Capability List and Capability 6Ch Device Capability 70h Device Status and Control 74h Link Capability 78h Link Status and Control 7Ch Slot Capability 80h Slot Status and Control Subsystem ID and Subsystem Vendor ID Capability Registers. 203 90h Subsystem Capability 94h Subsystem ID and Subsystem Vendor ID Device Serial Number Extended Capability Registers 205 100h Device Serial Number Enhanced Capability 104h Serial Number Lower DW 108h Serial Number Upper DW ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved Registers PLX Technology, Inc. Power Budget Extended Capability Registers 207 138h Power Budget Extended Capability Header 207 13Ch Data Select 207 140h Power Budget Data. 208 144h Power Budget Capability 209 Virtual Channel Extended Capability Registers. 210 148h Virtual Channel Extended Capability 210 14Ch Port VC Capability 211 150h Port VC Capability 2 211 154h Port VC Status and Control 212 158h VC0 Resource Capability 212 15Ch VC0 Resource Control 213 160h VC0 Resource Status 213 Port Arbitration Registers 214 1A8h Port Arbitration Table Phases 0 to 215 1ACh Port Arbitration Table Phases 8 to 15 216 1B0h Port Arbitration Table Phases 16 to 217 1B4h Port Arbitration Table Phases 24 to 218 Device-Specific Registers 1C0h to FB0h 219 Device-Specific Registers Error Checking and Debug 221 1C0h Device-Specific Error Status for Egress ECC Error 222 1C4h Device-Specific Error Mask for Egress ECC Error 226 1C8h ECC Error Check Disable 230 1CCh Error Handler 32-Bit Error Status 231 1D0h Error Handler 32-Bit Error Mask 234 1DCh Debug Control 237 1E0h Power Management Hot Plug User Configuration 239 1E4h Egress Control and Status 241 1E8h Bad TLP Count. 241 1ECh Bad DLLP Count 241 1F0h Egress Performance Counter 241 1F4h Station 0/1 Lane Status/Software PEX_PORT_GOODx# LED Control 242 1F8h ACK Transmission Latency Limit 244 Device-Specific Registers Physical Layer. 245 204h Phy Receiver Not Detected and Electrical Idle Detect Masks 247 208h Phy Deskew Level Low 248 20Ch Physical Deskew Level High 252 210h Phy User Test Pattern 0 256 214h Phy User Test Pattern 4 256 218h Phy User Test Pattern 8 256 21Ch Phy User Test Pattern 12 256 220h Physical Layer Command and Status. 257 224h Port Configuration. 258 228h Physical Layer Test 259 22Ch Physical Layer 261 230h Physical Layer Port Command 266 234h SKIP Ordered-Set Interval and Port Control. 269 238h SerDes Quad 0 Diagnostic Data 270 23Ch SerDes Quad 1 Diagnostic Data 271 240h SerDes Quad 2 Diagnostic Data 272 244h SerDes Quad 3 Diagnostic Data 273 248h SerDes Nominal Drive Current Select 274 24Ch SerDes Drive Current Level 1 276 ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved January, 2008 Registers 250h SerDes Drive Current Level 2 254h SerDes Drive Equalization Level Select 1 258h SerDes Drive Equalization Level Select 2 260h Serial EEPROM Status and Control 264h Serial EEPROM Data Buffer 268h Serial EEPROM Clock Frequency 26Ch Serial EEPROM 3rd Address Byte 270h Station 2 Lane Status Device-Specific Registers I2C Interface 284 294h I2C Configuration Device-Specific Registers Bus Number CAM 285 2C8h Bus Number CAM 0 2CCh Bus Number CAM 1 2D0h Bus Number CAM 2 2E8h Bus Number CAM 8 2ECh Bus Number CAM 9 2F0h Bus Number CAM 10 2F8h Bus Number CAM 12 2FCh Bus Number CAM 13 300h Bus Number CAM Device-Specific Registers I/O CAM 289 308h I/O CAM 0 30Ah I/O CAM 1 30Ch I/O CAM 2 318h I/O CAM 8 31Ah I/O CAM 9 31Ch I/O CAM 10 320h I/O CAM 12 322h I/O CAM 13 324h I/O CAM 14 Device-Specific Registers Address-Mapping CAM 293 348h AMCAM 0 Memory Base and Limit 34Ch AMCAM 0 Prefetchable Memory Base and Limit 350h AMCAM 0 Prefetchable Memory Upper Base Address 354h AMCAM 0 Prefetchable Memory Upper Limit Address 358h AMCAM 1 Memory Base and Limit 35Ch AMCAM 1 Prefetchable Memory Base and Limit 360h AMCAM 1 Prefetchable Memory Upper Base Address 364h AMCAM 1 Prefetchable Memory Upper Limit Address 368h AMCAM 2 Memory Base and Limit 36Ch AMCAM 2 Prefetchable Memory Base and Limit 370h AMCAM 2 Prefetchable Memory Upper Base Address 374h AMCAM 2 Prefetchable Memory Upper Limit Address 3C8h AMCAM 8 Memory Base and Limit. 3CCh AMCAM 8 Prefetchable Memory Base and Limit 3D0h AMCAM 8 Prefetchable Memory Upper Base Address 3D4h AMCAM 8 Prefetchable Memory Upper Limit Address 3D8h AMCAM 9 Memory Base and Limit. 3DCh AMCAM 9 Prefetchable Memory Base and Limit 3E0h AMCAM 9 Prefetchable Memory Upper Base Address. 3E4h AMCAM 9 Prefetchable Memory Upper Limit Address 3E8h AMCAM 10 Memory Base and Limit 3ECh AMCAM 10 Prefetchable Memory Base and Limit 3F0h AMCAM 10 Prefetchable Memory Upper Base Address. 3F4h AMCAM 10 Prefetchable Memory Upper Limit Address ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved xvii Registers PLX Technology, Inc. 408h AMCAM 12 Memory Base and Limit 301 40Ch AMCAM 12 Prefetchable Memory Base and Limit. 301 410h AMCAM 12 Prefetchable Memory Upper Base Address 301 414h AMCAM 12 Prefetchable Memory Upper Limit Address. 301 418h AMCAM 13 Memory Base and Limit 302 41Ch AMCAM 13 Prefetchable Memory Base and Limit. 302 420h AMCAM 13 Prefetchable Memory Upper Base Address 302 424h AMCAM 13 Prefetchable Memory Upper Limit Address. 302 428h AMCAM 14 Memory Base and Limit 303 42Ch AMCAM 14 Prefetchable Memory Base and Limit. 303 430h AMCAM 14 Prefetchable Memory Upper Base Address 303 434h AMCAM 14 Prefetchable Memory Upper Limit Address. 303 Device-Specific Registers Ingress Control and Port Enable 304 660h Ingress Control 304 664h Ingress Control Shadow 305 668h Ingress Port Enable 306 66Ch Negotiated Link Width for Ports 0, 1, 2 307 670h Negotiated Link Width for Ports 8, 9, 10, 12, 13, 14 308 Device-Specific Registers I/O CAM Base and Limit Upper 16 Bits 310 680h I/OCAM Upper Port 0 311 684h I/OCAM Upper Port 1 311 688h I/OCAM Upper Port 2 311 6A0h I/OCAM Upper Port 8 312 6A4h I/OCAM Upper Port 9 312 6A8h I/OCAM Upper Port 10 312 6B0h I/OCAM Upper Port 12 313 6B4h I/OCAM Upper Port 13 313 6B8h I/OCAM Upper Port 14 313 Device-Specific Registers Base Address Shadow 314 6C0h BAR0 Shadow for Port 0 315 6C4h BAR1 Shadow for Port 0 315 6C8h BAR0 Shadow for Port 1 316 6CCh BAR1 Shadow for Port 1 316 6D0h BAR0 Shadow for Port 2 317 6D4h BAR1 Shadow for Port 2 317 700h BAR0 Shadow for Port 318 704h BAR1 Shadow for Port 318 708h BAR0 Shadow for Port 319 70Ch BAR1 Shadow for Port 9 319 710h BAR0 Shadow for Port 320 714h BAR1 Shadow for Port 320 720h BAR0 Shadow for Port 321 724h BAR1 Shadow for Port 321 728h BAR0 Shadow for Port 322 72Ch BAR1 Shadow for Port 13 322 730h BAR0 Shadow for Port 323 734h BAR1 Shadow for Port 323 Device-Specific Registers Shadow Virtual Channel Capability. 324 740h VC0 Port 0 Capability 325 748h VC0 Port 1 Capability 325 750h VC0 Port 2 Capability 325 780h VC0 Port 8 Capability 326 788h VC0 Port 9 Capability 326 790h VC0 Port 10 Capability 326 ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version xviii Copyright 2008 by PLX Technology, Inc. All Rights Reserved The PEX 8548 groups 16 SerDes together into a station, which can be comprised of one to three ports. Refer to Table The station forwards ingress packets to the internal fabric and central RAM, and the station pulls egress packets from the central RAM to send out of the PEX Each station implements the PCI Express PHY Layer and Data Link Layer DLL functions for each of its ports, and aggregates traffic from these ports onto a transaction-based, non-blocking internal fabric. The PCI Express station also performs many Transaction Layer functions, while the packet queuing and ordering aspects of this layer are handled by the Crossbar Switch Control blocks. During system initialization, software initiates Configuration requests that set up the PCI Express interfaces, Device Numbers, and Address maps across the various ports. These maps are used to direct traffic between ports during standard system operation. Traffic flow between different ports of the same station, or ports on different stations, is supported through the central internal fabric. Functional Blocks At the top level, each station has a layered organization consisting of the Physical PHY , Data Link Layer DLL , and Transaction Layer Control TLC blocks, as illustrated in Figure The PHY and DLL blocks have port-specific data paths one per PCI Express port that operate independently of one another. The TLC ingress aggregates traffic for all ingress ports in the station, then sends the traffic to the internal fabric. The TLC egress accepts packets, by way of the internal fabric, from all ingress ports, and schedules them to be sent out the appropriate egress port. Figure PCI Express Station Block Diagram Non-Blocking Crossbar Switch Fabric Transaction Layer Control TLC Ingress TLC Egress Ingress Credit Unit CSR Handling Egress Credit Unit DLL Ingress 0-2 Data Link Layer DLL Egress 0-2 Port Enum. Logic Physical Layer Port Receive Logic Link Receive and Transmit Logic 16 Serial Lanes ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved Functional Overview PLX Technology, Inc. Physical Layer For details, refer to Section “Physical Layer.” Data Link Layer The Data Link Layer DLL serves as an intermediate stage between the Transaction Layer and the Physical Layer. The primary responsibility of the Data Link Layer includes link management and data integrity, including error detection and correction. The transmission side of the Data Link Layer accepts Transaction Layer Packets TLPs assembled by the Transaction Layer, calculates and applies data protection code and TLP Sequence Number, and submits them to the Physical Layer for transmission across the link. The receiving Data Link Layer is responsible for checking the integrity of received TLPs and submitting them to the Transaction Layer for further processing. On detection of TLP error s , this Layer is responsible for requesting re-transmission of TLPs until the information is correctly received, or the link is determined to have failed. For further details, refer to Section “Data Link Layer.” Transaction Layer Control The upper layer of the architecture is the Transaction Layer TL . The TL’s primary responsibility is the assembly and disassembly of TLPs. TLPs are used to communicate transactions, such as Read and Write, as well as certain types of events. The Transaction Layer is also responsible for managing credit-based flow control for TLPs. Every Request packet requiring a Response packet is implemented as a Split Transaction. Each packet has a unique identifier that enables Response packets to be directed to the correct originator. The packet format supports different forms of addressing, depending upon the transaction type Memory, I/O, Configuration, and Message. The packets can also have attributes, such as No Snoop and Relaxed Ordering. The TL supports four Address spaces it includes the three PCI Address spaces Memory, I/O, and Configuration and adds a Message space. This specification uses Message space to support all prior sideband signals, such as interrupts, Power Management requests, and so forth, as in-band Message transactions. PCI Express Message transactions can be thought of as virtual wires, because their effect is to eliminate the wide array of sideband signals currently used in a platform implementation. The PEX 8548 does not support Locked transactions. This is consistent with limitations for Locked transaction use, as outlined in the PCI r3.0 Appendix F, “Exclusive Accesses” , and prevents potential deadlock, as well as serious performance degradation, that could occur with Locked transaction use. The PEX 8548 responds to “lock”-type Read Requests MRdLk with a Completion, having a Completion with status of Unsupported Request UR . For further details, refer to Section “Transaction Layer.” ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved January, 2008 Cut-Thru Mode Non-Blocking Crossbar Switch Architecture The Non-Blocking Crossbar switch is an on-chip interconnect switching fabric. The Crossbar Switch architecture is built upon the existing PLX Switch Fabric Architecture technology. In addition to addressing simultaneous multiple flows, the Crossbar Switch architecture incorporates functions required to support an efficient PCI Express switch fabric, including: • Deadlock avoidance • Priority preemption • PCI Express Ordering rules • Packet fair queuing • Oldest first scheduling The Crossbar Switch interconnect physical topology is that of a packet-based Crossbar Switch fabric internal fabric designed to simultaneously connect multiple on-chip stations. The Crossbar Switch protocol is sufficiently flexible and robust to support a variety of embedded system requirements. The protocol is specifically designed to ease chip integration by strongly enforcing station boundaries and standardizing communication between stations. The Crossbar Switch architecture basic features include: • Multiple concurrent Data transfers • Global ordering within the switch • Three types of transactions Posted, Non-Posted, and Completion P, NP, and Cpl, respectively meet PCI and PCI Express Ordering and Deadlock Avoidance rules • Optional weighting of source ports to support Source Port arbitration Cut-Thru Mode The PEX 8548 is designed to cut through TLPs to and from every port. By default, all ports are enabled for Cut-Thru. Cut-Thru mode can reduce latency, especially for longer packets, because the entire packet does not need to be stored before being forwarded. Instead, after the header is decoded, the packet can be immediately forwarded. Cut-Thru mode can be disabled for all ports by clearing the Debug Control register Cut-Thru Enable bit Port 0, offset 1DCh[21] . Note The Debug Control register Cut-Thru Enable bit affects the entire chip. If Cut-Thru is enabled, all ports use Cut-Thru. If Cut-Thru is not enabled, no ports use Cut-Thru. Caution: One of the drawbacks to using Cut-Thru mode is that the TLP is not known to be good until the last byte. If the TLP proves to be bad, the Cut-Thru packet must be discarded. If the TLP has already been forwarded to another device, that TLP will be framed with an EDB End Data Bad , as opposed to the standard END. ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved Functional Overview PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved Chapter 5 Reset and Initialization Reset Overview Reset is a mechanism that returns a device to its initial state. Hardware or software mechanisms can trigger a reset. The re-initialized states following a reset vary, depending upon the reset type and condition. The PCI Express Base r1.1, Section defines the hardware mechanism as Fundamental Reset. Two actions can trigger a Fundamental Reset: • Cold Reset • Warm Reset There is also a type of reset triggered by an in-band signal from an upstream PCI Express link to all its downstream ports, which is called a Hot Reset. There is also a Secondary Bus Reset. Any PCI-to-PCI bridge can reset its downstream hierarchy by setting the Bridge Control register Secondary Bus Reset bit offset 3Ch[22]=1 . Upon exit from a Cold or Warm Reset, all port configurations, port registers, and state machines are set to initial start-up values, as specified in Section “Initialization Procedure.” Cold Reset A Cold Reset is a Fundamental Reset that occurs following a proper PEX 8548 power-on. When the PEX_PERST# signal is held Low following the proper application of power to the component, a Fundamental Reset occurs. A Fundamental Reset initializes the entire PEX 8548 device such as configuration information, clocks, state machines, registers, and so forth . When power is removed from the device, or travels outside required ranges, all settings and configuration information is lost. The device must cycle through the entire Initialization Procedure after power is accurately re-applied. Warm Reset The Fundamental Reset mechanism can also be triggered by driving the PEX 8548 hardware Reset signal PEX_PERST# Low, without the removal and re-application recycling of power. This is considered a Warm Reset. PEX_PERST# can be controlled by on-board toggle switches or other external hardware resets to the device. The PEX 8548 must cycle through the entire Initialization Procedure after the PEX_PERST# Input signal is returned to High. ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved Reset and Initialization PLX Technology, Inc. Hot Reset A Hot Reset is equivalent to a traditional Software Reset. Triggered by an in-band signal from an upstream PCI Express link to all downstream ports, a Hot Reset causes all ports that are downstream from the initiating port to set their registers and state machines to initial values. This type of reset does not require power cycling, nor does it cause PEX 8548 port re-configuration. However, a Hot Reset: • Causes all TLPs held in the PEX 8548 to be dropped • Returns all State machines to their initial default values • Returns all Non-Sticky register bits to their initial default conditions refer to Table 13-4, “Register Types, Grouped by User Accessibility,” for further details regarding Sticky register bit types A Hot Reset is triggered by the following actions • Physical Layer at the upstream port receives a reset through a training sequence leading to a Hot Reset • Upstream PCI Express port enters the DL_Inactive state, which has the same effect as a Hot Reset Note In the following sections, the terms “virtual PCI-to-PCI bridge” and “port” refer to a given Station port. Hot Reset Propagation A Hot Reset is propagated to a downstream PCI Express device through the PCI Express link, using the Physical Layer Hot Reset mechanism that is, a Reset bit in the Training Ordered-Set from the upstream device is set . PCI Express views a switch as a hierarchy of virtual PCI-to-PCI bridges. An example of reset propagation across the PEX 8548 switch is illustrated in Figure Upon receiving a Hot Reset from the upstream PCI Express link, the virtual primary PCI-to-PCI bridge propagates the reset to virtual secondary PCI-to-PCI bridges for the ports in all stations. Each virtual secondary PCI-to-PCI bridge propagates the reset to its downstream links, and initializes its internal states to initial/default conditions. A Hot Reset does not impact Clock Logic, Port Configuration, nor Sticky register bits. Figure PEX 8548 System Reset Propagation Example Upstream Port Upstream P-P Bridge Downstream P-P Bridges Downstream Ports Reset Propagation Station 0 Ordering Virtual Channel Management Flow Control VC0 Transmit Buffer Link Packet Sequence TLP LCRC DeMUX Data Link Layer DLLP Type Data CRC DLLP Type Data CRC LCRC Seq. Num TLP Check Link Packet Sequence TLP LCRC TLP Replay Buffers MUX Physical Packet Physical Layer Physical Packet Start Link Packet Start Link Packet Link Training Decode Serial-to-Parallel Encode Parallel-to-Serial Link Receive and Transmit Logic 16 Serial Lanes ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved Device Layers PLX Technology, Inc. Physical Layer The Physical Layer PHY is responsible for converting information received from the DLL into an appropriate serialized format and transmitting it across the PCI Express link. The PHY also receives the serialized input from the SerDes, converts it to parallel data internal Data Bus , then writes it to the TLC Ingress buffer. The Physical Layer includes all circuitry for PCI Express Link interface operation, including: • Driver and input buffers • Parallel-to-serial and serial-to-parallel conversion • PLLs and clock circuitry • Impedance matching circuitry • Interface initialization and maintenance functions The PHY module interfaces to the PCI Express lanes and implements the PHY Layer functions. The number of ports per station can vary from one to three, with a cumulative lane bandwidth of x16 on each station. PHY functions include: the programmed MPS • Checks and removes DLLP and TLP LCRC • Link state Power Management Supports L0, L0s, L1, L2/L3 Ready, and L3 • Supports cross-linked upstream port and downstream ports • Sequential packets are transmitted on consecutive lanes ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved January, 2008 PHY Status and Command Registers PHY Status and Command Registers • Decoding and checking rules for the incoming TLP • Memory-Mapped CSR access • Checking incoming packets for malformed or unsupported packets • Data Poisoning and end-to-end data integrity detection • ECRC checking of incoming packets • Error logging and reporting for incoming packets • TLP packet dispatching • Write control to the packet RAM and packet link list RAM • Destination lookup and TC-VC mapping • Shadow CSR registers for AMCAM/BusNoCAM/TC-VC mapping • Message Signaled Interrupt or INTx generation • Credit-based scheduling • Pipelined full Split Transaction protocol • PCI/PCI-X-compatible ordering • Interrupt handling INTx or Message Signal Interrupt • Power Management support • Hot Plug and PCI Express Hot Plug support • Link State event support • QoS support • Ordering • Ingress and Egress credit management ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved Device Layers PLX Technology, Inc. The hardware functions provided by the PEX 8548 to implement PCI Express Base r1.1 TL requirements are illustrated in Figure The blocks provide a combination of Ingress and Egress control, as well as the data management at each stage in the flow sequence. Figure TL Controller To Another Port From Another Port TLP Ingress Control TLP Egress Control AMCAM BusNoCAM CSRs Transaction Layer Packet Decode and Processing Egress Credit Unit Link Packet Ingress TLP Egress Update Flow Credit Advertise Control DLL Interface ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved January, 2008 Virtual Channel and Traffic Classes Virtual Channel and Traffic Classes The PEX 8548 supports one Virtual Channel VC0 and eight Traffic Classes TC[7:0] . VC0 and TC0 are required by the PCI Express Base r1.1, and configured at device start-up. TL Transmit/Egress Protocol The egress side TL receives TLP information from the internal fabric and makes a decision, based upon credit and ordering, regarding which TLP to send next from an Egress port. The PEX 8548 implements the PCI Express Base r1.1-specified Flow Control FC protocol, which ensures that it does not transmit a TLP over a link to a remote receiver unless the receiving device contains sufficient Buffer space to accommodate the packet. This flow control is automatically managed by the hardware and is transparent to software. Software is used only to enable additional buffers, to supplement the initial default buffer assignment. Headers The Headers contain three or four DWords that can include the following • Address/Routing 32 or 64 bits • TLP Type • Transfer Size Write requests = Total outgoing DWords Read requests = Requested DWords from Completer • Requester ID or Completer ID • Tag Used to identify a completion TLP • Traffic Class • Byte Enables • Completion status • Digest One bit indicating ECRC presence • Attributes Data Payloads The Data Payloads are variable length with a maximum of 1,024 bytes, as defined by the Maximum Payload Size field available sizes are 128, 256, 512, and 1,024, depending upon the number of ports used . Read requests do not include a Data Payload. Note Refer to the Device Control register Maximum Payload Size field offset 70h[7:5] for Maximum Payload Size port limitations. End-to-End Cyclic Redundancy Check End-to-end Cyclic Redundancy Check ECRC is an optional 32-bit field appended to the end of the outgoing packet. ECRC is calculated over the entire packet, starting with the Header and including the Data Payload, except for the EP bit and bit 0 of the Type field, which are always considered to be a value of 1 for ECRC calculations. The ECRC field is transmitted, unchanged, as it moves through the fabric to the completer device. The PEX 8548 checks the ECRC on all incoming TLPs if enabled, and can optionally report detected errors. [When the ECRC is detected, the Uncorrectable Error Status register ECRC Error Status bit offset FB8h[19] can be used to log ECRC errors.] Additionally, the PEX 8548 can optionally append ECRC to the end of internally generated TLPs, such as Interrupt and Error messages, if enabled. ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved Device Layers PLX Technology, Inc. TL Receive/Ingress Protocol The ingress side TL collects and stores inbound TLP traffic in the packet RAM. The incoming data is checked for ECRC errors, valid type field, length matching the Header Transfer Size field, and other TLP-specific errors defined by the PCI Express Base r1.1. Header and Data Payload information is forwarded to the Source Scheduler, to be routed across the internal fabric, to the Egress port. When CRC errors are detected, the packet is discarded. Flow Control Protocol The PEX 8548 implements Flow Control FC protocol that ensures it does not transmit a TLP over a link to a remote Receiver, unless the receiving device has sufficient VC Buffer space to accommodate the packet. This FC is automatically managed by the hardware and is transparent to software. Software is used only to enable additional buffers, to supplement the initial default buffer assignment. The initial default FC DLLP buffers, which are enabled after link training, allow TLP traffic immediately following the link training. The Configuration transactions are the first transactions to use the default VC buffers to set up the initial device operating modes and capabilities. The TL Egress Credit Unit transmits DLL packets, called FC packets, that update the FC to the transmitter device on a periodic basis. The updated DLLPs contain FC credit information that updates the transmitter regarding the amount of available buffer space in the receiver VC buffer. The transmitter tracks this information and transmits TLPs only when it perceives that the remote receiver contains sufficient Buffer space to accept the transmitted TLPs. ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved Chapter 10 Serial EEPROM Controller Overview The PEX 8548 provides an interface to SPI Serial Peripheral Interface -compatible serial EEPROMs. This interface consists of a Chip Select, Clock, Write Data, and Read Data balls, and operates at a programmable frequency of up to MHz. The PEX 8548 supports up to a 16-MB serial EEPROM, utilizing 1-, 2-, or 3-byte addressing. The PEX 8548 automatically determines the appropriate addressing mode. The primary function of the Serial EEPROM Controller is to allow access to non-volatile memory from the PEX This is accomplished using two different methods: • The first method of access to a serial EEPROM device is during initialization. When a serial EEPROM device is connected to the PEX 8548, during initialization, the Serial EEPROM Controller reads data from the serial EEPROM to be used to update the default values of registers within the PEX • The second method of access is controlled by software initiating a Read or Write Request to the serial EEPROM, to store or retrieve other data. The on-chip Serial EEPROM Controller is integrated into the PEX 8548, as illustrated in Figure The controller performs a serial EEPROM download when the following conditions exist: • Serial EEPROM is present, and • Validation signature first byte read from the serial EEPROM value is 5Ah, and • One of the following events occur: PEX_PERST# is returned High, following a Fundamental Reset such as, a Cold or Warm Reset Hot Reset is received at the upstream port [downloading upon this event can be optionally disabled, by setting the Debug Control register Disable Serial EEPROM Load on Hot Reset bit Port 0, offset 1DCh[17]=1 ] Upstream port exits a DL_Down state [downloading upon this event can be optionally disabled, by setting the Debug Control register Upstream Port DL_Down Reset Propagation Disable bit Port 0, offset 1DCh[20]=1 ] ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved Serial EEPROM Controller PLX Technology, Inc. Initialization Serial EEPROM EE_CS# EE_DI EE_DO PCI Express Relaxed Ordering Enable 4 Not supported Cleared to Maximum Payload Size Software can change this field to configure the PEX 8548 ports to support other Payload Sizes however, software cannot change this field to a value larger than that indicated by the Device Capability register Maximum Payload Size Supported field offset 6Ch[2:0] . Maximum Payload Size port limitations are as follows: • 1,024 if the number of ports is < 3 • 512 if the number of ports is < 5 • 256 if the number of ports is < 9 000b = Indicates that initially, the PEX 8548 port is configured to support a Maximum Payload Size of 128 bytes 001b = Indicates that initially, the PEX 8548 port is configured to support a Maximum Payload Size of 256 bytes 010b = Indicates that initially, the PEX 8548 port is configured to support a Maximum Payload Size of 512 bytes 011b = Indicates that initially, the PEX 8548 port is configured to support a Maximum Payload Size of 1,024 bytes Type RW RsvdP Serial EEPROM and I2C Default 000b ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved Port Registers Register 70h Device Status and Control All Ports Cont. Bit s 8 9 10 11 14:12 15 Extended Tag Field Enable Not supported Cleared to Phantom Functions Enable Not supported Cleared to AUX Power PM Enable Not supported Cleared to Enable No Snoop Not supported Cleared to Maximum Read Request Size Not supported Cleared to 000b. Reserved Hardwired to 0, as required by the PCI Express Base r1.1. PLX Technology, Inc. Type Serial EEPROM and I2C Default RsvdP RsvdP RsvdP RsvdP RsvdP RsvdP 000b 0 ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved Product Ordering Information Contact your local PLX Sales Representative for ordering information. Table A-1. PEX 8548 Product Ordering Information Part Numbers PEX8548-AA25BI PEX 8548-AA 48-Lane, 9-port PCI Express Gen 1 Switch Plastic BGA-H3 x mm2, 736-ball Package PEX8548-AA25BI G PEX 8548-AA 48-Lane, 9-port PCI Express Gen 1 Switch Plastic BGA-H3 x mm2, 736-ball , Lead-Free RoHS Green Package PEX8548-AA25B I G PEX 8548-AA RDK Breakout Board-88 Breakout Board-844 x1 Adapter x4 Adapter x8 Adapter G Lead-Free, RoHS-Compliant, Fully Green I Industrial Temperature B Ball Grid Array Package 8548 Part Number PEX PCI Express Product Family PEX 8548-AA Rapid Development Kit with x16 Edge Connector Breakout Board with x16 Edge Connector for Additional Fan-Out to Two Slots x8, x8 Breakout Board with x16 Edge Connector for Additional Fan-Out to Three Slots x8, x4, x4 PCI Express x16 to x1 Adapter PCI Express x16 to x4 Adapter PCI Express x16 to x8 Adapter ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved General Information PLX Technology, Inc. A.2 A.3 United States and International Representatives and Distributors PLX Technology, Inc., representatives and distributors are listed at Technical Support PLX Technology, Inc., technical support information is listed at or call 800 759-3735 domestic only or 408 ExpressLane PEX 8548-AA 48-Lane/9-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2008 by PLX Technology, Inc. All Rights Reserved

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FAX 408 774-2169

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Copyright Information

Copyright 2007 2008 PLX Technology, Inc. All Rights Reserved. The information in this document is proprietary and confidential to PLX Technology. No part of this document may be reproduced in any form or by any means or used to make any derivative work such as translation, transformation, or adaptation without written permission from PLX Technology.

PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, such information is preliminary, and no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product s and/or the program s described in this documentation at any time.

PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology products.

PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX Technology, Inc.

PCI Express is a trademark of the PCI Special Interest Group PCI-SIG .

EUI-64 is a trademark of The Institute of Electrical and Electronics Engineers, Inc. IEEE

All product names are trademarks, registered trademarks, or service marks of their respective owners.

Document Number 8548-AA-SIL-DB-P1-1.5

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Version

Date July, 2007 August, 2007 August, 2007 December, 2007

December, 2007

January, 2008

Description of Changes

PEX 8548S Only
• Global Changed “PBGA” to “HS BGA” Heat Slug BGA
• Chapter 3 Changed J21 Ball from “VSS” to “VTT_PEX17”
• Chapter 3 Changed K21 Ball from “VTT_PEX16/VTT_PEX17” to “VTT_PEX16”
• Chapter 17 Added Thermal specifications, and changed Mechanical Dimensions illustration

Global Applied miscellaneous corrections, changes, and enhancements throughout data book.

PEX 8548S Only
• Chapter 3 Removed J21 from VSS ball list Table 3-10
• Chapter 17 Updated Thermal specification illustration Figure 17-2

Global
• Chapter 13 Corrected register offset 24Ch[15:12] and 254h[15:12] descriptions
• Chapter 14 Updated I2C_ADDR[2:0]/I2C Slave Address values in Notes and tables, and other table values affected by the change

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Audience

The information in this data book is subject to change without notice. This PLX data book to be updated periodically as new information is made available.

This data book provides functional details of PLX Technology’s ExpressLane PEX 8548-AA 48-Lane/ 9-Port PCI Express Gen 1 Switch, for hardware designers and software/firmware engineers.

Supplemental Documentation

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A.1 Product Ordering Information 421 A.2 United States and International Representatives and Distributors 422 A.3 Technical Support 422

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Registers

Power Management Capability Registers 179 40h Power Management Capability 44h Power Management Status and Control

Message Signaled Interrupt Capability Registers 182 48h MSI Control and Capability Header 4Ch MSI Address 50h MSI Upper Address 54h MSI Data 58h MSI Mask.

PCI Express Capability Registers 184 68h PCI Express Capability List and Capability 6Ch Device Capability 70h Device Status and Control 74h Link Capability 78h Link Status and Control 7Ch Slot Capability 80h Slot Status and Control

Subsystem ID and Subsystem Vendor ID Capability Registers. 203 90h Subsystem Capability 94h Subsystem ID and Subsystem Vendor ID

Device Serial Number Extended Capability Registers 205 100h Device Serial Number Enhanced Capability 104h Serial Number Lower DW 108h Serial Number Upper DW

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Registers

PLX Technology, Inc.

Power Budget Extended Capability Registers 207 138h Power Budget Extended Capability Header 207 13Ch Data Select 207 140h Power Budget Data. 208 144h Power Budget Capability 209

Virtual Channel Extended Capability Registers. 210 148h Virtual Channel Extended Capability 210 14Ch Port VC Capability 211 150h Port VC Capability 2 211 154h Port VC Status and Control 212 158h VC0 Resource Capability 212 15Ch VC0 Resource Control 213 160h VC0 Resource Status 213

Port Arbitration Registers 214 1A8h Port Arbitration Table Phases 0 to 215 1ACh Port Arbitration Table Phases 8 to 15 216 1B0h Port Arbitration Table Phases 16 to 217 1B4h Port Arbitration Table Phases 24 to 218

Device-Specific Registers 1C0h to FB0h 219

Device-Specific Registers Error Checking and Debug 221 1C0h Device-Specific Error Status for Egress ECC Error 222 1C4h Device-Specific Error Mask for Egress ECC Error 226 1C8h ECC Error Check Disable 230 1CCh Error Handler 32-Bit Error Status 231 1D0h Error Handler 32-Bit Error Mask 234 1DCh Debug Control 237 1E0h Power Management Hot Plug User Configuration 239 1E4h Egress Control and Status 241 1E8h Bad TLP Count. 241 1ECh Bad DLLP Count 241 1F0h Egress Performance Counter 241 1F4h Station 0/1 Lane Status/Software PEX_PORT_GOODx# LED Control 242 1F8h ACK Transmission Latency Limit 244

Device-Specific Registers Physical Layer. 245 204h Phy Receiver Not Detected and Electrical Idle Detect Masks 247 208h Phy Deskew Level Low 248 20Ch Physical Deskew Level High 252 210h Phy User Test Pattern 0 256 214h Phy User Test Pattern 4 256 218h Phy User Test Pattern 8 256 21Ch Phy User Test Pattern 12 256 220h Physical Layer Command and Status. 257 224h Port Configuration. 258 228h Physical Layer Test 259 22Ch Physical Layer 261 230h Physical Layer Port Command 266 234h SKIP Ordered-Set Interval and Port Control. 269 238h SerDes Quad 0 Diagnostic Data 270 23Ch SerDes Quad 1 Diagnostic Data 271 240h SerDes Quad 2 Diagnostic Data 272 244h SerDes Quad 3 Diagnostic Data 273 248h SerDes Nominal Drive Current Select 274 24Ch SerDes Drive Current Level 1 276

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Registers
250h SerDes Drive Current Level 2 254h SerDes Drive Equalization Level Select 1 258h SerDes Drive Equalization Level Select 2 260h Serial EEPROM Status and Control 264h Serial EEPROM Data Buffer 268h Serial EEPROM Clock Frequency 26Ch Serial EEPROM 3rd Address Byte 270h Station 2 Lane Status

Device-Specific Registers I2C Interface 284 294h I2C Configuration

Device-Specific Registers Bus Number CAM 285 2C8h Bus Number CAM 0 2CCh Bus Number CAM 1 2D0h Bus Number CAM 2 2E8h Bus Number CAM 8 2ECh Bus Number CAM 9 2F0h Bus Number CAM 10 2F8h Bus Number CAM 12 2FCh Bus Number CAM 13 300h Bus Number CAM

Device-Specific Registers I/O CAM 289 308h I/O CAM 0 30Ah I/O CAM 1 30Ch I/O CAM 2 318h I/O CAM 8 31Ah I/O CAM 9 31Ch I/O CAM 10 320h I/O CAM 12 322h I/O CAM 13 324h I/O CAM 14

Device-Specific Registers Address-Mapping CAM 293 348h AMCAM 0 Memory Base and Limit 34Ch AMCAM 0 Prefetchable Memory Base and Limit 350h AMCAM 0 Prefetchable Memory Upper Base Address 354h AMCAM 0 Prefetchable Memory Upper Limit Address 358h AMCAM 1 Memory Base and Limit 35Ch AMCAM 1 Prefetchable Memory Base and Limit 360h AMCAM 1 Prefetchable Memory Upper Base Address 364h AMCAM 1 Prefetchable Memory Upper Limit Address 368h AMCAM 2 Memory Base and Limit 36Ch AMCAM 2 Prefetchable Memory Base and Limit 370h AMCAM 2 Prefetchable Memory Upper Base Address 374h AMCAM 2 Prefetchable Memory Upper Limit Address 3C8h AMCAM 8 Memory Base and Limit. 3CCh AMCAM 8 Prefetchable Memory Base and Limit 3D0h AMCAM 8 Prefetchable Memory Upper Base Address 3D4h AMCAM 8 Prefetchable Memory Upper Limit Address 3D8h AMCAM 9 Memory Base and Limit. 3DCh AMCAM 9 Prefetchable Memory Base and Limit 3E0h AMCAM 9 Prefetchable Memory Upper Base Address. 3E4h AMCAM 9 Prefetchable Memory Upper Limit Address 3E8h AMCAM 10 Memory Base and Limit 3ECh AMCAM 10 Prefetchable Memory Base and Limit 3F0h AMCAM 10 Prefetchable Memory Upper Base Address. 3F4h AMCAM 10 Prefetchable Memory Upper Limit Address

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xvii

Registers

PLX Technology, Inc.
408h AMCAM 12 Memory Base and Limit 301 40Ch AMCAM 12 Prefetchable Memory Base and Limit. 301 410h AMCAM 12 Prefetchable Memory Upper Base Address 301 414h AMCAM 12 Prefetchable Memory Upper Limit Address. 301 418h AMCAM 13 Memory Base and Limit 302 41Ch AMCAM 13 Prefetchable Memory Base and Limit. 302 420h AMCAM 13 Prefetchable Memory Upper Base Address 302 424h AMCAM 13 Prefetchable Memory Upper Limit Address. 302 428h AMCAM 14 Memory Base and Limit 303 42Ch AMCAM 14 Prefetchable Memory Base and Limit. 303 430h AMCAM 14 Prefetchable Memory Upper Base Address 303 434h AMCAM 14 Prefetchable Memory Upper Limit Address. 303

Device-Specific Registers Ingress Control and Port Enable 304 660h Ingress Control 304 664h Ingress Control Shadow 305 668h Ingress Port Enable 306 66Ch Negotiated Link Width for Ports 0, 1, 2 307 670h Negotiated Link Width for Ports 8, 9, 10, 12, 13, 14 308

Device-Specific Registers I/O CAM Base and Limit Upper 16 Bits 310 680h I/OCAM Upper Port 0 311 684h I/OCAM Upper Port 1 311 688h I/OCAM Upper Port 2 311 6A0h I/OCAM Upper Port 8 312 6A4h I/OCAM Upper Port 9 312 6A8h I/OCAM Upper Port 10 312 6B0h I/OCAM Upper Port 12 313 6B4h I/OCAM Upper Port 13 313 6B8h I/OCAM Upper Port 14 313

Device-Specific Registers Base Address Shadow 314 6C0h BAR0 Shadow for Port 0 315 6C4h BAR1 Shadow for Port 0 315 6C8h BAR0 Shadow for Port 1 316 6CCh BAR1 Shadow for Port 1 316 6D0h BAR0 Shadow for Port 2 317 6D4h BAR1 Shadow for Port 2 317 700h BAR0 Shadow for Port 318 704h BAR1 Shadow for Port 318 708h BAR0 Shadow for Port 319 70Ch BAR1 Shadow for Port 9 319 710h BAR0 Shadow for Port 320 714h BAR1 Shadow for Port 320 720h BAR0 Shadow for Port 321 724h BAR1 Shadow for Port 321 728h BAR0 Shadow for Port 322 72Ch BAR1 Shadow for Port 13 322 730h BAR0 Shadow for Port 323 734h BAR1 Shadow for Port 323

Device-Specific Registers Shadow Virtual Channel Capability. 324 740h VC0 Port 0 Capability 325 748h VC0 Port 1 Capability 325 750h VC0 Port 2 Capability 325 780h VC0 Port 8 Capability 326 788h VC0 Port 9 Capability 326 790h VC0 Port 10 Capability 326

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The PEX 8548 groups 16 SerDes together into a station, which can be comprised of one to three ports. Refer to Table The station forwards ingress packets to the internal fabric and central RAM, and the station pulls egress packets from the central RAM to send out of the PEX Each station implements the PCI Express PHY Layer and Data Link Layer DLL functions for each of its ports, and aggregates traffic from these ports onto a transaction-based, non-blocking internal fabric. The PCI Express station also performs many Transaction Layer functions, while the packet queuing and ordering aspects of this layer are handled by the Crossbar Switch Control blocks. During system initialization, software initiates Configuration requests that set up the PCI Express interfaces, Device Numbers, and Address maps across the various ports. These maps are used to direct traffic between ports during standard system operation. Traffic flow between different ports of the same station, or ports on different stations, is supported through the central internal fabric.

Functional Blocks

At the top level, each station has a layered organization consisting of the Physical PHY , Data Link Layer DLL , and Transaction Layer Control TLC blocks, as illustrated in Figure The PHY and DLL blocks have port-specific data paths one per PCI Express port that operate independently of one another. The TLC ingress aggregates traffic for all ingress ports in the station, then sends the traffic to the internal fabric. The TLC egress accepts packets, by way of the internal fabric, from all ingress ports, and schedules them to be sent out the appropriate egress port.

Figure PCI Express Station Block Diagram

Non-Blocking Crossbar Switch Fabric

Transaction Layer Control

TLC Ingress

TLC Egress

Ingress Credit Unit

CSR Handling

Egress Credit Unit

DLL Ingress 0-2

Data Link Layer

DLL Egress 0-2

Port Enum. Logic

Physical Layer Port Receive Logic

Link Receive and Transmit Logic
16 Serial Lanes

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Functional Overview

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Physical Layer

For details, refer to Section “Physical Layer.”

Data Link Layer

The Data Link Layer DLL serves as an intermediate stage between the Transaction Layer and the Physical Layer. The primary responsibility of the Data Link Layer includes link management and data integrity, including error detection and correction.

The transmission side of the Data Link Layer accepts Transaction Layer Packets TLPs assembled by the Transaction Layer, calculates and applies data protection code and TLP Sequence Number, and submits them to the Physical Layer for transmission across the link.

The receiving Data Link Layer is responsible for checking the integrity of received TLPs and submitting them to the Transaction Layer for further processing. On detection of TLP error s , this Layer is responsible for requesting re-transmission of TLPs until the information is correctly received, or the link is determined to have failed.

For further details, refer to Section “Data Link Layer.”

Transaction Layer Control

The upper layer of the architecture is the Transaction Layer TL . The TL’s primary responsibility is the assembly and disassembly of TLPs. TLPs are used to communicate transactions, such as Read and Write, as well as certain types of events. The Transaction Layer is also responsible for managing credit-based flow control for TLPs.
Every Request packet requiring a Response packet is implemented as a Split Transaction. Each packet has a unique identifier that enables Response packets to be directed to the correct originator. The packet format supports different forms of addressing, depending upon the transaction type Memory, I/O, Configuration, and Message. The packets can also have attributes, such as No Snoop and Relaxed Ordering.

The TL supports four Address spaces it includes the three PCI Address spaces Memory, I/O, and Configuration and adds a Message space. This specification uses Message space to support all prior sideband signals, such as interrupts, Power Management requests, and so forth, as in-band Message transactions. PCI Express Message transactions can be thought of as virtual wires, because their effect is to eliminate the wide array of sideband signals currently used in a platform implementation.

The PEX 8548 does not support Locked transactions. This is consistent with limitations for Locked transaction use, as outlined in the PCI r3.0 Appendix F, “Exclusive Accesses” , and prevents potential deadlock, as well as serious performance degradation, that could occur with Locked transaction use. The PEX 8548 responds to “lock”-type Read Requests MRdLk with a Completion, having a Completion with status of Unsupported Request UR .

For further details, refer to Section “Transaction Layer.”

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Cut-Thru Mode

Non-Blocking Crossbar Switch Architecture

The Non-Blocking Crossbar switch is an on-chip interconnect switching fabric. The Crossbar Switch architecture is built upon the existing PLX Switch Fabric Architecture technology. In addition to addressing simultaneous multiple flows, the Crossbar Switch architecture incorporates functions required to support an efficient PCI Express switch fabric, including:
• Deadlock avoidance
• Priority preemption
• PCI Express Ordering rules
• Packet fair queuing
• Oldest first scheduling

The Crossbar Switch interconnect physical topology is that of a packet-based Crossbar Switch fabric internal fabric designed to simultaneously connect multiple on-chip stations. The Crossbar Switch protocol is sufficiently flexible and robust to support a variety of embedded system requirements. The protocol is specifically designed to ease chip integration by strongly enforcing station boundaries and standardizing communication between stations. The Crossbar Switch architecture basic features include:
• Multiple concurrent Data transfers
• Global ordering within the switch
• Three types of transactions Posted, Non-Posted, and Completion P, NP, and Cpl, respectively
meet PCI and PCI Express Ordering and Deadlock Avoidance rules
• Optional weighting of source ports to support Source Port arbitration

Cut-Thru Mode

The PEX 8548 is designed to cut through TLPs to and from every port. By default, all ports are enabled for Cut-Thru. Cut-Thru mode can reduce latency, especially for longer packets, because the entire packet does not need to be stored before being forwarded. Instead, after the header is decoded, the packet can be immediately forwarded. Cut-Thru mode can be disabled for all ports by clearing the Debug Control register Cut-Thru Enable bit Port 0, offset 1DCh[21] .

Note The Debug Control register Cut-Thru Enable bit affects the entire chip. If Cut-Thru is enabled, all ports use Cut-Thru. If Cut-Thru is not enabled, no ports use Cut-Thru.

Caution:

One of the drawbacks to using Cut-Thru mode is that the TLP is not known to be good until the last byte. If the TLP proves to be bad, the Cut-Thru packet must be discarded. If the TLP has already been forwarded to another device, that TLP will be framed with an EDB End Data Bad , as opposed to the standard END.

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Functional Overview

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Chapter 5 Reset and Initialization

Reset Overview

Reset is a mechanism that returns a device to its initial state. Hardware or software mechanisms can trigger a reset. The re-initialized states following a reset vary, depending upon the reset type and condition. The PCI Express Base r1.1, Section defines the hardware mechanism as Fundamental Reset. Two actions can trigger a Fundamental Reset:
• Cold Reset
• Warm Reset

There is also a type of reset triggered by an in-band signal from an upstream PCI Express link to all its downstream ports, which is called a Hot Reset. There is also a Secondary Bus Reset. Any PCI-to-PCI bridge can reset its downstream hierarchy by setting the Bridge Control register Secondary Bus Reset bit offset 3Ch[22]=1 . Upon exit from a Cold or Warm Reset, all port configurations, port registers, and state machines are set to initial start-up values, as specified in Section “Initialization Procedure.”

Cold Reset

A Cold Reset is a Fundamental Reset that occurs following a proper PEX 8548 power-on. When the PEX_PERST# signal is held Low following the proper application of power to the component, a Fundamental Reset occurs. A Fundamental Reset initializes the entire PEX 8548 device such as configuration information, clocks, state machines, registers, and so forth . When power is removed from the device, or travels outside required ranges, all settings and configuration information is lost. The device must cycle through the entire Initialization Procedure after power is accurately re-applied.

Warm Reset

The Fundamental Reset mechanism can also be triggered by driving the PEX 8548 hardware Reset signal PEX_PERST# Low, without the removal and re-application recycling of power. This is considered a Warm Reset. PEX_PERST# can be controlled by on-board toggle switches or other external hardware resets to the device. The PEX 8548 must cycle through the entire Initialization Procedure after the PEX_PERST# Input signal is returned to High.

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Reset and Initialization

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Hot Reset

A Hot Reset is equivalent to a traditional Software Reset. Triggered by an in-band signal from an upstream PCI Express link to all downstream ports, a Hot Reset causes all ports that are downstream from the initiating port to set their registers and state machines to initial values. This type of reset does not require power cycling, nor does it cause PEX 8548 port re-configuration. However, a Hot Reset:
• Causes all TLPs held in the PEX 8548 to be dropped
• Returns all State machines to their initial default values
• Returns all Non-Sticky register bits to their initial default conditions refer to Table 13-4,
“Register Types, Grouped by User Accessibility,” for further details regarding Sticky register bit types

A Hot Reset is triggered by the following actions
• Physical Layer at the upstream port receives a reset through a training sequence leading to a Hot Reset
• Upstream PCI Express port enters the DL_Inactive state, which has the same effect as a Hot Reset

Note In the following sections, the terms “virtual PCI-to-PCI bridge” and “port” refer to a given Station port.

Hot Reset Propagation

A Hot Reset is propagated to a downstream PCI Express device through the PCI Express link, using the Physical Layer Hot Reset mechanism that is, a Reset bit in the Training Ordered-Set from the upstream device is set . PCI Express views a switch as a hierarchy of virtual PCI-to-PCI bridges. An example of reset propagation across the PEX 8548 switch is illustrated in Figure Upon receiving a Hot Reset from the upstream PCI Express link, the virtual primary PCI-to-PCI bridge propagates the reset to virtual secondary PCI-to-PCI bridges for the ports in all stations. Each virtual secondary PCI-to-PCI bridge propagates the reset to its downstream links, and initializes its internal states to initial/default conditions. A Hot Reset does not impact Clock Logic, Port Configuration, nor Sticky register bits.

Figure PEX 8548 System Reset Propagation Example

Upstream Port

Upstream P-P Bridge

Downstream P-P Bridges Downstream

Ports

Reset Propagation

Station 0
Ordering

Virtual Channel Management

Flow Control

VC0 Transmit

Buffer

Link Packet Sequence TLP LCRC

DeMUX

Data Link Layer

DLLP Type Data CRC

DLLP Type Data CRC

LCRC Seq. Num TLP

Check

Link Packet

Sequence TLP LCRC

TLP Replay Buffers MUX

Physical Packet

Physical Layer

Physical Packet

Start

Link Packet

Start

Link Packet

Link Training

Decode Serial-to-Parallel

Encode Parallel-to-Serial

Link Receive and Transmit Logic
16 Serial Lanes

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Device Layers

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Physical Layer

The Physical Layer PHY is responsible for converting information received from the DLL into an appropriate serialized format and transmitting it across the PCI Express link. The PHY also receives the serialized input from the SerDes, converts it to parallel data internal Data Bus , then writes it to the TLC Ingress buffer. The Physical Layer includes all circuitry for PCI Express Link interface operation, including:
• Driver and input buffers
• Parallel-to-serial and serial-to-parallel conversion
• PLLs and clock circuitry
• Impedance matching circuitry
• Interface initialization and maintenance functions

The PHY module interfaces to the PCI Express lanes and implements the PHY Layer functions. The number of ports per station can vary from one to three, with a cumulative lane bandwidth of x16 on each station. PHY functions include:
the programmed MPS
• Checks and removes DLLP and TLP LCRC
• Link state Power Management Supports L0, L0s, L1, L2/L3 Ready, and L3
• Supports cross-linked upstream port and downstream ports
• Sequential packets are transmitted on consecutive lanes

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PHY Status and Command Registers

PHY Status and Command Registers
• Decoding and checking rules for the incoming TLP
• Memory-Mapped CSR access
• Checking incoming packets for malformed or unsupported packets
• Data Poisoning and end-to-end data integrity detection
• ECRC checking of incoming packets
• Error logging and reporting for incoming packets
• TLP packet dispatching
• Write control to the packet RAM and packet link list RAM
• Destination lookup and TC-VC mapping
• Shadow CSR registers for AMCAM/BusNoCAM/TC-VC mapping
• Message Signaled Interrupt or INTx generation
• Credit-based scheduling
• Pipelined full Split Transaction protocol
• PCI/PCI-X-compatible ordering
• Interrupt handling INTx or Message Signal Interrupt
• Power Management support
• Hot Plug and PCI Express Hot Plug support
• Link State event support
• QoS support
• Ordering
• Ingress and Egress credit management

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Device Layers

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The hardware functions provided by the PEX 8548 to implement PCI Express Base r1.1 TL requirements are illustrated in Figure The blocks provide a combination of Ingress and Egress control, as well as the data management at each stage in the flow sequence.

Figure TL Controller

To Another Port From Another Port

TLP Ingress Control

TLP Egress Control

AMCAM BusNoCAM

CSRs

Transaction Layer Packet Decode and Processing

Egress Credit Unit

Link Packet Ingress

TLP Egress

Update Flow Credit Advertise

Control

DLL Interface

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Virtual Channel and Traffic Classes

Virtual Channel and Traffic Classes

The PEX 8548 supports one Virtual Channel VC0 and eight Traffic Classes TC[7:0] . VC0 and TC0 are required by the PCI Express Base r1.1, and configured at device start-up.

TL Transmit/Egress Protocol
The egress side TL receives TLP information from the internal fabric and makes a decision, based upon credit and ordering, regarding which TLP to send next from an Egress port. The PEX 8548 implements the PCI Express Base r1.1-specified Flow Control FC protocol, which ensures that it does not transmit a TLP over a link to a remote receiver unless the receiving device contains sufficient Buffer space to accommodate the packet. This flow control is automatically managed by the hardware and is transparent to software. Software is used only to enable additional buffers, to supplement the initial default buffer assignment.

Headers

The Headers contain three or four DWords that can include the following
• Address/Routing 32 or 64 bits
• TLP Type
• Transfer Size Write requests = Total outgoing DWords Read requests = Requested DWords from Completer
• Requester ID or Completer ID
• Tag Used to identify a completion TLP
• Traffic Class
• Byte Enables
• Completion status
• Digest One bit indicating ECRC presence
• Attributes

Data Payloads

The Data Payloads are variable length with a maximum of 1,024 bytes, as defined by the Maximum Payload Size field available sizes are 128, 256, 512, and 1,024, depending upon the number of ports used . Read requests do not include a Data Payload.

Note Refer to the Device Control register Maximum Payload Size field offset 70h[7:5] for Maximum Payload Size port limitations.

End-to-End Cyclic Redundancy Check

End-to-end Cyclic Redundancy Check ECRC is an optional 32-bit field appended to the end of the outgoing packet. ECRC is calculated over the entire packet, starting with the Header and including the Data Payload, except for the EP bit and bit 0 of the Type field, which are always considered to be a value of 1 for ECRC calculations. The ECRC field is transmitted, unchanged, as it moves through the fabric to the completer device. The PEX 8548 checks the ECRC on all incoming TLPs if enabled, and can optionally report detected errors. [When the ECRC is detected, the Uncorrectable Error Status register ECRC Error Status bit offset FB8h[19] can be used to log ECRC errors.] Additionally, the PEX 8548 can optionally append ECRC to the end of internally generated TLPs, such as Interrupt and Error messages, if enabled.

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Device Layers

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TL Receive/Ingress Protocol

The ingress side TL collects and stores inbound TLP traffic in the packet RAM. The incoming data is checked for ECRC errors, valid type field, length matching the Header Transfer Size field, and other TLP-specific errors defined by the PCI Express Base r1.1.

Header and Data Payload information is forwarded to the Source Scheduler, to be routed across the internal fabric, to the Egress port. When CRC errors are detected, the packet is discarded.

Flow Control Protocol

The PEX 8548 implements Flow Control FC protocol that ensures it does not transmit a TLP over a link to a remote Receiver, unless the receiving device has sufficient VC Buffer space to accommodate the packet. This FC is automatically managed by the hardware and is transparent to software. Software is used only to enable additional buffers, to supplement the initial default buffer assignment.

The initial default FC DLLP buffers, which are enabled after link training, allow TLP traffic immediately following the link training. The Configuration transactions are the first transactions to use the default VC buffers to set up the initial device operating modes and capabilities.

The TL Egress Credit Unit transmits DLL packets, called FC packets, that update the FC to the transmitter device on a periodic basis. The updated DLLPs contain FC credit information that updates the transmitter regarding the amount of available buffer space in the receiver VC buffer. The transmitter tracks this information and transmits TLPs only when it perceives that the remote receiver contains sufficient Buffer space to accept the transmitted TLPs.

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Chapter 10 Serial EEPROM Controller

Overview

The PEX 8548 provides an interface to SPI Serial Peripheral Interface -compatible serial EEPROMs. This interface consists of a Chip Select, Clock, Write Data, and Read Data balls, and operates at a programmable frequency of up to MHz. The PEX 8548 supports up to a 16-MB serial EEPROM, utilizing 1-, 2-, or 3-byte addressing. The PEX 8548 automatically determines the appropriate addressing mode.

The primary function of the Serial EEPROM Controller is to allow access to non-volatile memory from the PEX This is accomplished using two different methods:
• The first method of access to a serial EEPROM device is during initialization. When a serial EEPROM device is connected to the PEX 8548, during initialization, the Serial EEPROM Controller reads data from the serial EEPROM to be used to update the default values of registers within the PEX
• The second method of access is controlled by software initiating a Read or Write Request to the serial EEPROM, to store or retrieve other data.

The on-chip Serial EEPROM Controller is integrated into the PEX 8548, as illustrated in Figure The controller performs a serial EEPROM download when the following conditions exist:
• Serial EEPROM is present, and
• Validation signature first byte read from the serial EEPROM value is 5Ah, and
• One of the following events occur:

PEX_PERST# is returned High, following a Fundamental Reset such as, a Cold or Warm Reset

Hot Reset is received at the upstream port [downloading upon this event can be optionally disabled, by setting the Debug Control register Disable Serial EEPROM Load on Hot Reset bit Port 0, offset 1DCh[17]=1 ]

Upstream port exits a DL_Down state [downloading upon this event can be optionally disabled, by setting the Debug Control register Upstream Port DL_Down Reset Propagation Disable bit Port 0, offset 1DCh[20]=1 ]

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Serial EEPROM Controller

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Initialization Serial

EEPROM

EE_CS# EE_DI EE_DO
PCI Express Relaxed Ordering Enable 4 Not supported

Cleared to

Maximum Payload Size

Software can change this field to configure the PEX 8548 ports to support other Payload Sizes however, software cannot change this field to a value larger than that indicated by the Device Capability register Maximum Payload Size Supported field offset 6Ch[2:0] .

Maximum Payload Size port limitations are as follows:
• 1,024 if the number of ports is < 3
• 512 if the number of ports is < 5
• 256 if the number of ports is < 9
000b = Indicates that initially, the PEX 8548 port is configured to support a Maximum Payload Size of 128 bytes
001b = Indicates that initially, the PEX 8548 port is configured to support a Maximum Payload Size of 256 bytes
010b = Indicates that initially, the PEX 8548 port is configured to support a Maximum Payload Size of 512 bytes
011b = Indicates that initially, the PEX 8548 port is configured to support a Maximum Payload Size of 1,024 bytes

Type RW RsvdP

Serial EEPROM and I2C

Default
000b

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Port Registers

Register 70h Device Status and Control All Ports Cont.

Bit s
8 9 10 11 14:12 15

Extended Tag Field Enable Not supported Cleared to

Phantom Functions Enable Not supported Cleared to

AUX Power PM Enable Not supported Cleared to

Enable No Snoop Not supported Cleared to

Maximum Read Request Size Not supported Cleared to 000b.

Reserved Hardwired to 0, as required by the PCI Express Base r1.1.

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Type

Serial EEPROM and I2C

Default

RsvdP

RsvdP

RsvdP

RsvdP

RsvdP

RsvdP
000b 0

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Product Ordering Information
Contact your local PLX Sales Representative for ordering information.
Table A-1. PEX 8548 Product Ordering Information

Part Numbers

PEX8548-AA25BI

PEX 8548-AA 48-Lane, 9-port PCI Express Gen 1 Switch Plastic BGA-H3 x mm2, 736-ball Package

PEX8548-AA25BI G

PEX 8548-AA 48-Lane, 9-port PCI Express Gen 1 Switch Plastic BGA-H3 x mm2, 736-ball , Lead-Free RoHS Green Package

PEX8548-AA25B I G

PEX 8548-AA RDK Breakout Board-88 Breakout Board-844
x1 Adapter x4 Adapter x8 Adapter

G Lead-Free, RoHS-Compliant, Fully Green

I Industrial Temperature

B Ball Grid Array Package
8548 Part Number PEX PCI Express Product Family PEX 8548-AA Rapid Development Kit with x16 Edge Connector Breakout Board with x16 Edge Connector for Additional Fan-Out to Two Slots x8, x8 Breakout Board with x16 Edge Connector for Additional Fan-Out to Three Slots x8, x4, x4 PCI Express x16 to x1 Adapter PCI Express x16 to x4 Adapter PCI Express x16 to x8 Adapter

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General Information

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A.2 A.3

United States and International Representatives and Distributors

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Technical Support

PLX Technology, Inc., technical support information is listed at or call 800 759-3735 domestic only or 408

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PEX8548-AA25BI Datasheet file may be downloaded here without warranties.

Datasheet ID: PEX8548-AA25BI 520501