PEX8505-AA25BI

PEX8505-AA25BI Datasheet

ExpressLane PEX 8505-AA

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PEX8505-AA25BI	PEX8505-AA25BI (pdf)

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ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book Version April 2009 Website Technical Support Phone 800 759-3735 408 774-9060 FAX 408 774-2169 Copyright 2009 by PLX Technology, Inc. All Rights Reserved Version April, 2009 PLX Technology, Inc. Version Date November, 2007 April, 2009 Description of Changes Copyright Information Copyright 2007 2009 PLX Technology, Inc. All Rights Reserved. The information in this document is proprietary and confidential to PLX Technology. No part of this document may be reproduced in any form or by any means or used to make any derivative work such as translation, transformation, or adaptation without written permission from PLX Technology. PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, such information is preliminary, and no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product s and/or the program s described in this documentation at any time. PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology products. PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX Technology, Inc. PCI Express is a trademark of the PCI Special Interest Group PCI-SIG . EUI-64 is a trademark of The Institute of Electrical and Electronics Engineers, Inc. IEEE All product names are trademarks, registered trademarks, or service marks of their respective owners. Document Number 8505-AA-SIL-DB-P1-1.1 ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved April, 2009 Audience The information in this data book is subject to change without notice. This PLX data book to be updated periodically as new information is made available. This data book provides functional details of PLX Technology’s ExpressLane PEX 8505-AA 5-Lane/ 5-Port PCI Express Gen 1 Switch, for hardware designers and software/firmware engineers. Supplemental Documentation This data book assumes that the reader is familiar with the following documents: • PLX Technology, Inc. PLX 870 W Maude Avenue, Sunnyvale, CA 94085 USA Tel 800 759-3735 domestic only or 408 774-9060, Fax 408 774-2169, The PLX PEX 8505 Toolbox includes this data book, as well as other PEX 8505 documentation, including the Errata. • The Institute of Electrical and Electronics Engineers, Inc. IEEE 445 Hoes Lane, Piscataway, NJ 08854-4141 USA Tel 800 701-4333 domestic only or 732 981-0060, Fax 732 981-9667, IEEE Standard IEEE Standard Test Access Port and Boundary-Scan Architecture, 1990 IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Standard Specifications for Vendor-Specific Extensions IEEE Standard IEEE Standard Test Access Port and Boundary-Scan Architecture Extensions • NXP Semiconductors The I2C-Bus Specification, Version ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Terms and Abbreviations PLX Technology, Inc. Note In this data book, shortened titles are associated with the previously listed documents. The following table lists these abbreviations. Abbreviation Document PCI r3.0 PCI Power Mgmt. r1.2 A.1 Product Ordering Information 333 A.2 United States and International Representatives and Distributors 334 A.3 Technical Support 334 ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Contents PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Registers Power Management Capability Registers 152 40h Power Management Capability 44h Power Management Status and Control Message Signaled Interrupt Capability Registers 155 48h MSI Control and Capability Header 4Ch MSI Address 50h MSI Upper Address 54h MSI Data 58h MSI Mask. 5Ch MSI Pending PCI Express Capability Registers 157 68h PCI Express Capability List and Capability 6Ch Device Capability 70h Device Status and Control 74h Link Capability 78h Link Status and Control 7Ch Slot Capability 80h Slot Status and Control Subsystem ID and Subsystem Vendor ID Capability Registers. 176 90h Subsystem Capability 94h Subsystem ID and Subsystem Vendor ID Device Serial Number Extended Capability Registers 179 100h Device Serial Number Enhanced Capability 104h Serial Number Lower DW 108h Serial Number Upper DW ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved xiii Registers PLX Technology, Inc. Power Budget Extended Capability Registers 181 138h Power Budget Extended Capability Header 181 13Ch Data Select 181 140h Power Budget Data. 182 144h Power Budget Capability 183 Virtual Channel Extended Capability Registers. 184 148h Virtual Channel Extended Capability 184 14Ch Port VC Capability 185 154h Port VC Status and Control 185 158h VC0 Resource Capability 186 15Ch VC0 Resource Control 186 160h VC0 Resource Status 187 Port Arbitration Table Registers 188 1A8h Port Arbitration Table Phases 0 to 189 1ACh Port Arbitration Table Phases 8 to 15 190 1B0h Port Arbitration Table Phases 16 to 191 1B4h Port Arbitration Table Phases 24 to 192 Device-Specific Registers 193 Device-Specific Registers Error Checking and Debug 195 1C0h Device-Specific Error Status for Egress ECC Error 196 1C4h Device-Specific Error Mask for Egress ECC Error 197 1C8h ECC Error Check Disable 198 1CCh Error Handler 32-Bit Error Status 199 1D0h Error Handler 32-Bit Error Mask 201 1DCh Debug Control 203 1E0h Power Management Hot Plug User Configuration 205 1E8h Bad TLP Count. 206 1ECh Bad DLLP Count 206 1F4h Lane Status/Software PEX_LANE_GOODx# LED Control 207 1F8h ACK Transmission Latency Limit 208 Device-Specific Registers Physical Layer. 209 204h Physical Layer Receiver Not Detected and Electrical Idle Detect Masks 211 210h Physical Layer User Test Pattern 212 214h Physical Layer User Test Pattern 212 218h Physical Layer User Test Pattern 212 21Ch Physical Layer User Test Pattern 12 212 220h Physical Layer Command and Status. 213 224h Port Configuration. 214 228h Physical Layer Test 215 22Ch Physical Layer 217 230h Physical Layer Port Command 219 234h SKIP Ordered-Set Interval and Port Control. 224 238h SerDes Quad 0 Diagnostic Data 225 23Ch SerDes Quad 1 Diagnostic Data 226 248h SerDes Nominal Drive Current Select 226 24Ch SerDes Drive Current Level 1 227 254h SerDes Drive Equalization Level Select 1 227 260h Serial EEPROM Status and Control 228 264h Serial EEPROM Data Buffer. 231 268h Serial EEPROM Clock Frequency 231 26Ch Serial EEPROM 3rd Address Byte 231 Device-Specific Registers I2C Interface. 232 294h I2C Configuration 232 ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved April, 2009 Registers Device-Specific Registers Bus Number CAM 233 2C8h Bus Number CAM 0 2CCh Bus Number CAM 1 2D0h Bus Number CAM 2 2D4h Bus Number CAM 3 2D8h Bus Number CAM 4 Device-Specific Registers I/O CAM 236 308h I/O CAM 0 30Ah I/O CAM 1 30Ch I/O CAM 2 30Eh I/O CAM 3 310h I/O CAM 4 Device-Specific Registers Address-Mapping CAM 239 348h AMCAM 0 Memory Base and Limit 34Ch AMCAM 0 Prefetchable Memory Base and Limit 350h AMCAM 0 Prefetchable Memory Upper Base Address 354h AMCAM 0 Prefetchable Memory Upper Limit Address 358h AMCAM 1 Memory Base and Limit 35Ch AMCAM 1 Prefetchable Memory Base and Limit 360h AMCAM 1 Prefetchable Memory Upper Base Address 364h AMCAM 1 Prefetchable Memory Upper Limit Address 368h AMCAM 2 Memory Base and Limit 36Ch AMCAM 2 Prefetchable Memory Base and Limit 370h AMCAM 2 Prefetchable Memory Upper Base Address 374h AMCAM 2 Prefetchable Memory Upper Limit Address 378h AMCAM 3 Memory Base and Limit 37Ch AMCAM 3 Prefetchable Memory Base and Limit 380h AMCAM 3 Prefetchable Memory Upper Base Address 384h AMCAM 3 Prefetchable Memory Upper Limit Address 388h AMCAM 4 Memory Base and Limit 38Ch AMCAM 4 Prefetchable Memory Base and Limit 390h AMCAM 4 Prefetchable Memory Upper Base Address 394h AMCAM 4 Prefetchable Memory Upper Limit Address Device-Specific Registers Ingress Control and Port Enable. 245 660h Ingress Control 664h Ingress Control Shadow 668h Ingress Port Enable 66Ch Negotiated Link Width for Ports 0, 1, 2, 3, 4 Device-Specific Registers I/O CAM Base and Limit Upper 16 Bits 248 680h I/OCAM Upper Port 684h I/OCAM Upper Port 688h I/OCAM Upper Port 68Ch I/OCAM Upper Port 3 690h I/OCAM Upper Port Device-Specific Registers Base Address Shadow 250 6C0h BAR0 Shadow for Port 0 6C4h BAR1 Shadow for Port 0 6C8h BAR0 Shadow for Port 1 6CCh BAR1 Shadow for Port 1 6D0h BAR0 Shadow for Port 2 6D4h BAR1 Shadow for Port 2 6D8h BAR0 Shadow for Port 3 6DCh BAR1 Shadow for Port 3 6E0h BAR0 Shadow for Port 4 6E4h BAR1 Shadow for Port 4 ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Registers PLX Technology, Inc. Device-Specific Registers Shadow Virtual Channel Capability. 256 740h VC0 Port 0 Capability 257 748h VC0 Port 1 Capability 257 750h VC0 Port 2 Capability 257 758h VC0 Port 3 Capability 258 760h VC0 Port 4 Capability 258 • 5-port PCI Express switch Five lanes with integrated on-chip SerDes Low-power SerDes under 90 mW per lane Fully Non-Blocking Switch architecture Optional Device-Specific Relaxed Ordering Port configuration • Five independent ports • Choice of width number of lanes per unique link/port x1 and x2 • Configurable with serial EEPROM or I2C • Designate any port as the upstream port 0 is recommended Maximum Payload Size 1,024 bytes Dynamic Buffer Pool architecture, for faster credit updates • Quality of Service QoS support All ports support one, full-featured Virtual Channel VC0 All ports support eight Traffic Class TC mapping, independently of the other ports Ingress port arbitration • Reliability, Availability, Serviceability RAS features PCI Express Standard Hot Plug Controller for three ports, including optional usage models for Manually operated Retention Latch, by way of MRL Sensor and Attention Button support Baseline and Advanced Error Reporting capability JTAG boundary scan • INTA# PEX_INTA# and FATAL ERROR FATAL_ERR# Conventional PCI SERR# equivalent ball support • Lane Status balls PEX_LANE_GOOD[4:0]# • Other PCI Express Capabilities Transaction Layer Packet TLP Digest support • Poison bit • End-to-end Cyclic Redundancy Check ECRC and L3 with Vaux not supported Conventional PCI-compatible Device Power Management states D0 and D3hot Active State Power Management ASPM fully supported • Out-of-Band Initialization options Serial EEPROM I2C 7-bit Slave address with 100 Kbps ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Introduction PLX Technology, Inc. • Performance 25 Gbps aggregate bandwidth Gbps/lane x 5 SerDes lanes x 2 full duplex ] Cut-Thru packet latency of 210 ns for a x1 to x1 configuration Non-blocking internal crossbar supporting full wire speed • Testability JTAG support for DC • 15 x 15 mm2, 196-ball, Plastic Ball Grid Array PBGA package • Typical power 0.86W • Compliant to the following specifications: PCI ExpressCard CEM r1.1 IEEE Standard IEEE Standard Test Access Port and Boundary-Scan Architecture, 1990 IEEE Standard IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Standard Specifications for Vendor-Specific Extensions IEEE Standard IEEE Standard Test Access Port and Boundary-Scan Architecture Extensions IEEE Standard The I2C-Bus Specification, Version I2C Bus v2.1 ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved April, 2009 Overview Overview This data book describes PLX Technology’s ExpressLane PEX 8505, a fully non-blocking, low-latency, low-cost, and low-power 5-lane, 5-port PCI Express Gen 1 switch. Conforming to the PCI Express Base r1.1, the PEX 8505 enables users to add scalable, high-bandwidth I/O to a wide variety of products, including servers, communication products, storage systems, and other embedded products. The PEX 8505’s flexible hardware configuration and software programmability allows the switch’s port configurations and QoS operating characteristics to be tailored to suit a wide variety of application requirements. The PEX 8505 is principally aimed at control plane applications, multi-function printers, digital video recorders DVRs , industrial control systems, medical imaging systems, embedded systems, and AMC modules. The PEX 8505 supports multiple port configurations, as illustrated in Figure The PEX 8505 can support x1 and x2 ports, by auto-negotiating its ports to the link width of the end-device to which it is interfacing. Figure PEX 8505 Port Configuration Examples ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Introduction PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Chapter 2 Features and Applications Flexible and Feature-Rich 5-Lane/5-Port Switch Highly Flexible Port Configurations The PLX ExpressLane PEX 8505 PCI Express Switch offers flexibility in the configuration of its ports. A maximum of five ports can be configured to the standard widths of x1 and/or x2, to support specific bandwidth needs. The ports can be symmetric each port has the same lane width or asymmetric ports have different lane widths . Any one port can be designated as the upstream port. High Performance The PEX 8505 architecture supports packet Cut-Thru with a latency of 210 ns x1 to x1 . This, combined with large Packet memory 256 to 1,024-byte Maximum Payload Size , and Non-Blocking Internal Switch architecture, provide full line rate on its ports. End-to-End Packet Integrity The PEX 8505 provides End-to-end CRC ECRC protection and Poison Bit support to enable designs that require guaranteed error-free packets. PLX also supports data path parity and memory RAM error correction as packets pass through the PEX These features are optional in the PCI Express Base r1.1 however, PLX provides them across its entire ExpressLane switch product line. Configuration Flexibility The station implements the PCI Express Physical Layer PHY and Data Link Layer DLL functions for its ports, and aggregates traffic from these ports onto a transaction-based, non-blocking internal fabric. The PCI Express station also performs many Transaction Layer functions, while the packet queuing and ordering aspects of this layer are handled by the Crossbar Switch Control blocks. During system initialization, software initiates Configuration requests that set up the PCI Express interfaces, Device Numbers, and Address maps across the various ports. These maps are used to direct traffic between ports during standard system operation. The PCI Express station can contain multiple ports one upstream and multiple downstream . Traffic flow between the ports is supported through the central internal fabric. Functional Blocks At the top level, the station has a layered organization consisting of the PHY, DLL, and Transaction Layer TL blocks, as illustrated in Figure The PHY and DLL blocks have port-specific data paths one per PCI Express port that operate independently of one another. The Transaction Layer Control TLC ingress section of the TL block aggregates traffic for all ingress ports in the station, then sends the traffic to the internal fabric. The TLC egress section of the TL block accepts packets, by way of the internal fabric, from all ingress ports, and schedules them to be sent out the appropriate egress port. ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Functional Overview Figure PCI Express Station Block Diagram Non-Blocking Crossbar Switch Fabric TLC Ingress Ingress Credit Unit Transaction Layer CSR Handling TLC Egress Egress Credit Unit PLX Technology, Inc. Data Link Layer DLL Ingress 0-4 DLL Egress 0-4 Port Enum. Logic Physical Layer Port Receive Logic Link Receive and Transmit Logic 5 Serial Lanes ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved April, 2009 Functional Blocks Physical Layer For details, refer to Section “Physical Layer.” Data Link Layer The Data Link Layer DLL serves as an intermediate stage between the Transaction Layer and the Physical Layer. The primary responsibility of the Data Link Layer includes link management and data integrity, including error detection and correction. The transmission side of the Data Link Layer accepts Transaction Layer Packets TLPs assembled by the Transaction Layer, calculates and applies data protection code and TLP Sequence Number, and submits them to the Physical Layer for transmission across the link. The receiving Data Link Layer is responsible for checking the integrity of received TLPs and submitting them to the Transaction Layer for further processing. On detection of TLP error s , this Layer is responsible for requesting re-transmission of TLPs until the information is correctly received, or the link is determined to have failed. For further details, refer to Section “Data Link Layer.” Transaction Layer Control The upper layer of the architecture is the Transaction Layer TL . The TL’s primary responsibility is the assembly and disassembly of TLPs. TLPs are used to communicate transactions, such as Read and Write, as well as certain types of events. The Transaction Layer is also responsible for managing credit-based flow control for TLPs. Every Request packet requiring a Response packet is implemented as a Split Transaction. Each packet has a unique identifier that enables Response packets to be directed to the correct originator. The packet format supports different forms of addressing, depending upon the transaction type Memory, I/O, Configuration, and Message. The packets can also have attributes, such as No Snoop and Relaxed Ordering. The TL supports four Address spaces it includes the three PCI Address spaces Memory, I/O, and Configuration and adds a Message space. This specification uses Message space to support all prior sideband signals, such as interrupts, Power Management requests, and so forth, as in-band Message transactions. PCI Express Message transactions can be thought of as virtual wires, because their effect is to eliminate the wide array of sideband signals currently used in a platform implementation. The PEX 8505 does not support Locked transactions. This is consistent with limitations for Locked transaction use, as outlined in the PCI r3.0 Appendix F, “Exclusive Accesses” , and prevents potential deadlock, as well as serious performance degradation, that could occur with Locked transaction use. The PEX 8505 responds to “lock”-type Read Requests MRdLk with a Completion, having a Completion with status of Unsupported Request UR . For further details, refer to Section “Transaction Layer.” ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Functional Overview PLX Technology, Inc. Non-Blocking Crossbar Switch Architecture The Non-Blocking Crossbar switch is an on-chip interconnect switching fabric. The Crossbar Switch architecture is built upon the existing PLX Switch Fabric Architecture technology. In addition to addressing simultaneous multiple flows, the Crossbar Switch architecture incorporates functions required to support an efficient PCI Express switch fabric, including: • Deadlock avoidance • Priority preemption • PCI Express Ordering rules • Packet fair queuing • Oldest first scheduling The Crossbar Switch interconnect physical topology is that of a packet-based Crossbar Switch fabric internal fabric designed to simultaneously connect multiple on-chip stations. The Crossbar Switch protocol is sufficiently flexible and robust to support a variety of embedded system requirements. The protocol is specifically designed to ease chip integration by strongly enforcing station boundaries and standardizing communication between stations. The Crossbar Switch architecture basic features include: • Multiple concurrent Data transfers • Global ordering within the switch • Three types of transactions Posted, Non-Posted, and Completion P, NP, and Cpl, respectively meet PCI and PCI Express Ordering and Deadlock Avoidance rules • Optional weighting of source ports to support Source Port arbitration Note Although the internal fabric is designed to support multiple stations, the PEX 8505 has only one station. Cut-Thru Mode The PEX 8505 is designed to cut through TLPs to and from every port. By default, all ports are enabled for Cut-Thru. Cut-Thru mode can reduce latency, especially for longer packets, because the entire packet does not need to be stored before being forwarded. Instead, after the header is decoded, the packet can be immediately forwarded. Cut-Thru mode can be disabled for all ports by clearing the Debug Control register Cut-Thru Enable bit Port 0, offset 1DCh[21] . Note The Debug Control register Cut-Thru Enable bit affects the entire chip. If Cut-Thru is enabled, all ports use Cut-Thru. If Cut-Thru is not enabled, no ports use Cut-Thru. Caution: One of the drawbacks to using Cut-Thru mode is that the TLP is not known to be good until the last byte. If the TLP proves to be bad, the Cut-Thru packet must be discarded. If the TLP has already been forwarded to another device, that TLP will be framed with an EDB End Data Bad , as opposed to the standard END. ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Chapter 5 Reset and Initialization Reset Overview Reset is a mechanism that returns a device to its initial state. Hardware or software mechanisms can trigger a reset. The re-initialized states following a reset vary, depending upon the reset type and condition. The PCI Express Base r1.1, Section defines the hardware mechanism as Fundamental Reset. Two actions can trigger a Fundamental Reset: • Cold Reset • Warm Reset There is also a type of reset triggered by an in-band signal from an upstream PCI Express link to all its downstream ports, which is called a Hot Reset. There is also a Secondary Bus Reset. Any PCI-to-PCI bridge can reset its downstream hierarchy by setting the Bridge Control register Secondary Bus Reset bit offset 3Ch[22]=1 . Upon exit from a Cold or Warm Reset, all port configurations, port registers, and state machines are set to initial start-up values, as specified in Section “Initialization Procedure.” Cold Reset A Cold Reset is a Fundamental Reset that occurs following a proper PEX 8505 power-on. When the PEX_PERST# signal is held Low following the proper application of power to the component, a Fundamental Reset occurs. A Fundamental Reset initializes the entire PEX 8505 device such as configuration information, clocks, state machines, registers, and so forth . When power is removed from the device, or travels outside required ranges, all settings and configuration information is lost. The device must cycle through the entire Initialization Procedure after power is accurately re-applied. Warm Reset The Fundamental Reset mechanism can also be triggered by driving the PEX 8505 hardware Reset signal PEX_PERST# Low, without the removal and re-application recycling of power. This is considered a Warm Reset. PEX_PERST# can be controlled by on-board toggle switches or other external hardware resets to the device. The PEX 8505 must cycle through the entire Initialization Procedure after the PEX_PERST# Input signal is returned to High. ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Reset and Initialization PLX Technology, Inc. Hot Reset A Hot Reset is equivalent to a traditional Software Reset. Triggered by an in-band signal from an upstream PCI Express link to all downstream ports, a Hot Reset causes all ports that are downstream from the initiating port to set their registers and state machines to initial values. This type of reset does not require power cycling, nor does it cause PEX 8505 port re-configuration. However, a Hot Reset: • Causes all TLPs held in the PEX 8505 to be dropped • Returns all State machines to their initial default values • Returns all Non-Sticky register bits to their initial default conditions refer to Table 13-4, “Register Types, Grouped by User Accessibility,” for further details regarding Sticky register bit types A Hot Reset is triggered by the following actions • Physical Layer at the upstream port receives a reset through a training sequence leading to a Hot Reset • Upstream PCI Express port enters the DL_Inactive state, which has the same effect as a Hot Reset Note In the following sections, the terms “virtual PCI-to-PCI bridge” and “port” refer to a given Station port. Hot Reset Propagation A Hot Reset is propagated to a downstream PCI Express device through the PCI Express link, using the Physical Layer Hot Reset mechanism that is, a Reset bit in the Training Ordered-Set from the upstream device is set . PCI Express views a switch as a hierarchy of virtual PCI-to-PCI bridges. An example of reset propagation across the PEX 8505 switch is illustrated in Figure Upon receiving a Hot Reset from the upstream PCI Express link, the virtual primary PCI-to-PCI bridge propagates the reset to virtual secondary PCI-to-PCI bridges for all ports. Each virtual secondary PCI-to-PCI bridge propagates the reset to its downstream links, and initializes its internal states to initial/default conditions. A Hot Reset does not impact Clock Logic, Port Configuration, nor Sticky register bits. Figure System Reset Propagation Example Upstream Port Upstream P-P Bridge Downstream P-P Bridges Downstream Ports Reset Propagation Internal Virtual PCI Bus Station ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved April, 2009 Ordering Virtual Channel Management Flow Control TLC Egress Control Transaction Layer Packet TLP Header Data Payload ECRC VC0 Transmit Buffer Link Packet Sequence TLP LCRC DeMUX Data Link Layer DLLP Type Data CRC DLLP Type Data CRC LCRC Seq. Num TLP Check Link Packet Sequence TLP LCRC TLP Replay Buffers MUX Physical Packet Physical Layer Physical Packet Start Link Packet Start Link Packet Link Training Decode Serial-to-Parallel Encode Parallel-to-Serial Link Receive and Transmit Logic 5 Serial Lanes ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Device Layers PLX Technology, Inc. Physical Layer The Physical Layer PHY is responsible for converting information received from the DLL into an appropriate serialized format and transmitting it across the PCI Express link. The PHY also receives the serialized input from the SerDes, converts it to parallel data internal Data Bus , then writes it to the TLC Ingress buffer. The Physical Layer includes all circuitry for PCI Express Link interface operation, including: • Driver and input buffers • Parallel-to-serial and serial-to-parallel conversion • PLLs and clock circuitry • Impedance matching circuitry • Interface initialization and maintenance functions The PHY module interfaces to the PCI Express lanes and implements the PHY functions. The number of ports can vary from three to five, with a cumulative lane bandwidth of x5. PHY functions include: the programmed MPS • Checks and removes DLLP and TLP LCRC • Link state Power Management Supports L0, L0s, L1, L2/L3 Ready, and L3 • Supports cross-linked upstream port and downstream ports ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved April, 2009 PHY Status and Command Registers PHY Status and Command Registers • Decoding and checking rules for the incoming TLP • Memory-Mapped CSR access • Checking incoming packets for malformed or unsupported packets • Data Poisoning and end-to-end data integrity detection • ECRC checking of incoming packets • Error logging and reporting for incoming packets • TLP packet dispatching • Write control to the packet RAM and packet link list RAM • Destination lookup and TC-VC mapping • Shadow CSRs for BusNoCAM/IOCAM/AMCAM/TC-VC mapping • Message Signaled Interrupt or INTx generation • Credit-based scheduling • Pipelined full Split Transaction protocol • PCI/PCI-X-compatible ordering • Interrupt handling INTx or Message Signal Interrupt • Power Management support • Hot Plug and PCI Express Hot Plug support • Link State event support • QoS support • Ordering • Ingress and Egress credit management ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved April, 2009 Transaction Layer The hardware functions provided by the PEX 8505 to implement PCI Express Base r1.1 TL requirements are illustrated in Figure The blocks provide a combination of Ingress and Egress control, as well as the data management at each stage in the flow sequence. Figure TL Controller To Another Port From Another Port TLP Ingress Control TLP Egress Control BusNoCAM, IOCAM, and AMCAM CSRs Transaction Layer Packet Decode and Processing Egress Credit Unit Link Packet Ingress TLP Egress Update Flow Credit Advertise Control DLL Interface ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Device Layers PLX Technology, Inc. Virtual Channel and Traffic Classes The PEX 8505 supports one Virtual Channel VC0 and eight Traffic Classes TC[7:0] . VC0 and TC0 are required by the PCI Express Base r1.1, and configured at device start-up. TL Transmit/Egress Protocol The egress side TL receives TLP information from the internal fabric and makes a decision, based upon credit and ordering, regarding which TLP to send next from an Egress port. The PEX 8505 implements the PCI Express Base r1.1-specified Flow Control FC protocol, which ensures that it does not transmit a TLP over a link to a remote receiver unless the receiving device contains sufficient Buffer space to accommodate the packet. This flow control is automatically managed by the hardware and is transparent to software. Software is used only to enable additional buffers, to supplement the initial default buffer assignment. Headers The Headers contain three or four DWords that can include the following • Address/Routing 32 or 64 bits • TLP Type • Transfer Size Write requests = Total outgoing DWords Read requests = Requested DWords from Completer • Requester ID or Completer ID • Tag Used to identify a completion TLP • Traffic Class • Byte Enables • Completion status • Digest One bit indicating ECRC presence • Attributes Data Payloads The Data Payloads are variable length with a maximum of 1,024 bytes, as defined by the Maximum Payload Size field available sizes are 128, 256, 512, and 1,024, depending upon the number of ports used . Read requests do not include a Data Payload. Note Refer to the Device Control register Maximum Payload Size field offset 70h[7:5] for Maximum Payload Size port limitations. End-to-End Cyclic Redundancy Check End-to-end Cyclic Redundancy Check ECRC is an optional 32-bit field appended to the end of the outgoing packet. ECRC is calculated over the entire packet, starting with the Header and including the Data Payload, except for the EP bit and bit 0 of the Type field, which are always considered to be a value of 1 for ECRC calculations. The ECRC field is transmitted, unchanged, as it moves through the fabric to the completer device. The PEX 8505 checks the ECRC on all incoming TLPs if enabled, and can optionally report detected errors. [When the ECRC is detected, the Uncorrectable Error Status register ECRC Error Status bit offset FB8h[19] can be used to log ECRC errors.] Additionally, the PEX 8505 can optionally append ECRC to the end of internally generated TLPs, such as Interrupt and Error messages, if enabled. ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved April, 2009 TL Receive/Ingress Protocol TL Receive/Ingress Protocol The ingress side TL collects and stores inbound TLP traffic in the packet RAM. The incoming data is checked for ECRC errors, valid type field, length matching the Header Transfer Size field, and other TLP-specific errors defined by the PCI Express Base r1.1. Header and Data Payload information is forwarded to the Source Scheduler, to be routed across the internal fabric, to the Egress port. When CRC errors are detected, the packet is discarded. Flow Control Protocol The initial number of VC0 Flow Control FC credits are advertised as programmed in the Threshold registers, for each type of Header and Payload. The FC initial credits received are sent to the Egress buffer. After FC initialization is complete, the FC update credits received are transferred to the Egress buffer. For FC Credit updates, the Ingress buffer sends update requests to the DLL for DLLP for transmission, to increase the number of advertised credits in the PEX ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Device Layers PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Chapter 10 Interrupts Interrupt Support The PEX 8505 supports the PCI Express interrupt model, which uses two mechanisms: • INTx emulation • Message Signaled Interrupt MSI For Conventional PCI compatibility, the PCI INTx emulation mechanism is used to signal interrupts to the System Interrupt Controller. This mechanism is compatible with existing PCI software, provides the same level of service as the corresponding PCI interrupt signaling mechanism, and is independent of System Interrupt Controller specifics. The PCI INTx emulation mechanism virtualizes PCI physical Interrupt signals by using an in-band signaling mechanism. In addition to PCI INTx-compatible interrupt emulation, the PEX 8505 supports the Message Signaled Interrupt MSI mechanism. The PCI Express MSI mechanism is compatible with the MSI Capability defined in the PCI r3.0. The following events are supported for interrupts: • Hot Plug Presence Detect Changed HP_PRSNTx# Input signal Attention Button Pressed Power Fault Detected MRL Sensor Changed Command Completed • PCI Express Hot Plug Presence Detect Changed SerDes Receiver Detect Data Link Layer State Changed • Device-Specific errors Error-Correcting Code ECC error detected in the internal packet RAM Internal Error FIFO overflow The PEX 8505’s external Interrupt ball, PEX_INTA#, indicates the assertion and/or de-assertion of the internally generated INTx signal: • For Hot Plug or Link State triggered INTx events, PEX_INTA# assertion is controlled by the ECC Error Check Disable register Enable PEX_INTA# Ball for Hot Plug or Link State Event bit Port 0, offset 1C8h[4] . When this bit is set, Hot Plug or Link State events trigger PEX_INTA# assertion however, an INTx message is not generated in this case. PEX_INTA# assertion and INTx message generation for Hot Plug or Link State cases are mutually exclusive. • PEX_INTA# assertion is controlled by the ECC Error Check Disable register Enable PEX_INTA# Ball for Device-Specific Error bit Port 0, offset 1C8h[5] . When this bit is set, Device-Specific errors trigger PEX_INTA# assertion however, PEX_INTA# assertion and INTx message generation are mutually exclusive. ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Interrupts PLX Technology, Inc. PCI Express Relaxed Ordering Enable 4 Not supported Cleared to Maximum Payload Size Software can change this field to configure the PEX 8505 ports to support other Payload Sizes however, software cannot change this field to a value larger than that indicated by the Device Capability register Maximum Payload Size Supported field offset 6Ch[2:0] . Maximum Payload Size port limitations are as follows: • 1,024 if the number of ports is < 3 • 512 if the number of ports is < 5 7:5 000b = Indicates that the PEX 8505 port is configured to support a Maximum Payload Size of 128 bytes 001b = Indicates that the PEX 8505 port is configured to support a Maximum Payload Size of 256 bytes 010b = Indicates that the PEX 8505 port is configured to support a Maximum Payload Size of 512 bytes 011b = Indicates that the PEX 8505 port is configured to support a Maximum Payload Size of 1,024 bytes Type RW RsvdP Serial EEPROM and I2C Default 000b ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved April, 2009 Register 70h Device Status and Control All Ports Cont. Bit s 8 9 10 11 14:12 15 Extended Tag Field Enable Not supported Cleared to Phantom Functions Enable Not supported Cleared to AUX Power PM Enable Not supported Cleared to Enable No Snoop Not supported Cleared to Maximum Read Request Size Not supported Cleared to 000b. Reserved Hardwired to 0, as required by the PCI Express Base r1.1. PCI Express Capability Registers Type Serial EEPROM and I2C Default RsvdP RsvdP RsvdP RsvdP RsvdP RsvdP 000b 0 ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved Port Registers Register 70h Device Status and Control All Ports Cont. Bit s 19 20 21 31:22 Device Status Correctable Error Detected Set when the corresponding port detects a Correctable error, regardless of the bit 0 Correctable Error Reporting Enable state. 0 = Corresponding PEX 8505 port did not detect a Correctable error 1 = Corresponding PEX 8505 port detected a Correctable error Non-Fatal Error Detected Set when the corresponding port detects a Non-Fatal error, regardless of the bit 1 Non-Fatal Error Reporting Enable state. Product Ordering Information Contact your local PLX Sales Representative for ordering information. Table A-1. Product Ordering Information Part Numbers PEX8505-AA25BI PEX 8505 5-Lane, 5-port PCI Express Gen 1 Switch Plastic BGA 15 x 15 mm2, 196-ball Leaded Package PEX8505-AA25BI G PEX 8505 5-Lane, 5-port PCI Express Gen 1 Switch Plastic BGA 15 x 15 mm2, 196-ball LeadFree RoHS Green Package PEX8505-AA25B I G PEX 8505-AA RDK Port Expander Kit G Lead-Free, RoHS-Compliant, Fully Green I Industrial Temperature B Ball Grid Array Package 8505 Part Number PEX PCI Express Product Family PEX 8505 Rapid Development Kit with x4 Edge Connector Port Expander, with • Four x1 slots • One x1 PCI Express cable • One x1 PCI Express Host adapter ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved General Information PLX Technology, Inc. A.2 A.3 United States and International Representatives and Distributors PLX Technology, Inc., representatives and distributors are listed at Technical Support PLX Technology, Inc., technical support information is listed at or call 800 759-3735 domestic only or 408 ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version Copyright 2009 by PLX Technology, Inc. All Rights Reserved

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FAX 408 774-2169

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Description of Changes

Copyright Information

Copyright 2007 2009 PLX Technology, Inc. All Rights Reserved. The information in this document is proprietary and confidential to PLX Technology. No part of this document may be reproduced in any form or by any means or used to make any derivative work such as translation, transformation, or adaptation without written permission from PLX Technology.

PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, such information is preliminary, and no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product s and/or the program s described in this documentation at any time.

PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology products.

PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX Technology, Inc.

PCI Express is a trademark of the PCI Special Interest Group PCI-SIG .

EUI-64 is a trademark of The Institute of Electrical and Electronics Engineers, Inc. IEEE

All product names are trademarks, registered trademarks, or service marks of their respective owners.

Document Number 8505-AA-SIL-DB-P1-1.1

ExpressLane PEX 8505-AA 5-Lane/5-Port PCI Express Gen 1 Switch Data Book, Version

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Audience

The information in this data book is subject to change without notice. This PLX data book to be updated periodically as new information is made available.

This data book provides functional details of PLX Technology’s ExpressLane PEX 8505-AA 5-Lane/ 5-Port PCI Express Gen 1 Switch, for hardware designers and software/firmware engineers.

Supplemental Documentation

This data book assumes that the reader is familiar with the following documents:
• PLX Technology, Inc. PLX 870 W Maude Avenue, Sunnyvale, CA 94085 USA Tel 800 759-3735 domestic only or 408 774-9060, Fax 408 774-2169, The PLX PEX 8505 Toolbox includes this data book, as well as other PEX 8505 documentation, including the Errata.
• The Institute of Electrical and Electronics Engineers, Inc. IEEE 445 Hoes Lane, Piscataway, NJ 08854-4141 USA Tel 800 701-4333 domestic only or 732 981-0060, Fax 732 981-9667, IEEE Standard IEEE Standard Test Access Port and Boundary-Scan Architecture, 1990 IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Standard Specifications for Vendor-Specific Extensions IEEE Standard IEEE Standard Test Access Port and Boundary-Scan Architecture Extensions
• NXP Semiconductors The I2C-Bus Specification, Version

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Terms and Abbreviations

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Note In this data book, shortened titles are associated with the previously listed documents. The following table lists these abbreviations.

Abbreviation

Document

PCI r3.0

PCI Power Mgmt. r1.2
A.1 Product Ordering Information 333 A.2 United States and International Representatives and Distributors 334 A.3 Technical Support 334

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Contents

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Registers

Power Management Capability Registers 152 40h Power Management Capability 44h Power Management Status and Control

Message Signaled Interrupt Capability Registers 155 48h MSI Control and Capability Header 4Ch MSI Address 50h MSI Upper Address 54h MSI Data 58h MSI Mask. 5Ch MSI Pending

PCI Express Capability Registers 157 68h PCI Express Capability List and Capability 6Ch Device Capability 70h Device Status and Control 74h Link Capability 78h Link Status and Control 7Ch Slot Capability 80h Slot Status and Control

Subsystem ID and Subsystem Vendor ID Capability Registers. 176 90h Subsystem Capability 94h Subsystem ID and Subsystem Vendor ID

Device Serial Number Extended Capability Registers 179 100h Device Serial Number Enhanced Capability 104h Serial Number Lower DW 108h Serial Number Upper DW

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Registers

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Power Budget Extended Capability Registers 181 138h Power Budget Extended Capability Header 181 13Ch Data Select 181 140h Power Budget Data. 182 144h Power Budget Capability 183

Virtual Channel Extended Capability Registers. 184 148h Virtual Channel Extended Capability 184 14Ch Port VC Capability 185 154h Port VC Status and Control 185 158h VC0 Resource Capability 186 15Ch VC0 Resource Control 186 160h VC0 Resource Status 187

Port Arbitration Table Registers 188 1A8h Port Arbitration Table Phases 0 to 189 1ACh Port Arbitration Table Phases 8 to 15 190 1B0h Port Arbitration Table Phases 16 to 191 1B4h Port Arbitration Table Phases 24 to 192

Device-Specific Registers 193

Device-Specific Registers Error Checking and Debug 195 1C0h Device-Specific Error Status for Egress ECC Error 196 1C4h Device-Specific Error Mask for Egress ECC Error 197 1C8h ECC Error Check Disable 198 1CCh Error Handler 32-Bit Error Status 199 1D0h Error Handler 32-Bit Error Mask 201 1DCh Debug Control 203 1E0h Power Management Hot Plug User Configuration 205 1E8h Bad TLP Count. 206 1ECh Bad DLLP Count 206 1F4h Lane Status/Software PEX_LANE_GOODx# LED Control 207 1F8h ACK Transmission Latency Limit 208

Device-Specific Registers Physical Layer. 209 204h Physical Layer Receiver Not Detected and Electrical Idle Detect Masks 211 210h Physical Layer User Test Pattern 212 214h Physical Layer User Test Pattern 212 218h Physical Layer User Test Pattern 212 21Ch Physical Layer User Test Pattern 12 212 220h Physical Layer Command and Status. 213 224h Port Configuration. 214 228h Physical Layer Test 215 22Ch Physical Layer 217 230h Physical Layer Port Command 219 234h SKIP Ordered-Set Interval and Port Control. 224 238h SerDes Quad 0 Diagnostic Data 225 23Ch SerDes Quad 1 Diagnostic Data 226 248h SerDes Nominal Drive Current Select 226 24Ch SerDes Drive Current Level 1 227 254h SerDes Drive Equalization Level Select 1 227 260h Serial EEPROM Status and Control 228 264h Serial EEPROM Data Buffer. 231 268h Serial EEPROM Clock Frequency 231 26Ch Serial EEPROM 3rd Address Byte 231

Device-Specific Registers I2C Interface. 232 294h I2C Configuration 232

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Registers

Device-Specific Registers Bus Number CAM 233 2C8h Bus Number CAM 0 2CCh Bus Number CAM 1 2D0h Bus Number CAM 2 2D4h Bus Number CAM 3 2D8h Bus Number CAM 4

Device-Specific Registers I/O CAM 236 308h I/O CAM 0 30Ah I/O CAM 1 30Ch I/O CAM 2 30Eh I/O CAM 3 310h I/O CAM 4

Device-Specific Registers Address-Mapping CAM 239 348h AMCAM 0 Memory Base and Limit 34Ch AMCAM 0 Prefetchable Memory Base and Limit 350h AMCAM 0 Prefetchable Memory Upper Base Address 354h AMCAM 0 Prefetchable Memory Upper Limit Address 358h AMCAM 1 Memory Base and Limit 35Ch AMCAM 1 Prefetchable Memory Base and Limit 360h AMCAM 1 Prefetchable Memory Upper Base Address 364h AMCAM 1 Prefetchable Memory Upper Limit Address 368h AMCAM 2 Memory Base and Limit 36Ch AMCAM 2 Prefetchable Memory Base and Limit 370h AMCAM 2 Prefetchable Memory Upper Base Address 374h AMCAM 2 Prefetchable Memory Upper Limit Address 378h AMCAM 3 Memory Base and Limit 37Ch AMCAM 3 Prefetchable Memory Base and Limit 380h AMCAM 3 Prefetchable Memory Upper Base Address 384h AMCAM 3 Prefetchable Memory Upper Limit Address 388h AMCAM 4 Memory Base and Limit 38Ch AMCAM 4 Prefetchable Memory Base and Limit 390h AMCAM 4 Prefetchable Memory Upper Base Address 394h AMCAM 4 Prefetchable Memory Upper Limit Address

Device-Specific Registers Ingress Control and Port Enable. 245 660h Ingress Control 664h Ingress Control Shadow 668h Ingress Port Enable 66Ch Negotiated Link Width for Ports 0, 1, 2, 3, 4

Device-Specific Registers I/O CAM Base and Limit Upper 16 Bits 248 680h I/OCAM Upper Port 684h I/OCAM Upper Port 688h I/OCAM Upper Port 68Ch I/OCAM Upper Port 3 690h I/OCAM Upper Port

Device-Specific Registers Base Address Shadow 250 6C0h BAR0 Shadow for Port 0 6C4h BAR1 Shadow for Port 0 6C8h BAR0 Shadow for Port 1 6CCh BAR1 Shadow for Port 1 6D0h BAR0 Shadow for Port 2 6D4h BAR1 Shadow for Port 2 6D8h BAR0 Shadow for Port 3 6DCh BAR1 Shadow for Port 3 6E0h BAR0 Shadow for Port 4 6E4h BAR1 Shadow for Port 4

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Registers

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Device-Specific Registers Shadow Virtual Channel Capability. 256 740h VC0 Port 0 Capability 257 748h VC0 Port 1 Capability 257 750h VC0 Port 2 Capability 257 758h VC0 Port 3 Capability 258 760h VC0 Port 4 Capability 258
• 5-port PCI Express switch Five lanes with integrated on-chip SerDes Low-power SerDes under 90 mW per lane Fully Non-Blocking Switch architecture Optional Device-Specific Relaxed Ordering Port configuration
• Five independent ports
• Choice of width number of lanes per unique link/port x1 and x2
• Configurable with serial EEPROM or I2C
• Designate any port as the upstream port 0 is recommended Maximum Payload Size 1,024 bytes Dynamic Buffer Pool architecture, for faster credit updates
• Quality of Service QoS support All ports support one, full-featured Virtual Channel VC0 All ports support eight Traffic Class TC mapping, independently of the other ports Ingress port arbitration
• Reliability, Availability, Serviceability RAS features PCI Express Standard Hot Plug Controller for three ports, including optional usage models for Manually operated Retention Latch, by way of MRL Sensor and Attention Button support Baseline and Advanced Error Reporting capability JTAG boundary scan
• INTA# PEX_INTA# and FATAL ERROR FATAL_ERR# Conventional PCI SERR# equivalent ball support
• Lane Status balls PEX_LANE_GOOD[4:0]#
• Other PCI Express Capabilities

Transaction Layer Packet TLP Digest support
• Poison bit
• End-to-end Cyclic Redundancy Check ECRC
and L3 with Vaux not supported Conventional PCI-compatible Device Power Management states D0 and D3hot Active State Power Management ASPM fully supported
• Out-of-Band Initialization options Serial EEPROM I2C 7-bit Slave address with 100 Kbps

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Introduction

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• Performance 25 Gbps aggregate bandwidth Gbps/lane x 5 SerDes lanes x 2 full duplex ] Cut-Thru packet latency of 210 ns for a x1 to x1 configuration Non-blocking internal crossbar supporting full wire speed
• Testability JTAG support for DC
• 15 x 15 mm2, 196-ball, Plastic Ball Grid Array PBGA package
• Typical power 0.86W
• Compliant to the following specifications:

PCI ExpressCard CEM r1.1 IEEE Standard IEEE Standard Test Access Port and Boundary-Scan

Architecture, 1990 IEEE Standard IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan

Architecture IEEE Standard Specifications for Vendor-Specific Extensions IEEE Standard IEEE Standard Test Access Port and Boundary-Scan

Architecture Extensions IEEE Standard The I2C-Bus Specification, Version I2C Bus v2.1

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Overview

Overview

This data book describes PLX Technology’s ExpressLane PEX 8505, a fully non-blocking, low-latency, low-cost, and low-power 5-lane, 5-port PCI Express Gen 1 switch. Conforming to the PCI Express Base r1.1, the PEX 8505 enables users to add scalable, high-bandwidth I/O to a wide variety of products, including servers, communication products, storage systems, and other embedded products. The PEX 8505’s flexible hardware configuration and software programmability allows the switch’s port configurations and QoS operating characteristics to be tailored to suit a wide variety of application requirements.

The PEX 8505 is principally aimed at control plane applications, multi-function printers, digital video recorders DVRs , industrial control systems, medical imaging systems, embedded systems, and AMC modules. The PEX 8505 supports multiple port configurations, as illustrated in Figure The PEX 8505 can support x1 and x2 ports, by auto-negotiating its ports to the link width of the end-device to which it is interfacing.

Figure PEX 8505 Port Configuration Examples

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Introduction

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Chapter 2 Features and Applications

Flexible and Feature-Rich 5-Lane/5-Port Switch

Highly Flexible Port Configurations

The PLX ExpressLane PEX 8505 PCI Express Switch offers flexibility in the configuration of its ports. A maximum of five ports can be configured to the standard widths of x1 and/or x2, to support specific bandwidth needs. The ports can be symmetric each port has the same lane width or asymmetric ports have different lane widths . Any one port can be designated as the upstream port.

High Performance

The PEX 8505 architecture supports packet Cut-Thru with a latency of 210 ns x1 to x1 . This, combined with large Packet memory 256 to 1,024-byte Maximum Payload Size , and Non-Blocking Internal Switch architecture, provide full line rate on its ports.

End-to-End Packet Integrity

The PEX 8505 provides End-to-end CRC ECRC protection and Poison Bit support to enable designs that require guaranteed error-free packets. PLX also supports data path parity and memory RAM error correction as packets pass through the PEX These features are optional in the PCI Express Base r1.1 however, PLX provides them across its entire ExpressLane switch product line.

Configuration Flexibility
The station implements the PCI Express Physical Layer PHY and Data Link Layer DLL functions for its ports, and aggregates traffic from these ports onto a transaction-based, non-blocking internal fabric. The PCI Express station also performs many Transaction Layer functions, while the packet queuing and ordering aspects of this layer are handled by the Crossbar Switch Control blocks.

During system initialization, software initiates Configuration requests that set up the PCI Express interfaces, Device Numbers, and Address maps across the various ports. These maps are used to direct traffic between ports during standard system operation. The PCI Express station can contain multiple ports one upstream and multiple downstream . Traffic flow between the ports is supported through the central internal fabric.

Functional Blocks

At the top level, the station has a layered organization consisting of the PHY, DLL, and Transaction Layer TL blocks, as illustrated in Figure The PHY and DLL blocks have port-specific data paths one per PCI Express port that operate independently of one another. The Transaction Layer Control TLC ingress section of the TL block aggregates traffic for all ingress ports in the station, then sends the traffic to the internal fabric. The TLC egress section of the TL block accepts packets, by way of the internal fabric, from all ingress ports, and schedules them to be sent out the appropriate egress port.

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Functional Overview

Figure PCI Express Station Block Diagram

Non-Blocking Crossbar Switch Fabric

TLC Ingress

Ingress Credit Unit

Transaction Layer

CSR Handling

TLC Egress

Egress Credit Unit

PLX Technology, Inc.

Data Link Layer DLL Ingress 0-4

DLL Egress 0-4

Port Enum. Logic

Physical Layer Port Receive Logic

Link Receive and Transmit Logic
5 Serial Lanes

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Functional Blocks

Physical Layer

For details, refer to Section “Physical Layer.”

Data Link Layer

The Data Link Layer DLL serves as an intermediate stage between the Transaction Layer and the Physical Layer. The primary responsibility of the Data Link Layer includes link management and data integrity, including error detection and correction.

The transmission side of the Data Link Layer accepts Transaction Layer Packets TLPs assembled by the Transaction Layer, calculates and applies data protection code and TLP Sequence Number, and submits them to the Physical Layer for transmission across the link.

The receiving Data Link Layer is responsible for checking the integrity of received TLPs and submitting them to the Transaction Layer for further processing. On detection of TLP error s , this Layer is responsible for requesting re-transmission of TLPs until the information is correctly received, or the link is determined to have failed.

For further details, refer to Section “Data Link Layer.”

Transaction Layer Control

The upper layer of the architecture is the Transaction Layer TL . The TL’s primary responsibility is the assembly and disassembly of TLPs. TLPs are used to communicate transactions, such as Read and Write, as well as certain types of events. The Transaction Layer is also responsible for managing credit-based flow control for TLPs.
Every Request packet requiring a Response packet is implemented as a Split Transaction. Each packet has a unique identifier that enables Response packets to be directed to the correct originator. The packet format supports different forms of addressing, depending upon the transaction type Memory, I/O, Configuration, and Message. The packets can also have attributes, such as No Snoop and Relaxed Ordering.

The TL supports four Address spaces it includes the three PCI Address spaces Memory, I/O, and Configuration and adds a Message space. This specification uses Message space to support all prior sideband signals, such as interrupts, Power Management requests, and so forth, as in-band Message transactions. PCI Express Message transactions can be thought of as virtual wires, because their effect is to eliminate the wide array of sideband signals currently used in a platform implementation.

The PEX 8505 does not support Locked transactions. This is consistent with limitations for Locked transaction use, as outlined in the PCI r3.0 Appendix F, “Exclusive Accesses” , and prevents potential deadlock, as well as serious performance degradation, that could occur with Locked transaction use. The PEX 8505 responds to “lock”-type Read Requests MRdLk with a Completion, having a Completion with status of Unsupported Request UR .

For further details, refer to Section “Transaction Layer.”

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Functional Overview

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Non-Blocking Crossbar Switch Architecture

The Non-Blocking Crossbar switch is an on-chip interconnect switching fabric. The Crossbar Switch architecture is built upon the existing PLX Switch Fabric Architecture technology. In addition to addressing simultaneous multiple flows, the Crossbar Switch architecture incorporates functions required to support an efficient PCI Express switch fabric, including:
• Deadlock avoidance
• Priority preemption
• PCI Express Ordering rules
• Packet fair queuing
• Oldest first scheduling

The Crossbar Switch interconnect physical topology is that of a packet-based Crossbar Switch fabric internal fabric designed to simultaneously connect multiple on-chip stations. The Crossbar Switch protocol is sufficiently flexible and robust to support a variety of embedded system requirements. The protocol is specifically designed to ease chip integration by strongly enforcing station boundaries and standardizing communication between stations. The Crossbar Switch architecture basic features include:
• Multiple concurrent Data transfers
• Global ordering within the switch
• Three types of transactions Posted, Non-Posted, and Completion P, NP, and Cpl, respectively
meet PCI and PCI Express Ordering and Deadlock Avoidance rules
• Optional weighting of source ports to support Source Port arbitration

Note Although the internal fabric is designed to support multiple stations, the PEX 8505 has only one station.

Cut-Thru Mode

The PEX 8505 is designed to cut through TLPs to and from every port. By default, all ports are enabled for Cut-Thru. Cut-Thru mode can reduce latency, especially for longer packets, because the entire packet does not need to be stored before being forwarded. Instead, after the header is decoded, the packet can be immediately forwarded. Cut-Thru mode can be disabled for all ports by clearing the Debug Control register Cut-Thru Enable bit Port 0, offset 1DCh[21] .

Note The Debug Control register Cut-Thru Enable bit affects the entire chip. If Cut-Thru is enabled, all ports use Cut-Thru. If Cut-Thru is not enabled, no ports use Cut-Thru.

Caution:

One of the drawbacks to using Cut-Thru mode is that the TLP is not known to be good until the last byte. If the TLP proves to be bad, the Cut-Thru packet must be discarded. If the TLP has already been forwarded to another device, that TLP will be framed with an EDB End Data Bad , as opposed to the standard END.

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Chapter 5 Reset and Initialization

Reset Overview

Reset is a mechanism that returns a device to its initial state. Hardware or software mechanisms can trigger a reset. The re-initialized states following a reset vary, depending upon the reset type and condition. The PCI Express Base r1.1, Section defines the hardware mechanism as Fundamental Reset. Two actions can trigger a Fundamental Reset:
• Cold Reset
• Warm Reset

There is also a type of reset triggered by an in-band signal from an upstream PCI Express link to all its downstream ports, which is called a Hot Reset. There is also a Secondary Bus Reset. Any PCI-to-PCI bridge can reset its downstream hierarchy by setting the Bridge Control register Secondary Bus Reset bit offset 3Ch[22]=1 . Upon exit from a Cold or Warm Reset, all port configurations, port registers, and state machines are set to initial start-up values, as specified in Section “Initialization Procedure.”

Cold Reset

A Cold Reset is a Fundamental Reset that occurs following a proper PEX 8505 power-on. When the PEX_PERST# signal is held Low following the proper application of power to the component, a Fundamental Reset occurs. A Fundamental Reset initializes the entire PEX 8505 device such as configuration information, clocks, state machines, registers, and so forth . When power is removed from the device, or travels outside required ranges, all settings and configuration information is lost. The device must cycle through the entire Initialization Procedure after power is accurately re-applied.

Warm Reset

The Fundamental Reset mechanism can also be triggered by driving the PEX 8505 hardware Reset signal PEX_PERST# Low, without the removal and re-application recycling of power. This is considered a Warm Reset. PEX_PERST# can be controlled by on-board toggle switches or other external hardware resets to the device. The PEX 8505 must cycle through the entire Initialization Procedure after the PEX_PERST# Input signal is returned to High.

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Reset and Initialization

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Hot Reset

A Hot Reset is equivalent to a traditional Software Reset. Triggered by an in-band signal from an upstream PCI Express link to all downstream ports, a Hot Reset causes all ports that are downstream from the initiating port to set their registers and state machines to initial values. This type of reset does not require power cycling, nor does it cause PEX 8505 port re-configuration. However, a Hot Reset:
• Causes all TLPs held in the PEX 8505 to be dropped
• Returns all State machines to their initial default values
• Returns all Non-Sticky register bits to their initial default conditions refer to Table 13-4,
“Register Types, Grouped by User Accessibility,” for further details regarding Sticky register bit types

A Hot Reset is triggered by the following actions
• Physical Layer at the upstream port receives a reset through a training sequence leading to a Hot Reset
• Upstream PCI Express port enters the DL_Inactive state, which has the same effect as a Hot Reset

Note In the following sections, the terms “virtual PCI-to-PCI bridge” and “port” refer to a given Station port.

Hot Reset Propagation

A Hot Reset is propagated to a downstream PCI Express device through the PCI Express link, using the Physical Layer Hot Reset mechanism that is, a Reset bit in the Training Ordered-Set from the upstream device is set . PCI Express views a switch as a hierarchy of virtual PCI-to-PCI bridges. An example of reset propagation across the PEX 8505 switch is illustrated in Figure Upon receiving a Hot Reset from the upstream PCI Express link, the virtual primary PCI-to-PCI bridge propagates the reset to virtual secondary PCI-to-PCI bridges for all ports. Each virtual secondary PCI-to-PCI bridge propagates the reset to its downstream links, and initializes its internal states to initial/default conditions. A Hot Reset does not impact Clock Logic, Port Configuration, nor Sticky register bits.

Figure System Reset Propagation Example

Upstream Port

Upstream P-P Bridge

Downstream P-P Bridges Downstream

Ports

Reset Propagation

Internal Virtual PCI Bus

Station

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Ordering Virtual Channel

Management Flow Control

TLC Egress Control Transaction Layer Packet TLP Header Data Payload ECRC

VC0 Transmit

Buffer

Link Packet Sequence TLP LCRC

DeMUX

Data Link Layer

DLLP Type Data CRC

DLLP Type Data CRC

LCRC Seq. Num TLP

Check

Link Packet

Sequence TLP LCRC

TLP Replay Buffers MUX

Physical Packet

Physical Layer

Physical Packet

Start

Link Packet

Start

Link Packet

Link Training

Decode Serial-to-Parallel

Encode Parallel-to-Serial

Link Receive and Transmit Logic
5 Serial Lanes

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Device Layers

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Physical Layer

The Physical Layer PHY is responsible for converting information received from the DLL into an appropriate serialized format and transmitting it across the PCI Express link. The PHY also receives the serialized input from the SerDes, converts it to parallel data internal Data Bus , then writes it to the TLC Ingress buffer. The Physical Layer includes all circuitry for PCI Express Link interface operation, including:
• Driver and input buffers
• Parallel-to-serial and serial-to-parallel conversion
• PLLs and clock circuitry
• Impedance matching circuitry
• Interface initialization and maintenance functions

The PHY module interfaces to the PCI Express lanes and implements the PHY functions. The number of ports can vary from three to five, with a cumulative lane bandwidth of x5. PHY functions include:
the programmed MPS
• Checks and removes DLLP and TLP LCRC
• Link state Power Management Supports L0, L0s, L1, L2/L3 Ready, and L3
• Supports cross-linked upstream port and downstream ports

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PHY Status and Command Registers

PHY Status and Command Registers
• Decoding and checking rules for the incoming TLP
• Memory-Mapped CSR access
• Checking incoming packets for malformed or unsupported packets
• Data Poisoning and end-to-end data integrity detection
• ECRC checking of incoming packets
• Error logging and reporting for incoming packets
• TLP packet dispatching
• Write control to the packet RAM and packet link list RAM
• Destination lookup and TC-VC mapping
• Shadow CSRs for BusNoCAM/IOCAM/AMCAM/TC-VC mapping
• Message Signaled Interrupt or INTx generation
• Credit-based scheduling
• Pipelined full Split Transaction protocol
• PCI/PCI-X-compatible ordering
• Interrupt handling INTx or Message Signal Interrupt
• Power Management support
• Hot Plug and PCI Express Hot Plug support
• Link State event support
• QoS support
• Ordering
• Ingress and Egress credit management

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Transaction Layer

The hardware functions provided by the PEX 8505 to implement PCI Express Base r1.1 TL requirements are illustrated in Figure The blocks provide a combination of Ingress and Egress control, as well as the data management at each stage in the flow sequence.

Figure TL Controller

To Another Port From Another Port

TLP Ingress Control

TLP Egress Control

BusNoCAM, IOCAM, and AMCAM CSRs

Transaction Layer Packet Decode and Processing

Egress Credit Unit

Link Packet Ingress

TLP Egress

Update Flow Credit Advertise

Control

DLL Interface

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Device Layers

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Virtual Channel and Traffic Classes

The PEX 8505 supports one Virtual Channel VC0 and eight Traffic Classes TC[7:0] . VC0 and TC0 are required by the PCI Express Base r1.1, and configured at device start-up.

TL Transmit/Egress Protocol
The egress side TL receives TLP information from the internal fabric and makes a decision, based upon credit and ordering, regarding which TLP to send next from an Egress port. The PEX 8505 implements the PCI Express Base r1.1-specified Flow Control FC protocol, which ensures that it does not transmit a TLP over a link to a remote receiver unless the receiving device contains sufficient Buffer space to accommodate the packet. This flow control is automatically managed by the hardware and is transparent to software. Software is used only to enable additional buffers, to supplement the initial default buffer assignment.

Headers

The Headers contain three or four DWords that can include the following
• Address/Routing 32 or 64 bits
• TLP Type
• Transfer Size Write requests = Total outgoing DWords Read requests = Requested DWords from Completer
• Requester ID or Completer ID
• Tag Used to identify a completion TLP
• Traffic Class
• Byte Enables
• Completion status
• Digest One bit indicating ECRC presence
• Attributes

Data Payloads

The Data Payloads are variable length with a maximum of 1,024 bytes, as defined by the Maximum Payload Size field available sizes are 128, 256, 512, and 1,024, depending upon the number of ports used . Read requests do not include a Data Payload.

Note Refer to the Device Control register Maximum Payload Size field offset 70h[7:5] for Maximum Payload Size port limitations.

End-to-End Cyclic Redundancy Check

End-to-end Cyclic Redundancy Check ECRC is an optional 32-bit field appended to the end of the outgoing packet. ECRC is calculated over the entire packet, starting with the Header and including the Data Payload, except for the EP bit and bit 0 of the Type field, which are always considered to be a value of 1 for ECRC calculations. The ECRC field is transmitted, unchanged, as it moves through the fabric to the completer device. The PEX 8505 checks the ECRC on all incoming TLPs if enabled, and can optionally report detected errors. [When the ECRC is detected, the Uncorrectable Error Status register ECRC Error Status bit offset FB8h[19] can be used to log ECRC errors.] Additionally, the PEX 8505 can optionally append ECRC to the end of internally generated TLPs, such as Interrupt and Error messages, if enabled.

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TL Receive/Ingress Protocol

TL Receive/Ingress Protocol

The ingress side TL collects and stores inbound TLP traffic in the packet RAM. The incoming data is checked for ECRC errors, valid type field, length matching the Header Transfer Size field, and other TLP-specific errors defined by the PCI Express Base r1.1.

Header and Data Payload information is forwarded to the Source Scheduler, to be routed across the internal fabric, to the Egress port. When CRC errors are detected, the packet is discarded.

Flow Control Protocol

The initial number of VC0 Flow Control FC credits are advertised as programmed in the Threshold registers, for each type of Header and Payload. The FC initial credits received are sent to the Egress buffer. After FC initialization is complete, the FC update credits received are transferred to the Egress buffer. For FC Credit updates, the Ingress buffer sends update requests to the DLL for DLLP for transmission, to increase the number of advertised credits in the PEX

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Chapter 10 Interrupts

Interrupt Support

The PEX 8505 supports the PCI Express interrupt model, which uses two mechanisms:
• INTx emulation
• Message Signaled Interrupt MSI

For Conventional PCI compatibility, the PCI INTx emulation mechanism is used to signal interrupts to the System Interrupt Controller. This mechanism is compatible with existing PCI software, provides the same level of service as the corresponding PCI interrupt signaling mechanism, and is independent of System Interrupt Controller specifics. The PCI INTx emulation mechanism virtualizes PCI physical Interrupt signals by using an in-band signaling mechanism.

In addition to PCI INTx-compatible interrupt emulation, the PEX 8505 supports the Message Signaled Interrupt MSI mechanism. The PCI Express MSI mechanism is compatible with the MSI Capability defined in the PCI r3.0.

The following events are supported for interrupts:
• Hot Plug Presence Detect Changed HP_PRSNTx# Input signal Attention Button Pressed Power Fault Detected MRL Sensor Changed Command Completed
• PCI Express Hot Plug Presence Detect Changed SerDes Receiver Detect Data Link Layer State Changed
• Device-Specific errors Error-Correcting Code ECC error detected in the internal packet RAM Internal Error FIFO overflow

The PEX 8505’s external Interrupt ball, PEX_INTA#, indicates the assertion and/or de-assertion of the internally generated INTx signal:
• For Hot Plug or Link State triggered INTx events, PEX_INTA# assertion is controlled by the ECC Error Check Disable register Enable PEX_INTA# Ball for Hot Plug or Link State Event bit Port 0, offset 1C8h[4] . When this bit is set, Hot Plug or Link State events trigger PEX_INTA# assertion however, an INTx message is not generated in this case. PEX_INTA# assertion and INTx message generation for Hot Plug or Link State cases are mutually exclusive.
• PEX_INTA# assertion is controlled by the ECC Error Check Disable register Enable PEX_INTA# Ball for Device-Specific Error bit Port 0, offset 1C8h[5] . When this bit is set, Device-Specific errors trigger PEX_INTA# assertion however, PEX_INTA# assertion and INTx message generation are mutually exclusive.

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Interrupts

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PCI Express Relaxed Ordering Enable 4 Not supported

Cleared to

Maximum Payload Size Software can change this field to configure the PEX 8505 ports to support other Payload Sizes however, software cannot change this field to a value larger than that indicated by the Device Capability register Maximum Payload Size Supported field offset 6Ch[2:0] . Maximum Payload Size port limitations are as follows:
• 1,024 if the number of ports is < 3
• 512 if the number of ports is < 5 7:5 000b = Indicates that the PEX 8505 port is configured to support a Maximum Payload Size of 128 bytes 001b = Indicates that the PEX 8505 port is configured to support a Maximum Payload Size of 256 bytes 010b = Indicates that the PEX 8505 port is configured to support a Maximum Payload Size of 512 bytes 011b = Indicates that the PEX 8505 port is configured to support a Maximum Payload Size of 1,024 bytes

Type RW RsvdP

Serial EEPROM and I2C

Default
000b

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Register 70h Device Status and Control All Ports Cont.

Bit s
8 9 10 11 14:12 15

Extended Tag Field Enable Not supported Cleared to

Phantom Functions Enable Not supported Cleared to

AUX Power PM Enable Not supported Cleared to

Enable No Snoop Not supported Cleared to

Maximum Read Request Size Not supported Cleared to 000b.

Reserved Hardwired to 0, as required by the PCI Express Base r1.1.

PCI Express Capability Registers

Type

Serial EEPROM and I2C

Default

RsvdP

RsvdP

RsvdP

RsvdP

RsvdP

RsvdP
000b 0

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Port Registers

Register 70h Device Status and Control All Ports Cont.

Bit s
19 20 21 31:22

Device Status

Correctable Error Detected Set when the corresponding port detects a Correctable error, regardless of the bit 0 Correctable Error Reporting Enable state.
0 = Corresponding PEX 8505 port did not detect a Correctable error 1 = Corresponding PEX 8505 port detected a Correctable error

Non-Fatal Error Detected Set when the corresponding port detects a Non-Fatal error, regardless of the bit 1 Non-Fatal Error Reporting Enable state.
Product Ordering Information
Contact your local PLX Sales Representative for ordering information.
Table A-1. Product Ordering Information

Part Numbers

PEX8505-AA25BI

PEX 8505 5-Lane, 5-port PCI Express Gen 1 Switch Plastic BGA 15 x 15 mm2, 196-ball Leaded Package

PEX8505-AA25BI G

PEX 8505 5-Lane, 5-port PCI Express Gen 1 Switch Plastic BGA 15 x 15 mm2, 196-ball LeadFree RoHS Green Package

PEX8505-AA25B I G

PEX 8505-AA RDK Port Expander Kit

G Lead-Free, RoHS-Compliant, Fully Green

I Industrial Temperature

B Ball Grid Array Package
8505 Part Number PEX PCI Express Product Family

PEX 8505 Rapid Development Kit with x4 Edge Connector

Port Expander, with
• Four x1 slots
• One x1 PCI Express cable
• One x1 PCI Express Host adapter

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General Information

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A.2 A.3

United States and International Representatives and Distributors

PLX Technology, Inc., representatives and distributors are listed at

Technical Support

PLX Technology, Inc., technical support information is listed at or call 800 759-3735 domestic only or 408

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PEX8505-AA25BI Datasheet file may be downloaded here without warranties.

Datasheet ID: PEX8505-AA25BI 520498