PEX8112-AA66BI
PEX8112-AA66BI Datasheet
ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book
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PEX8112-AA66BI |
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| ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book Version October 2008 Website Technical Support Phone 800 759-3735 408 774-9060 FAX 408 774-2169 Copyright 2008 by PLX Technology Inc. All Rights Reserved Version October, 2008 Data Book PLX Technology, Inc. Copyright Information Copyright 2007 2008 PLX Technology, Inc. All Rights Reserved. The information in this document is proprietary and confidential to PLX Technology. No part of this document may be reproduced in any form or by any means or used to make any derivative work such as translation, transformation, or adaptation without written permission from PLX Technology. PLX Technology provides this documentation without warranty, term or condition of any kind, either express or implied, including, but not limited to, express and implied warranties of merchantability, fitness for a particular purpose, and non-infringement. While the information contained herein is believed to be accurate, such information is preliminary, and no representations or warranties of accuracy or completeness are made. In no event will PLX Technology be liable for damages arising directly or indirectly from any use of or reliance upon the information contained in this document. PLX Technology may make improvements or changes in the product s and/or the program s described in this documentation at any time. PLX Technology retains the right to make changes to this product at any time, without notice. Products may have minor variations to this publication, known as errata. PLX Technology assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology products. PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX Technology, Inc. PCI Express is a trademark of the PCI Special Interest Group PCI-SIG . Tri-State is a registered trademark of National Semiconductor Corporation. All product names are trademarks, registered trademarks, or servicemarks of their respective owners. Document Number 8112-AA-SIL-DB-P1-1.2 ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 Version Date October, 2007 November, 2007 October, 2008 Description of Changes PCI Control Register Offset 100Ch in Forward Bridge Mode. Configuration Registers Chapter 15 changed Bit 30 from Reserved to Short Discard Timer Timeout Select. Appendix A Added Leaded package part number and description. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved PLX Technology, Inc. This data book contains material that is proprietary to PLX. Reproduction without the express written consent of PLX is prohibited. All reasonable attempts are made to ensure the contents of this data book are accurate however no liability, expressed or implied is guaranteed. PLX reserves the right to modify this data book, without notification, at any time. This data book is periodically updated as new information is made available. Scope This data book describes the PEX 8112 bridge operation and provides operational data for customer use. Audience This data book provides the functional details of PLX Technology’s ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge, for hardware designers and software/firmware engineers. Supplemental Documentation This data book assumes that the reader is familiar with the documents referenced below. • PLX Technology, Inc. PLX 870 W Maude Avenue, Sunnyvale, CA 94085 USA Tel 800 759-3735 domestic only or 408 774-9060, Fax 408 774-2169, The PLX PEX 8112 Toolbox includes this data book, as well as other PEX 8112 documentation, including the Errata and Schematic Design Checklist. • PCI Special Interest Group PCI-SIG 3855 SW 153rd Drive, Beaverton, OR 97006 USA Tel 503 619-0569, Fax 503 644-6708, Architecture, 1990 IEEE Standard 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture IEEE Standard 1149.1b-1994, Specifications for Vendor-Specific Extensions ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 Supplemental Documentation Abbreviations A.1 Product Ordering Information 293 A.2 United States and International Representatives and Distributors 294 A.3 Technical Support 294 ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved xvii Contents PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version xviii Copyright 2008 by PLX Technology Inc. All Rights Reserved Registers Forward Bridge Mode Configuration Registers PCI-Compatible Extended Capability Registers for PCI Express Interface 153 Offset 40h PWRMNGID Power Management Capability ID Offset 41h PWRMNGNEXT Power Management Next Capability Pointer Offset 42h PWRMNGCAP Power Management Capability. Offset 44h PWRMNGCSR Power Management Control/Status Offset 46h PWRMNGBRIDGE Power Management Bridge Support Offset 47h PWRMNGDATA Power Management Data Offset 48h DEVSPECCTL Device-Specific Control Offset 50h MSIID MSI Capability ID Offset 51h MSINEXT MSI Next Capability Pointer Offset 52h MSICTL MSI Control Offset 54h MSIADDR MSI Address Offset 58h MSIUPPERADDR MSI Upper Address Offset 5Ch MSIDATA MSI Data ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved PLX Technology, Inc. Offset 60h PCIEXID PCI Express Capability ID. 159 Offset 61h PCIEXNEXT PCI Express Next Capability Pointer 159 Offset 62h PCIEXCAP PCI Express Capability 159 Offset 64h DEVCAP Device Capability 160 Offset 68h DEVCTL PCI Express Device Control 162 Offset 6Ah DEVSTAT PCI Express Device Status 164 Offset 6Ch LINKCAP Link Capability 165 Offset 70h LINKCTL Link Control. 166 Offset 72h LINKSTAT Link Status 167 Offset 74h SLOTCAP Slot Capability 168 Offset 78h SLOTCTL Slot Control 169 Offset 7Ah SLOTSTAT Slot Status 170 Offset 84h MAININDEX Main Control Register Index 170 Offset 88h MAINDATA Main Control Register Data 170 PCI Express Extended Capability Registers 171 PCI Express Power Budget Registers 172 Offset 100h PWRCAPHDR Power Budget Enhanced Capability Header 172 Offset 104h PWRDATASEL Power Budget Data Select 172 Offset 108h PWRDATA Power Budget Data. 173 Offset 10Ch PWRBUDCAP Power Budget Capability 174 PCI Express Serial Number Registers 175 Offset 110h SERCAPHDR Serial Number Enhanced Capability Header 175 Offset 114h SERNUMLOW Serial Number Low Lower DWORD 175 Offset 118h SERNUMHI Serial Number Hi Upper DWORD 175 ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 PCI-Compatible Extended Capability Registers for PCI Express Interface 217 Offset 40h PWRMNGID Power Management Capability ID Offset 41h PWRMNGNEXT Power Management Next Capability Pointer Offset 42h PWRMNGCAP Power Management Capability. Offset 44h PWRMNGCSR Power Management Control/Status Offset 46h PWRMNGBRIDGE Power Management Bridge Support Offset 47h PWRMNGDATA Power Management Data Offset 48h DEVSPECCTL Device-Specific Control Offset 50h MSIID MSI Capability ID Offset 51h MSINEXT MSI Next Capability Pointer Offset 52h MSICTL MSI Control Offset 54h MSIADDR MSI Address Offset 58h MSIUPPERADDR MSI Upper Address Offset 5Ch MSIDATA MSI Data Offset 60h PCIEXID PCI Express Capability ID Offset 61h PCIEXNEXT PCI Express Next Capability Pointer Offset 62h PCIEXCAP PCI Express Capability. Offset 64h DEVCAP Device Capability Offset 68h DEVCTL PCI Express Device Control Offset 6Ah DEVSTAT PCI Express Device Status Offset 6Ch LINKCAP Link Capability ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved PLX Technology, Inc. Offset 70h LINKCTL Link Control. 231 Offset 72h LINKSTAT Link Status 232 Offset 74h SLOTCAP Slot Capability 233 Offset 78h SLOTCTL Slot Control 234 Offset 7Ah SLOTSTAT Slot Status 235 Offset 7Ch ROOTCTL Root Control. 236 Offset 80h ROOTSTAT Root Status 236 Offset 84h MAININDEX Main Control Register Index 237 Offset 88h MAINDATA Main Control Register Data 237 PCI Express Extended Capability Registers 238 PCI Express Power Budget Registers 239 Offset 100h PWRCAPHDR Power Budget Enhanced Capability Header 239 Offset 104h PWRDATASEL Power Budget Data Select 239 Offset 108h PWRDATA Power Budget Data. 240 Offset 10Ch PWRBUDCAP Power Budget Capability 241 PCI Express Serial Number Registers 242 Offset 110h SERCAPHDR Serial Number Enhanced Capability Header 242 Offset 114h SERNUMLOW Serial Number Low Lower DWORD 242 Offset 118h SERNUMHI Serial Number Hi Upper DWORD 242 ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version xxii Copyright 2008 by PLX Technology Inc. All Rights Reserved Chapter 1 Introduction Overview PLX Technology’s ExpressLaneTM PEX 8112 PCI Express-to-PCI Bridge allows for the use of ubiquitous PCI silicon with the high-performance PCI Express Network. As PCI Express systems proliferate, there remain many applications that do not need the extensive bandwidth nor performance features of PCI Express. With the PEX 8112, many existing chips and entire subsystems can be used, without modification, with PCI Express motherboards. PCI Express Endpoint Interface • Full Gbps per direction • Single lane and single virtual channel operation • Compatible with multi-lane and multi-virtual channel PCI Express chips • Packetized serial traffic with PCI Express Split Completion protocol • Data Link Layer Cyclic Redundancy Check CRC generator and checker • Automatic Retry of bad packets • Integrated low-voltage differential drivers • 8b/10b signal encoding • In-band interrupts and messages • Message Signaled Interrupt MSI support PCI Bus • PCI r3.0-compliant 32-bit, 66 MHz PCI Bus • PCI Master Controller allows PCI Express access to PCI Target devices • PCI Target Controller The PCI Express interface supports interrupts using MSIs. With this mechanism, a device signals an interrupt by writing to a specific memory location. The PEX 8112 uses the 64-bit Message Address version of the MSI Capability structure MSI Address and MSI Upper Address registers , and clears the No Snoop and Relaxed Ordering bits in the Requester attributes. Address and Data Configuration registers are associated with the MSI feature MSI Address, MSI Upper Address, and MSI Data. When an internal interrupt event occurs, the value in the MSI Data Configuration register is written to the PCI Express address specified by the MSI Address and MSI Upper Address Configuration registers. When MSI is enabled MSI Control register MSI Enable bit is set to 1 , the Virtual Wire Interrupt feature is disabled. MSIs are generated independently of the PCI Command register Interrupt Disable bit. MSIs are gated by the PCI Command register Bus Master Enable bit. Notes The No Snoop and Relaxed Ordering bits are cleared, because the PEX 8112 does not support these features. PCI INTx interrupts are never translated to Message Signaled Interrupts, but are always forwarded using Virtual Wire interrupts. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 The following internal events can be programmed to generate an interrupt • Serial EEPROM transaction completed • Any GPIO bit that is programmed as an input • Mailbox register written When one of these interrupts occurs, either an INTx# signal interrupt or Message Signaled interrupt is generated. Both generated-interrupt methods are described, in detail, in the following two sections. The Mailbox registers can be written from the downstream side with Memory-Mapped transactions, using the Address range defined by the PCI Base Address 0 register. INTx# Signals When an internal interrupt event occurs, it causes a PCI INTx# signal to assert. Internal interrupt sources are masked by the PCI Command register Interrupt Disable bit and are routed to one of the INTx# signals, using the PCI Interrupt Pin register. The INTx# signals are asserted only when Message Signaled Interrupts are disabled. The PCI Bus supports interrupts using MSIs. With this mechanism, a device signals an interrupt by writing to a specific memory location. The PEX 8112 uses the 64-bit Message Address version of the MSI Capability structure MSI Address and MSI Upper Address registers . Address and Data Configuration registers are associated with the MSI feature MSI Address, MSI Upper Address, and MSI Data. When an internal interrupt event occurs, the value in the MSI Data Configuration register is written to the PCI Express address specified by the MSI Address and MSI Upper Address Configuration registers. When MSI is enabled MSI Control register MSI Enable bit is set to 1 , the INTx# Interrupt signals for internally generated interrupts are disabled. MSIs are generated independently of the PCI Command register Interrupt Disable bit. MSIs are gated by the PCI Command register Bus Master Enable bit. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved Interrupts PLX Technology, Inc. THIS PAGE INTENTIONALLY LEFT BLANK. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved Chapter 6 Serial EEPROM Controller Overview The PEX 8112 provides an interface to Serial Peripheral Interface SPI -compatible serial EEPROMs. This interface consists of a Chip Select, Clock, Write Data, and Read Data balls, and operates at up to 25 MHz. Compatible 128-byte serial EEPROMs include the Catalyst CAT25C01, ST Microelectronics M95010W, and the following Atmel part numbers AT25080A, AT25160A, AT25320A, and AT25640A. The PEX 8112 supports up to a 16 MB serial EEPROM, using 1-, 2-, or 3-byte addressing. The PEX 8112 automatically determines the appropriate addressing mode. Serial EEPROM Data Format The data in the serial EEPROM is stored in the format defined in Table The Validation Signature byte is located in the first address. The Serial EEPROM Controller reads this byte to determine whether a valid serial EEPROM image exists versus a blank image. REG_BYTE_COUNT[15:0] contains the number of bytes of serial EEPROM data to be loaded. It is equal to the number of registers to be loaded times six 6 serial EEPROM bytes per register . For the remaining register-related locations, data is written into a 2-byte address that represents the Configuration register offset and Port Number, and the 4 bytes following are the data loaded for that Configuration register. Only Configuration register data specifically programmed into the serial EEPROM is loaded after the PEX 8112 exits reset. Following the register data are two bytes that determine how many shared memory locations to load. The remaining locations in the EEPROM contain the data to be loaded into the shared memory. Table 6-2 defines the Serial EEPROM Format Byte organization. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved Serial EEPROM Controller Table Serial EEPROM Data Location 0h 1h 2h 3h Value 5Ah Refer to Table 6-2 REG_BYTE_COUNT LSB REG_BYTE_COUNT MSB REGADDR LSB REGADDR MSB REGDATA Byte 0 REGDATA Byte 1 REGDATA Byte 2 REGDATA Byte 3 REGADDR LSB REGADDR MSB REGDATA Byte 0 REGDATA Byte 1 REGDATA Byte 2 REGDATA Byte 3 After transaction ordering requirements on the PCI Bus are met, the PEX 8112 requests the secondary PCI Bus. When the grant is received and the bus is idle, the PEX 8112 drives FRAME#, and the address and command. On the following Clock cycle, the first Data word is driven onto the bus and IRDY# is asserted. Data is transferred to the PCI Target when TRDY# is asserted, and continues transferring until the last word is read from the queue. When a Target Disconnect is detected, the current burst terminates. If there is data remaining in the queue, another Burst Write is initiated with the updated address. This Burst Write continues until the queue is empty, indicating the end of the Write transaction. When a PCI Express-to-PCI Posted Write terminates with a PCI Target Abort, PCI Master Abort, or PCI Retry Abort, the remaining data is read from the queue and discarded. An ERR_NONFATAL message is sent to the PCI Express Root Complex, if enabled by the PCI Express Device Control register Non-Fatal Error Reporting Enable bit. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 Forward Bridge PCI Express-to-PCI Forwarding Downstream Translation to Memory Write and Invalidate The PEX 8112 supports translation of PCI Express Memory Write Requests to PCI Memory Write and Invalidate MWI transactions. The PCI Command register Memory Write and Invalidate bit must be set, and the PCI Cache Line Size register must be set to a supported value. The MWI command can be used only when the PCI Express Byte Enables are contiguous. The address, Write Request length, and first and last Byte Enables of each request are used to determine whether an MWI command can be used. The transaction length is loaded into an internal Counter and compared to the Cache Line Size. An MWI transaction is initiated when the following three conditions exist: • Write Request contains at least the number of bytes indicated by the Cache Line Size • Write Request starts at a Cache Line boundary • All Byte Enables are asserted An internal Counter is decremented as each word is transferred to the PCI Target. At each Cache Line boundary, the Counter is used to determine whether there are at least the number of Cache Line Size bytes remaining. If the necessary number of Cache Line size bytes are present, the MWI burst continues otherwise, the MWI terminates and a Memory Write command transfers the remaining bytes. When a Memory Write Request does not begin or end on a Cache Line boundary, the request is segmented into multiple transactions. The bytes up to the first Cache Line boundary are transferred using a Memory Write command. An MWI transaction is then used to transfer the Write data beginning on the aligned Cache Line boundary, including all subsequent complete cache lines up to the final aligned Cache Line boundary contained in the original Memory Write Request. A Memory Write transaction is then used to transfer the remaining bytes of the original Memory Write Request. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved Bridge Operation PLX Technology, Inc. I/O and Configuration Writes PCI Express I/O Writes and Type 1 Configuration Writes are Non-Posted Write transactions. That is, the Completion TLP is not returned to the primary PCI Express interface until the transaction completes on the secondary PCI interface. The forwarding address range of the I/O Writes is determined by the I/O Base and I/O Limit registers and Bridge Control register ISA Enable and VGA Enable bits. When the PEX 8112 accepts each PCI Express I/O Write or Type 1 Configuration Write Request TLP, the Non-Posted Transaction queue issues a Write Request, consisting of the following: • Transaction type • Address 32 bits • Byte Enables for a single DWORD • TLP total Byte Count always a value of 1 • Sequence number 6 bits Because all I/O Writes and Type 1 Configuration Writes are 1 DWORD in length, this DWORD is always the first and last DWORD. These Write transactions complete on the PCI Bus, before the Completion TLP is returned to the PCI Express interface. PCI Express I/O Write Requests are translated into PCI I/O Write transactions. PCI Express Configuration Writes are translated into PCI Configuration transactions. The Configuration Write address can be modified to indicate a Type 0, Type 1, or special cycle. Configuration transaction forwarding is discussed in Chapter 8, “Configuration Transactions.” After the transaction ordering requirements are met, the PEX 8112 requests the secondary PCI interface. When the grant is received and the bus is idle, the PEX 8112 drives FRAME#, and the address and command. On the following Clock cycle, the Data word is driven onto the bus and IRDY# is asserted. Data is transferred to the PCI Target when TRDY# is asserted, and the transaction terminates. Only single words are transferred for these transactions. When the transaction successfully completes on the secondary bus, a Completion TLP is transmitted to the PCI Express Master. When the transaction terminates with a Master Abort, a Completion with Unsupported Request UR status is returned to the PCI Express interface and the data is discarded. When the transaction terminates with a Target Abort, a Completion with Completer Abort status is returned to the PCI Express interface and the data is discarded. An ERR_NONFATAL message is sent to the Root Complex, if enabled by the PCI Express Device Control register Non-Fatal Error Reporting Enable bit. When the transaction terminates with a Retry, the PEX 8112 repeats the transaction until the data transfer is complete or an error condition is detected. When the PEX 8112 is unable to deliver Write data after the number of attempts determined by the PCI Control register PCI Express-to-PCI Retry Count field, a Completion with Completer Abort status is returned to the PCI Express interface, and the data is discarded. A ERR_NONFATAL message is sent to the Root Complex, if enabled by the PCI Express Device Control register Non-Fatal Error Reporting Enable bit. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 Forward Bridge PCI Express-to-PCI Forwarding Downstream Read Transactions PCI Express-to-PCI Read transactions are Prefetchable or Non-Prefetchable, as defined in Table Because a PCI Express Read Request always specifies the number of bytes to read, the PEX 8112 never reads more data than requested. When translating a PCI Express Memory Read Request into a PCI transaction, the PEX 8112 uses its Prefetchable and Non-Prefetchable Memory windows to determine the proper PCI Read command to use. Table Prefetchable or Non-Prefetchable PCI Express-to-PCI Read Transactions PCI Express Transaction Prefetchable Memory Read Request I/O Read Request Type 0 Configuration Read Request Type 1 Configuration Read Request Yes, when in Prefetchable space Non-Prefetchable Not forwarded Non-Prefetchable Non-Prefetchable Memory Read Transactions When a PCI Express Memory Read falls within Non-Prefetchable Address space, the PEX 8112 uses the PCI Memory Read command to read the number of bytes requested in the PCI Express Memory Read Request. The forwarding address range is determined by the Memory Base, Memory Limit, Prefetchable Memory Base, and Prefetchable Memory Limit registers and Bridge Control register VGA Enable bit. Prefetchable Memory Read Transactions When a PCI Express Memory Read falls within Prefetchable Address space, the PEX 8112 uses the PCI Memory Read, Memory Read Line, or Memory Read Line Multiple command. The command type is based upon the starting address and the number of bytes in the request. The PEX 8112 does not extend the length of the burst, but reads the number of bytes requested, as per the PCI ExpressBridge r1.0. That is, the PEX 8112 does not prefetch data from the PCI Target, regardless of whether the data is located in Prefetchable Memory space. Refer to Table Memory Read Line transactions are terminated at a Cache Line boundary when there is not at least one cache line of data remaining to read, or if the transaction can be converted to a Memory Read Line Multiple transaction. Any remaining words are read, using a Memory Read command. Table Prefetchable Memory Read Transactions Memory Read Command Memory Read Line Memory Read Line Multiple Status Used when less than a cache line of data is read. Used when at least one cache line of data is read, and the starting address is not on a Cache Line boundary. Used when at least one cache line of data is read, and the starting address is on a Cache Line boundary. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved Bridge Operation PLX Technology, Inc. Memory Read Request When the PEX 8112 accepts each PCI Express Memory Read Request, the Non-Posted Transaction queue issues a Read Request, consisting of the following: • Transaction type Memory Read • Address 64 bits • Byte Enables for the first and last DWORD • TLP total Byte Count of 10 bits • Sequence Number 6 bits A Memory Read, Memory Read Line, or Memory Read Line Multiple command is performed on the PCI Bus, depending upon the starting address, Byte Enables, and Read Request length. After the transaction ordering requirements are met, the PEX 8112 requests the secondary PCI interface. When the grant is received and the bus is idle, the PEX 8112 drives FRAME# and the address and command. On the following Clock cycle, IRDY# is asserted. Read data is transferred to the PEX 8112 when TRDY# is asserted, and continues transferring until the Read Request length is satisfied or the Target disconnects. As the data is read from the PCI Bus, it is written to the Non-Posted Transaction Completion queue. When the transaction terminates with a Master Abort, a Completion with UR status is returned to the PCI Express interface. When the transaction terminates with a Target Abort, a Completion with Completer Abort status is returned to the PCI Express interface. An ERR_NONFATAL messages is sent to the Root Complex, if enabled by the PCI Express Device Control register Non-Fatal Error Reporting Enable bit. When the transaction terminates with a Retry, the PEX 8112 repeats the transaction until the Data transfer is complete or an error condition is detected. When the PEX 8112 is unable to complete the Read transaction after the number of attempts specified by the PCI Control register PCI-to-PCI Express Retry Count field, a Completion with Completer Abort status is returned to the PCI Express interface. When a transaction terminates with a PCI Disconnect, the PEX 8112 starts a new Read transaction at the current address, and attempts to complete reading the requested number of bytes. After the transaction is complete, a Completion is transmitted to the PCI Express Master. The PEX 8112 does not service a new Memory Read Request from the Host performs Retries on the PCI Bus until it receives a Completion from the previous Read Request sent by the Host or the PCI-toPCI Express Retry Count is exceeded. Memory Read Request Locked A PCI Express Memory Read Request Locked is similar to a normal Memory Read Request. Refer to Chapter 11, “Exclusive Locked Access,” for details. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 Forward Bridge PCI Express-to-PCI Forwarding Downstream I/O and Configuration Reads PCI Express I/O Reads and Type 1 Configuration Reads are Non-Prefetchable Read transactions. That is, the Byte Enable information is preserved and no additional bytes are requested. The forwarding address range of the I/O Reads is determined by the I/O Base and I/O Limit registers and Bridge Control register ISA Enable and VGA Enable bits. When the PEX 8112 accepts each PCI Express I/O Read or Type 1 Configuration Read Request, the Non-Posted Transaction queue issues a Read Request, consisting of the following: • Transaction type I/O or Configuration Type 1 Read • Address 32 bits • Byte Enables for a single DWORD • TLP total Byte Count always a value of 1 • Sequence Number 6 bits An I/O Read or Configuration Read command is performed on the PCI Bus. The Configuration Read address can be modified to indicate a Type 0, Type 1, or special cycle. Configuration transaction forwarding is discussed in Chapter 8, “Configuration Transactions.” After the transaction ordering requirements are met, the PEX 8112 requests the secondary PCI interface. When the grant is received and the bus is idle, the PEX 8112 drives FRAME#, and the address and command. On the following Clock cycle, IRDY# is asserted. Read data is transferred to the PEX 8112 when TRDY# is asserted, and the transaction terminates. Only single DWORDs are transferred for these transactions. When the transaction terminates with a Master Abort, a Completion with UR status is returned to the PCI Express interface. When the transaction terminates with a Target Abort, a Completion with Completer Abort status is returned to the PCI Express interface. An ERR_NONFATAL message is sent to the Root Complex, if enabled by the PCI Express Device Control register Non-Fatal Error Reporting Enable bit. When the transaction terminates with a Retry, the PEX 8112 repeats the transaction until the Data transfer is complete or an error condition is detected. When the PEX 8112 is unable to complete the Read transaction after the number of attempts specified by the PCI Control register PCI-to-PCI Express Retry Count field, a Completion with Timeout status is returned to the PCI Express interface. After the transaction is complete, a Completion is transmitted to the PCI Express Master. The PEX 8112 does not service a new I/O Read Request or Type 1 Configuration Read from the Host performs Retries on the PCI Bus until it receives a Completion from the previous Read Request sent by the Host or the PCI-to-PCI Express Retry Count is exceeded. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved Bridge Operation PLX Technology, Inc. Forward Bridge PCI-to-PCI Express Forwarding Upstream Transaction Types Table 9-8 defines the PCI transactions forwarded upstream to the PCI Express interface. Table PCI Transactions Forwarded Upstream to PCI Express Interface Secondary Bus PCI Command Memory Write or Memory Write and Invalidate Memory Read, Memory Read Line or Memory Read Line Multiple I/O Write I/O Read Primary Bus PCI Express Command Memory Write Request Memory Read Request I/O Write Request I/O Read Request Write Decomposition PCI Write transactions transfer Byte Enables with every Data phase however, the PCI Express interface supports Byte Enables only on the first and last DWORDs of a request. Furthermore, non-contiguous Byte Enables are permitted only for requests of 1 or 2 DWORDs in length, and requests with no Byte Enables set must use a length of 1 DWORD. Therefore, in certain cases, the PEX 8112 must break up PCI Write Requests into multiple PCI Express requests. Byte Enables are always set in PCI Memory Write and Invalidate transactions therefore, these transactions are not broken up into two separate transactions due to non-contiguous Byte Enables. PCI Express Write transactions cannot cross 4-KB Address boundaries therefore, PCI Writes are terminated with a Disconnect at 4-KB boundaries. Additionally, PCI Writes are terminated with a Disconnect when the Maximum Payload Size is reached. Read Decomposition PCI Express Read transactions cannot cross 4-KB Address boundaries therefore, PCI Reads that cross a 4-KB Address Boundary space are broken up into multiple PCI Express Read transactions. When a PCI Read Request crosses a 4-KB Address Boundary space, the PEX 8112 disconnects at the boundary. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 Forward Bridge PCI-to-PCI Express Forwarding Upstream PCI Express Header Field Formation Rules Table 9-9 defines the PCI Express Header Field Formation rules. Table PCI Express Header Field Formation Rules Fmt[1:0] Type[4:0] TC[3:0] Attr[1:0] TD Header Item Rule Single address PCI cycles below the 4-GB Address Boundary space use a 3-DWORD Header. Dual Address cycles at or above the 4-GB boundary use a 4-DWORD Header. Write Requests use a request format with data. Populated, based upon the command translations described in Section For requests, this field must be cleared to For Completions, this field must contain the value supplied in the corresponding request. These bits include the Relaxed Ordering and No Snoop attributes. Always cleared to Cleared to The PEX 8112 does not support End-to-end Cyclic Redundancy Check ECRC in the TLP Digest. Length[9:0] Requester ID[15:0] Tag[7:0] First DWORD Byte Enable[3:0] and Last DWORD Byte Enable[3:0] Address[63:2] 4-DWORD Header or Address[31:2] 3-DWORD Header Endpoint. Set to 1 when the PEX 8112 is forwarding an Uncorrectable Data error from the PCI Bus. PCI Write or Read Request length, rounded up to nearest DWORD-aligned boundary. Assigned by the PEX 8112, comprised of the Bus Number, Device Number, and Function Number. Sequentially assigned by the PEX First and last Byte Enables. Transaction DWORD starting address. Value is derived from the Byte address of the PCI transaction, by rounding the address down to the nearest DWORD-aligned boundary. Requester ID and Tag The PEX 8112 uses the Bus Number from the Secondary Bus Number register , Device Number always a value of 0 , and Function Number always a value of 0 to create the Requester ID. The 8-bit Tag is created by the TLP Controller, and is unique for each transaction. 15 Bus Number Requester ID Device Number Function Number ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved Bridge Operation PLX Technology, Inc. Memory Write or Memory Write and Invalidate Memory Write or Memory Write and Invalidate transactions are performed as a PCI Express Memory Write Request. The forwarding address range is determined by the Memory Base, Memory Limit, Prefetchable Memory Base, and Prefetchable Memory Limit registers and Bridge Control register VGA Enable bit. Writes cannot cross 4-KB Address boundaries. Write data posting is required for these transactions. The PEX 8112 terminates these transactions with a Retry when the PEX 8112 is locked from the PCI Express interface. When the PEX 8112 determines that a PCI Write transaction is to be forwarded to the PCI Express interface, DEVSEL# and TRDY# are asserted, assuming that there is sufficient space in the 8-DWORD buffer. When there is insufficient Buffer space, the PEX 8112 responds with a Retry. When there is sufficient space, the PEX 8112 accepts Write data until one of the following occurs: • PCI Master terminates the transaction by de-asserting FRAME# • 4-KB Address Boundary space is reached • Maximum Payload Size is reached • No Byte Enables, or Partial Byte Enables, are detected during Memory Write When one of these events occurs, the PEX 8112 terminates the PCI transaction with a Disconnect. If no Byte Enables, or partial Byte Enables, are asserted during a DWORD transaction, the Write transaction must be broken up into two separate transactions. The data with no Byte Enables, or partial Byte Enables and the corresponding address are written into the Posted Write Data queue as a new transaction. The TLP Controller prioritizes these transactions. When the Posted Write’s Sequence Number is less than that of the Non-Posted transaction, the Posted Write is performed first. When the Posted Write’s Sequence Number is greater than that of the Non-Posted transaction, the transactions alternate. Delayed Transactions Non-Posted PCI transactions except Memory Write transactions are performed as Delayed transactions on the PCI Bus. A Delayed transaction occurs when the PEX 8112 responds to a NonPosted transaction with a Retry, and forwards the request to the PCI Express interface. When the associated Completion returns from the PCI Express Target, the PEX 8112 buffers the Completion until the PCI Master Retries the transaction. The following information is latched from the PCI Bus and stored into the Non-Posted Transaction queue when a new Delayed transaction is detected: • Address • Address Parity • Command • Byte Enables • Data for Write transactions • Data Parity for Write transactions After latching the above information, the PCI transaction terminates with a Retry. The PEX 8112 then transmits the Delayed transaction request upstream, to the PCI Express interface: • When the Delayed request is a Read Memory, I/O, or Configuration , the Read data is read from the PCI Express interface and stored in the TLP Controller • When the Delayed request is a Write I/O or Configuration , the Write data is delivered to the PCI Express Target When the transaction successfully completes on the PCI Express interface, and all ordering constraints with Posted Write transactions are satisfied, the PEX 8112 transfers data to the PCI Master when the Master Retries the transaction. The PEX 8112 asserts TRDY# and drives data until the final DWORD is transferred from the queue to the PCI Master. When the Master terminates the transaction before all queue data is transferred, the remaining data is read from the queue and discarded. Table Bytes Requested by PCI Express Interface Determined by PCI Command, Address Space, Register, and Bit after Request Reaches Top of Queue PCI Transaction Address Space Blind Prefetch Enable Number of DWORDs Requested Memory Read Memory Read Line Memory Read Line Multiple Non-prefetchable Cache Line Size Cache Line Size 2 Cache Line Sizes Blind Prefetch When Blind Prefetch mode is enabled Device-Specific Control register Blind Prefetch Enable bit is set , the PEX 8112 can prefetch a user-defined data block from the Host when a Memory Read transaction is performed, instead of one DWORD at a time in standard operation. Prefetching can improve Read performance, because the PEX 8112 can burst its Prefetchable data onto the PCI Bus when the Endpoint requests it. The PEX 8112 discards remaining unused data. The Prefetch Size can be programmed from 0 to 4 KB of data, by way of the PCI Control register Programmed Prefetch Size field. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 Forward Bridge PCI-to-PCI Express Forwarding Upstream I/O Write I/O Write transactions are performed as a PCI Express I/O Write Request. The forwarding address range is determined by the I/O Base and I/O Limit registers and Bridge Control register ISA Enable and VGA Enable bits. This transaction is performed as a Delayed transaction on the PCI Bus. Posting these transactions is not permitted. A Completion must be received from the PCI Express Target before the transaction is completed on the PCI Bus. When the PEX 8112 determines that a PCI I/O Write transaction is to be forwarded to the PCI Express interface, DEVSEL# and STOP# are asserted, indicating a Retry. The Address, Address Parity, Command, Data, Data Parity, and Byte Enables are stored into an entry in the Non-Posted Transaction queue, assuming that there is sufficient space in the queue. If there is insufficient space, the transaction is Retried without entering the transaction into the queue. After the request reaches the top of the Non-Posted Transaction queue, an I/O Write Request is transmitted to the PCI Express interface. The Byte Enables are passed through from the PCI Bus, and only 1 DWORD is transferred. When the Write Request does not successfully complete on the PCI Express interface, the Write Request entry in the Non-Posted Transaction queue is appropriately marked. When the transaction is Retried on the PCI Bus, it terminates with a Target Abort response. When the I/O Write Request successfully completes on the PCI Express interface, the I/O Write Request entry in the Non-Posted Transaction queue is marked as complete. When the transaction successfully completes on the PCI Express interface, the PEX 8112 asserts TRDY# to complete the transaction when the Master Retries the transaction. The I/O Write Request is removed from the Non-Posted Transaction queue when the PCI Master Retries the transaction and the transaction completes successfully or not on the PCI Express interface. I/O Read I/O Read transactions are performed as a PCI Express I/O Read Request. The forwarding address range is determined by the I/O Base and I/O Limit registers and Bridge Control register ISA Enable and VGA Enable bits. This transaction is performed as a Delayed transaction on the PCI Bus. When the PEX 8112 determines that a PCI I/O Read transaction is to be forwarded to the PCI Express interface, DEVSEL# and STOP# are asserted, indicating a Retry. The Address, Command, Address Parity, and Byte Enables are stored into an entry in the Non-Posted Transaction queue, assuming that there is sufficient space in the queue. If there is insufficient space, the transaction is Retried without entering the transaction into the queue. After the request reaches the top of the Non-Posted Transaction queue, an I/O Read Request is transmitted to the PCI Express interface. The Byte Enables are passed through from the PCI Bus, and only 1 DWORD is requested. When all ordering constraints with Posted Write transactions are satisfied, the PEX 8112 transfers data to the PCI Master when the Master Retries the transaction. The PEX 8112 asserts TRDY# and drives a single DWORD of data from the queue to the PCI Master. If the I/O Read Request does not successfully complete on the PCI Express interface, the Read Request entry in the Non-Posted Transaction queue is appropriately marked. When the transaction is Retried on the PCI Bus, it terminates with a Target Abort response. When the I/O Read Request successfully completes on the PCI Express interface, the Read Request entry in the Non-Posted Transaction queue is marked as complete. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved Bridge Operation PLX Technology, Inc. Forward Bridge PCI Transaction Terminations Table 9-11 defines the transaction termination methods used by PCI Masters. Table 9-12 defines the transaction termination methods used by PCI Targets. Table PCI Master Transaction Termination Methods Termination Methods Normal Termination Master Abort The Master de-asserts FRAME# at the beginning of the last Data phase and de-asserts IRDY# at the end of the last Data phase if the Target asserts TRDY# or STOP#. If the Master does not detect that DEVSEL# is asserted from the Target within five Clock cycles after asserting FRAME#, the transaction terminates with a Master Abort. If FRAME# remains asserted, the Master de-asserts FRAME# on the next cycle, then de-asserts IRDY# on the following cycle. IRDY# must be asserted in the same cycle in which FRAME# de-asserts. If FRAME# is de-asserted, IRDY# can be de-asserted on the next Clock cycle following detection of the Master Abort condition. Table PCI Target Transaction Termination Methods Termination Methods Normal Termination Target Retry Target Disconnect with Data Target Disconnect without Data Target Abort TRDY# and DEVSEL# are asserted in conjunction with FRAME# de-assertion and IRDY# assertion. STOP# and DEVSEL# asserted without TRDY# during the first Data phase. No Data transfers occur during the transaction, and the Master must repeat the transaction. STOP# and DEVSEL# asserted with TRDY#, which indicates that this is the last transfer of the transaction. If FRAME# is de-asserted, this is considered a normal termination, although STOP# is asserted. STOP# and DEVSEL# are asserted without TRDY# after previous data transfers occurred, which indicates that no more Data transfers occur during this transaction. STOP# is asserted without DEVSEL# and TRDY#, which indicates that the Target is never able to complete this transaction. DEVSEL# must be asserted for at least one Clock cycle during the transaction otherwise, the Master detects a Master Abort. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 Forward Bridge PCI Transaction Terminations PCI Master Termination Initiated by PEX 8112 The PEX 8112, as a PCI Master, uses normal termination if the Target asserts DEVSEL# within five Clock cycles of FRAME# assertion. As a PCI Master, the PEX 8112 terminates a transaction when any of the following occur: • During a Delayed Write transaction I/O or Configuration Write , a single DWORD is delivered • During a Non-Prefetchable Read Memory, I/O, or Configuration , a single DWORD is read from the Target • In the case of a Prefetchable Read transaction, the number of words requested in the PCI Express request are read from the PCI Target • In the case of a Posted Write transaction, the last word for the transaction is written to the PCI Target • In the case of a Burst transfer, with the exception of Memory Write and Invalidate transactions, the Master Latency Timer expires and the PCI Bus Grant is de-asserted • Target terminates the transaction with a Retry, Disconnect, or Target Abort When a Posted Write or Prefetchable Read transaction terminates because of a latency timeout, another transaction is initiated to complete the transfer. PCI Master Abort Received by PEX 8112 ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved Bridge Operation PLX Technology, Inc. Delayed Write Target Termination Response When the PEX 8112 initiates a Delayed Write transaction on the PCI Bus, it responds to certain Target terminations as defined in Table Table PEX 8112 Response to Target Terminations upon Delayed Write Transactions Each register is 32 bits wide, and is accessed one byte, word, or DWORD at a time. These registers use Little Endian byte ordering, which is consistent with the PCI r3.0. The least significant byte in a DWORD is accessed at Address The least significant bit in a DWORD is 0, and the most significant bit is After the PEX 8112 is powered up or reset, the registers are set to their default values. Writes to unused registers are ignored. Reads from unused registers return a value of Table Forward Bridge Mode PCI Base Address 0 Register Map Address Offset 0000h 0FFFh 1000h 1FFFh 2000h 2FFFh 8000h 9FFFh Register Space PCI-Compatible Configuration registers Main Configuration registers 8-KB internal shared memory Table Selecting Register Space AD12 0 1 Register Space PCI-Compatible Configuration registers Main Configuration registers ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved Forward Bridge Mode Configuration Registers PLX Technology, Inc. Indexed Addressing In addition to Memory-Mapped accesses, the PEX 8112 Main Configuration registers can be accessed using the Main Control Register Index and Main Control Register Data registers. This method allows all Main Configuration registers to be accessed using Configuration transactions, rather than Memory transactions. First, the Main Configuration register offset is written to the Main Control Register Index register offset 84h . Then, the Main Configuration register is written or read by accessing the Main Control Register Data register offset 88h . The Main Control Register Index and Main Control Register Data registers are used only to access the Main Control registers, because there is a built-in offset of 1000h. For example, if the Main Control Register Index register is set to 20h, the Main Control Register Data register stores the contents of the General-Purpose I/O Control register during a Memory Read. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 Configuration Access Types Configuration Access Types Table 15-3 defines configuration access types referenced by the registers in this chapter. Table Configuration Access Types Access Type CFG MM EE Description Initiated by PCI Configuration transactions on the primary bus. Initiated by PCI Memory transactions on the primary or secondary bus, using the Address range defined by the PCI Base Address 0 register. Initiated by the Serial EEPROM Controller during initialization. Register Attributes Table 15-4 defines the register attributes used to indicate access types provided by each register bit/field. Table Access Provided by Register Bits Register Attribute HwInit RsvdP RsvdZ RW RW1C Hardware-Initialized Register bits are initialized by firmware or hardware mechanisms such as ball strapping on the BAR0ENB#, EXTARB, and FORWARD balls or serial EEPROM. Bits are Read-Only after initialization and reset only with a Fundamental Reset. Read-Only Register bits are Read-Only and cannot be altered by software. Register bits are initialized by a PEX 8112 Hardware-Initialization mechanism or PEX 8112 Serial EEPROM register Initialization feature. Reserved and Preserved Reserved for future RW implementations. Registers are Read-Only and must return 0 when read. Software must preserve the value read, for writes to bits. Reserved and Zero Reserved for future RW1C implementations. Registers are Read-Only and must return 0 when read. Software must use 0 for Writes to bits. Read-Write Register bits are Read-Write and set or cleared by software to the needed state. Read-Only Status, Write 1 to Clear Status Register bits indicate status when read a set bit that is indicating a status event, is cleared by writing 0 to RW1C bits has no effect. Write-Only Used to indicate that a register is written by the Serial EEPROM Controller. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved Forward Bridge Mode Configuration Registers downstream queue that is, all ordering requirements are satisfied and the PEX 8112 is ready to complete the Delayed Transaction with the originating Master on the secondary bus . When the originating Master does not repeat the transaction before the Counter expires, the PEX 8112 deletes the Delayed Transaction from its queue and sets bit 10 Discard Timer Status . 0 = Secondary Discard Timer counts 215 PCI clock periods 1 = Secondary Discard Timer counts 210 PCI clock periods Discard Timer Status 10 Set to 1 when the Secondary Discard Timer expires and a Delayed Completion is discarded from a queue within the PEX Writing 1 clears this bit. RW1C WO Discard Timer SERR# Enable When set to 1, enables the PEX 8112 to generate an ERR_NONFATAL message on the primary bus when the Secondary Discard Timer expires and a Delayed Transaction is discarded from a queue within the PEX 11 0 = Does not generate ERR_NONFATAL message on the primary bus as a result of the Secondary Discard Timer expiration 1 = Generates ERR_NONFATAL message on the primary bus when the Secondary Discard Timer expires and a Delayed Transaction is discarded from a queue within the PEX 8112 15:12 Reserved RsvdP Default 0 ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 Register Configuration and Map PCI-Compatible Extended Capability Registers for PCI Express Interface This section details the PEX 8112 Forward Bridge mode PCI-Compatible Extended Capability registers for the PCI Express interface. Table 15-7 defines the register map. Table Forward Bridge Mode PCI-Compatible Extended Capability for PCI Express Interface Register Map PCI Configuration Register Offset 44h 48h 4Ch 50h 54h 58h 5Ch 60h 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 24 23 16 15 Power Management Capability Power Management Next Capability Pointer Power Management Capability ID Power Management Data Power Management Bridge Support Power Management Control/Status Device-Specific Control Reserved MSI Control MSI Next Capability Pointer MSI Capability ID MSI Address MSI Upper Address Reserved MSI Data Enable Relaxed Ordering 4 Not supported Forced to Maximum Payload Size Sets the maximum TLP Payload Size for the PEX As a Receiver, the PEX 8112 must handle TLPs as large as the set value as Transmitter, the PEX 8112 must not generate TLPs exceeding the set value. Permissible values for transmitted TLPs are indicated in the Device Capability register Maximum Payload Size Supported field. 7:5 000b = 128 bytes 001b = 256 bytes 010b = 512 bytes 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = Reserved EE Default 000b ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 Register Configuration and Map Register Offset 68h DEVCTL PCI Express Device Control Cont. Bit s CFG MM Extended Tag Field Enable 0 = PEX 8112 is restricted to a 5-bit Tag field 8 1 = Enables PEX 8112 to use an 8-bit Tag field as a Requester Forced to 0 when the Device Capability register Extended Tag Field Supported bit is cleared. Phantom Function Enable 9 Not supported Hardwired to Auxiliary AUX Power PM Enable 10 Not supported Hardwired to Enable No Snoop 11 Not supported Hardwired to Maximum Read Request Size The value specified in this register is the upper boundary of the PCI Control register Programmed Prefetch Size field if the Device-Specific Control register Blind Prefetch Enable bit is set. Sets the Maximum Read Request Size for the PEX 8112 as a Requester. The PEX 8112 must not generate Read Requests with a size that exceeds the set value. 14:12 000b = 128 bytes 001b = 256 bytes 010b = 512 bytes 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = Reserved Bridge Configuration Retry Enable 0 = PEX 8112 does not generate Completions with Completion Retry Status 15 on behalf of PCI Express-to-PCI Configuration transactions. 1 = PEX 8112 generates Completions with Completion Retry Status on behalf of PCI Express-to-PCI Configuration transactions. Occurs after a delay determined by the CRS Timer register. EE Default 010b ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Each register is 32 bits wide, and is accessed one byte, word, or DWORD at a time. These registers use Little Endian byte ordering, which is consistent with the PCI r3.0. The least significant byte in a DWORD is accessed at Address The least significant bit in a DWORD is 0, and the most significant bit is After the PEX 8112 is powered up or reset, the registers are set to their default values. Writes to unused registers are ignored. Reads from unused registers return a value of Address Offset 0000h 0FFFh 1000h 1FFFh 2000h 2FFFh 8000h 9FFFh Register Space PCI-Compatible Configuration registers Main Configuration registers Memory-Mapped indirect access to downstream PCI Express Endpoint registers 8-KB internal shared memory Table Selecting Register Space AD12 0 1 Register Space PCI-Compatible Configuration registers Main Configuration registers ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved PLX Technology, Inc. Indexed Addressing In addition to Memory-Mapped accesses, the PEX 8112 Main Configuration registers can be accessed using the Main Control Register Index and Main Control Register Data registers. This method allows all Main Configuration registers to be accessed using Configuration transactions, rather than Memory transactions. First, the Main Configuration register offset is written to the Main Control Register Index register offset 84h . Then, the Main Configuration register is written or read by accessing the Main Control Register Data register offset 88h . The Main Control Register Index and Main Control Register Data registers are used only to access the Main Control registers, because there is a built-in offset of 1000h. For example, if the Main Control Register Index register is set to 20h, the Main Control Register Data register stores the contents of the General-Purpose I/O Control register during a Memory Read. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 Configuration Access Types Configuration Access Types Table 16-3 defines configuration access types referenced by the registers in this chapter. Table Configuration Access Types Access Type CFG MM EE Description Initiated by PCI Configuration transactions on the primary bus. Initiated by PCI Memory transactions on the primary or secondary bus, using the Address range defined by the PCI Base Address 0 register. Initiated by the Serial EEPROM Controller during initialization. Register Attributes Table 16-4 defines the register attributes used to indicate access types provided by each register bit. Table Access Provided by Register Bits Register Attribute HwInit RsvdP RsvdZ RW RW1C Hardware-Initialized Register bits are initialized by firmware or hardware mechanisms such as ball strapping on the BAR0ENB#, EXTARB, and FORWARD balls or serial EEPROM. Bits are Read-Only after initialization and reset only with “Fundamental Reset.” Read-Only Register bits are Read-Only and cannot be altered by software. Register bits are initialized by a PEX 8112 Hardware-Initialization mechanism or PEX 8112 Serial EEPROM register Initialization feature. Reserved and Preserved Reserved for future RW implementations. Registers are Read-Only and must return 0 when read. Software must preserve the value read, for writes to bits. Reserved and Zero Reserved for future RW1C implementations. Registers are Read-Only and must return 0 when read. Software must use 0 for Writes to bits. Read-Write Register bits are Read-Write and set or cleared by software to the needed state. Read-Only Status, Write 1 to Clear Status Register bits indicate status when read a set bit that is indicating a status event, is cleared by writing 0 to RW1C bits has no effect. Write-Only Used to indicate that a register is written by the Serial EEPROM Controller. ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved PLX Technology, Inc. Register Summary Register Group Selects the number of PCI clocks that the PEX 8112 waits for a Master on the primary bus, to repeat a Delayed Transaction request. The Counter starts after the Completion PCI Express Completion associated with the Delayed Transaction request reaches the head of the PEX 8112 downstream queue that is, all ordering requirements are satisfied and the PEX 8112 is ready to complete the Delayed Transaction with the originating Master on the primary bus . When the originating Master does not repeat the transaction before the Counter expires, the PEX 8112 flushes the Delayed Transaction from its queue and sets bit 10 Discard Timer Status . Usually, this bit selects either 215 or 210 PCI clocks. When using the PEX 8112 Blind Prefetch feature, these long discard delays could result in significant performance degradation. The PEX 8112 includes an additional Control bit PCI Control register Short Discard Timer Timeout Select bit that can 8 provide a short timeout of 26 clocks. PCI Control Register Short Primary Discard Discard Timer Timer Timeout Select Bit Value Bit 30 Value Transaction data is flushed in 215 PCI clock periods Transaction data is flushed in 210 PCI clock periods Transaction data is flushed in 26 PCI clock periods Note “X” is “Don’t Care.” Secondary Discard Timer 9 Discard Timer Status 10 Set to 1 when the Primary Discard Timer expires and a Delayed Completion is discarded from a queue within the PEX RW1C Discard Timer SERR# Enable When set to 1, enables the PEX 8112 to assert SERR# on the primary bus when the Primary Discard Timer expires and a Delayed Transaction is discarded from a queue within the PEX 11 0 = Does not assert SERR# on the primary bus as a result of the Primary Discard Timer expiration 1 = Generates SERR# on the primary bus when the Primary Discard Timer expires and a Delayed Transaction is discarded from a queue within the PEX 8112 15:12 Reserved RsvdP Default ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 Register Summary PCI-Compatible Extended Capability Registers for PCI Express Interface PCI Configuration Register Offset 48h 4Ch 54h 58h 5Ch 64h 68h 6Ch 70h 74h 78h 7Ch 80h 84h 88h 24 23 16 15 Power Management Capability Power Management Next Capability Pointer Power Management Capability ID Power Management Data Power Management Bridge Support Enable Relaxed Ordering 4 Not supported Forced to Maximum Payload Size Sets the maximum TLP Payload Size for the PEX As a Receiver, the PEX 8112 must handle TLPs as large as the set value as Transmitter, the PEX 8112 must not generate TLPs exceeding the set value. Permissible values for transmitted TLPs are indicated in the Device Capability register Maximum Payload Size Supported field. 7:5 000b = 128 bytes 001b = 256 bytes 010b = 512 bytes 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = Reserved EE Default 000b ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved PLX Technology, Inc. Register Offset 68h DEVCTL PCI Express Device Control Cont. Bit s CFG MM Extended Tag Field Enable 0 = PEX 8112 is restricted to a 5-bit Tag field 8 1 = Enables PEX 8112 to use an 8-bit Tag field as a Requester Forced to 0 when the Device Capability register Extended Tag Field Supported bit is cleared. Phantom Function Enable 9 Not supported Hardwired to Auxiliary AUX Power PM Enable 10 Not supported Hardwired to Enable No Snoop 11 Not supported Hardwired to Maximum Read Request Size The value specified in this register is the upper boundary of the PCI Control register Programmed Prefetch Size field if the Device-Specific Control register Blind Prefetch Enable bit is set. 14:12 Sets the Maximum Read Request Size for the PEX 8112 as a Requester. The PEX 8112 must not generate Read Requests with a size that exceeds the set value. 000b = 128 bytes 001b = 256 bytes 010b = 512 bytes 011b = 1,024 bytes 100b = 2,048 bytes 101b = 4,096 bytes 110b, 111b = Reserved Bridge Configuration Retry Enable 0 = PEX 8112 does not generate Completions with Completion Retry Status 15 on behalf of PCI Express-to-PCI Configuration transactions 1 = PEX 8112 generates Completions with Completion Retry Status on behalf of PCI Express-to-PCI Configuration transactions EE Default 010b ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved October, 2008 Register Summary Product Ordering Information Contact your local PLX Sales Representative for ordering information. Table A-1. Product Ordering Information PEX8112-AA66BI PEX 8112 PCI Express-to-PCI Bridge, Standard BGA 144-Ball, 13 x 13 mm2 Leaded Package PEX8112-AA66BI F PEX 8112 PCI Express-to-PCI Bridge, Standard BGA 144-Ball, 13 x 13 mm2 Lead Free Package PEX8112-AA66FBI F PEX 8112 PCI Express-to-PCI Bridge, Fine-Pitch BGA 161-Ball, 10 x 10 mm2 Lead Free Package PEX8112-AA66 FBI F F Lead-free, RoHS Compliant I Industrial Temperature B Plastic Ball Grid Array Package FB Fine-Pitch Plastic Ball Grid Array Package PEX 8112-AA RDK-F PEX 8112-AA RDK-R 8112 Part Number PEX PCI Express Product Family PEX 8112 Forward Bridge Rapid Development Kit ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved General Information PLX Technology, Inc. A.2 A.3 United States and International Representatives and Distributors PLX Technology, Inc., representatives and distributors are listed at Technical Support PLX Technology, Inc., technical support information is listed at or call 800 759-3735 domestic only or 408 ExpressLane PEX 8112-AA PCI Express-to-PCI Bridge Data Book, Version Copyright 2008 by PLX Technology Inc. All Rights Reserved |
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