AMMC-5023-W10

AMMC-5023-W10 Datasheet

AMMC-5023

Part	Datasheet
AMMC-5023-W10	AMMC-5023-W10 (pdf)

Related Parts	Information
AMMC-5023-W50	AMMC-5023-W50

PDF Datasheet Preview
AMMC-5023 23 GHz Low Noise Amplifier GHz Data Sheet Chip Size Chip Size Tolerance Chip Thickness Pad Dimensions: 1880 x 600 µm 74 x mils ±10 µm mils 100 ± 10 µm 4 ± mils 80 x 80 µm x mils , or larger Avago’s AMMC-5023 is a high gain, low noise amplifier that operates from 21 GHz to over 30 GHz. By eliminating the complex tuning and assembly processes typically required by hybrid discrete-FET amplifiers, the AMMC5023 is a cost-effective alternative in both GHz and GHz communications receivers. The device has good input and output match to 50 Ohm and is unconditionally stable to more than 40 GHz. The backside of the chip is both RF and DC ground. This helps simplify the assembly process and reduces assembly related performance variations and costs. It is fabricated in a PHEMT process to provide exceptional noise and gain performance. For improved reliability and moisture protection, the die is passivated at the active areas. Features • Frequency range GHz • High gain 23 dB • Low noise figure dB • Input and output return loss >10 dB • Single supply bias 5 volts, 28 mA • Optional bias adjust Applications • Digital Radio Communication Systems GHz and GHz • Any narrow band application within 21 GHz • GHz collision avoidance • Front-end gain stage Absolute Maximum Ratings [1] Symbol Parameters/Conditions Units Min. VD1, VD2 VG1, VG2 ID1 ID2 Pin Tch Tb Tstg Tmax Drain Supply Voltage Gate Supply Voltage Drain Supply Current Drain Supply Current RF Input Power Channel Temperature Operating Backside Temperature Storage Temperature Max. Assembly Temp 60 sec max Notes Absolute maximum ratings for continuous operation unless otherwise noted. Max. 8 2 35 15 +150 +140 +165 +300 AMMC-5023 DC Specifications/Physical Properties[1] Symbol Parameters and Test Conditions Units Min. Typ. Max. VD1, VD2 VG1, VG2 ID1, ID2 ID1+ID2 Recommended Drain Supply Voltage Gate Supply Voltage[2] VD1 max , VD2 max Input and Output Stage Drain Supply Current VG1 = VG2 = Open, VD1 = VD2 = 5 V Total Drain Supply Current VG1 = VG2 = Open, VD1 = VD2 = 5 V Thermal Resistance[3] Backside temperature, Tb = 25°C °C/W Backside ambient operating temperature TA = 25°C unless otherwise noted. Open circuit voltage at VG1 and VG2 when VD1 and VD2 are 5 Volts. Channel-to-backside Thermal Resistance = 66°C/W at Tchannel Tc = 150°C as measured using the liquid crystal method. Thermal Resistance at backside temperature Tb = 25°C calculated from measured data. RF Specifications[4] VG1 = VG2 = Open, VD1 = VD2 = 5V, ID1 + ID2 = 28 mA, Zin = Z0 = 50Ω Symbol Parameters and Test Conditions Units GHz Min. Typ. Max. GHz Min. Typ. Max. \|S21\|2 \|S21\|2 RLin RLout \|S12\|2 P-1dB Small-signal Gain Small-signal Gain Flatness Input Return Loss Output Return Loss Isolation Output Power 1 dB Gain Compression f = 23 GHz 19 25 17 43 10 Psat Saturated Output Power 3 dB Gain Compression OIP3 Output 3rd Order Intercept Point, GHz Rfin1 = Rfin2 = -20 dBm, = 2 MHz GHz Ordering Information AMMC-5023-W10 = 10 devices per tray AMMC-5023-W50 = 50 devices per tray VG2 1235 VD2 1555 RF OUTPUT 300 VG2 Y-axis 105 0 1880 For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright 2005-2008 Avago Technologies Limited. All rights reserved. Obsoletes 5989-3930EN AV02-1313EN - May 29, 2008

PDF Datasheet Preview

AMMC-5023
23 GHz Low Noise Amplifier GHz

Data Sheet

Chip Size Chip Size Tolerance Chip Thickness Pad Dimensions:
1880 x 600 µm 74 x mils ±10 µm mils 100 ± 10 µm 4 ± mils 80 x 80 µm x mils , or larger

Avago’s AMMC-5023 is a high gain, low noise amplifier that operates from 21 GHz to over 30 GHz. By eliminating the complex tuning and assembly processes typically required by hybrid discrete-FET amplifiers, the AMMC5023 is a cost-effective alternative in both GHz and GHz communications receivers. The device has good input and output match to 50 Ohm and is unconditionally stable to more than 40 GHz. The backside of the chip is both RF and DC ground. This helps simplify the assembly process and reduces assembly related performance variations and costs. It is fabricated in a PHEMT process to provide exceptional noise and gain performance. For improved reliability and moisture protection, the die is passivated at the active areas.

Features
• Frequency range GHz
• High gain 23 dB
• Low noise figure dB
• Input and output return loss >10 dB
• Single supply bias 5 volts, 28 mA
• Optional bias adjust

Applications
• Digital Radio Communication Systems GHz
and GHz
• Any narrow band application within 21 GHz
• GHz collision avoidance
• Front-end gain stage

Absolute Maximum Ratings [1]

Symbol Parameters/Conditions

Units

Min.

VD1, VD2 VG1, VG2 ID1 ID2 Pin Tch Tb Tstg Tmax

Drain Supply Voltage Gate Supply Voltage Drain Supply Current Drain Supply Current RF Input Power Channel Temperature Operating Backside Temperature Storage Temperature Max. Assembly Temp 60 sec max

Notes Absolute maximum ratings for continuous operation unless otherwise noted.

Max. 8 2 35 15 +150 +140 +165 +300

AMMC-5023 DC Specifications/Physical Properties[1]

Symbol Parameters and Test Conditions

Units Min. Typ. Max.

VD1, VD2 VG1, VG2 ID1, ID2 ID1+ID2

Recommended Drain Supply Voltage

Gate Supply Voltage[2] VD1 max , VD2 max Input and Output Stage Drain Supply Current VG1 = VG2 = Open, VD1 = VD2 = 5 V Total Drain Supply Current VG1 = VG2 = Open, VD1 = VD2 = 5 V Thermal Resistance[3] Backside temperature, Tb = 25°C
°C/W

Backside ambient operating temperature TA = 25°C unless otherwise noted. Open circuit voltage at VG1 and VG2 when VD1 and VD2 are 5 Volts. Channel-to-backside Thermal Resistance = 66°C/W at Tchannel Tc = 150°C as measured using the liquid crystal method. Thermal Resistance
at backside temperature Tb = 25°C calculated from measured data.

RF Specifications[4]

VG1 = VG2 = Open, VD1 = VD2 = 5V, ID1 + ID2 = 28 mA, Zin = Z0 = 50Ω

Symbol Parameters and Test Conditions

Units

GHz Min. Typ. Max.

GHz Min. Typ. Max.
|S21|2 |S21|2 RLin RLout |S12|2 P-1dB

Small-signal Gain Small-signal Gain Flatness Input Return Loss Output Return Loss Isolation Output Power 1 dB Gain Compression f = 23 GHz
19 25 17 43 10

Psat

Saturated Output Power
3 dB Gain Compression

OIP3

Output 3rd Order Intercept Point, GHz

Rfin1 = Rfin2 = -20 dBm, = 2 MHz GHz
Ordering Information AMMC-5023-W10 = 10 devices per tray AMMC-5023-W50 = 50 devices per tray

VG2 1235

VD2 1555

RF OUTPUT 300

VG2 Y-axis 105 0
1880

For product information and a complete list of distributors, please go to our web site:

Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries. Data subject to change. Copyright 2005-2008 Avago Technologies Limited. All rights reserved. Obsoletes 5989-3930EN AV02-1313EN - May 29, 2008

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AMMC-5023-W10 Datasheet file may be downloaded here without warranties.

Datasheet ID: AMMC-5023-W10 520108