ATP AW24P64F8BLK0M
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AW24P64F8BLK0M (pdf) |
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Electronics, Inc. 2590 North First Street, San Jose, CA 95131, U.S.A. Tel 408-732-5000 Fax 408-732-5055 ATP AW24P64F8BLK0M 8GB DDR3-1600 UNBUFFERED NON-ECC SODIMM DESCRIPTION The ATP AW24P64F8BLK0M is a high performance 8GB DDR3-1600 Unbuffered NON-ECC SODIMM SDRAM memory module. It is organized as 1024M x 64 in a 204-pin Small Outline Dual-In-Line Memory Module SODIMM package. The module utilizes sixteen 512Mx8 DDR3 SDRAMs in FBGA package. The module consists of a 256-byte serial EEPROM, which contains the module configuration information. KEY FEATURES • High Density 8GB 1024M x 64 • DIMM Rank 2 Ranks • Cycle Time 1.25ns 800MHz • CAS Latency 11 • Power supply 1.35V 1.283V~1.45V Backward compatible to 1.5V ±0.075V • Internal self calibration through ZQ • Burst lengths 8 • Auto & Self refresh • Asynchronous Reset • Minimum Thickness of Golden Finger 30 Micro-inch • refresh interval at lower than TCASE 85°C, refresh interval at 85°C < TCASE < 95 °C • Dynamic On Die Termination • Fly-by topology • PCB Height inches • RoHS compliant Part No. AW24P64F8BLK0M Max Freq 800MHz x2 Interface SSTL_15 PIN DESCRIPTION Pin Name A0~A9, A11~A15 A10/AP BA0~BA2 Address Inputs Address Input/Auto precharge SDRAM Bank Address CAS CK0~CK1 CK0 ~ CK1 CKE0,CKE1 DM0~DM7 DQ0~DQ63 DQS0~DQS7 DQS0 ~ DQS7 VREFDQ VREFCA A12/ BC VTT Column Address Strobe Clock Inputs, positive line Clock Inputs, negative line Clock Enables Data Masks Data Input/Output Data strobes Data strobes, negative line Input/Output Reference Address Input/Burst chop Termination voltage Pin Name ODT0,ODT1 RAS CS0 , CS1 SA0~SA1 SCL SDA VDD VDDSPD VSS RESET WE TEST On die termination Row Address Strobe Chip Selects SPD address Serial Presence Detect SPD Clock Input SPD Data Input/Output Core Power SPD Power Ground This signal resets the DDR3 SDRAM Write Enable Logic Analyzer specific test pin No Connect Your Ultimate Memory Solution! Page 1 of 7 ATP AW24P64F8BLK0M PIN ASSIGNMENT 13 15 17 19 21 23 25 27 |
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