AL48P72L8BNK0M

AL48P72L8BNK0M Datasheet

ATP AL48P72L8BNK0M

Part	Datasheet
AL48P72L8BNK0M	AL48P72L8BNK0M (pdf)

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Electronics, Inc. 2590 North First Street, San Jose, CA 95131, U.S.A. Tel 408-732-5000 Fax 408-732-5055 ATP AL48P72L8BNK0M 16GB DDR3-1600 REGISTERED ECC DIMM DESCRIPTION The ATP AL48P72L8BNK0M is a high performance 16GB DDR3-1600 Registered ECC SDRAM memory module. It is organized as 2048M x 72 in a 240-pin Dual-In-Line Memory Module DIMM package. The module utilizes eighteen 1024Mx8 DDR3 SDRAMs in FBGA package. The module consists of a 256-byte serial EEPROM, which contains the module configuration information. KEY FEATURES • High Density 16GB 2048M x 72 • DIMM Rank 2 Ranks • Cycle Time 1.25ns 800MHz • CAS Latency 11 • Power supply 1.35V 1.28V~1.45V Backward compatible to 1.5V ±0.075V • Internal self calibration through ZQ • Burst lengths 8 • On-board I2C temperature sensor with integrated SPD EEPROM • Auto & Self refresh • Asynchronous Reset • Minimum Thickness of Golden Finger 30 Micro-inch • refresh interval at lower than TCASE 85°C, refresh interval at 85°C < TCASE < 95 °C • Support address and command signals parity function • Dynamic On Die Termination • Fly-by topology • PCB Height inches Very Low Profile • RoHS compliant Part No. AL48P72L8BNK0M Max Freq 800MHz x2 Interface SSTL_15 PIN DESCRIPTION Pin Name A0~A9, A11~A15 A10/AP BA0~BA2 CAS CB0~CB7 CK0 Address Inputs Address Input/Auto precharge SDRAM Bank Address Column Address Strobe Data check bits Input/Output Clock Inputs, positive line CK0 CKE0, CKE1 DM0~DM8 Event DQ0~DQ63 DQS0~DQS8 DQS0 ~ DQS8 TDQS9~TDQS17 TDQS9 ~ TDQS17 Err_Out Clock Inputs, negative line Clock Enables Data Masks Temperature sensor Event output Data Input/Output Data strobes Data strobes, negative line Termination Data Strobe Termination Data Strobe, negative line Parity error found in the Address and Control bus PIN ASSIGNMENT Pin Name ODT0, ODT1 Par_In RESET WE CS0 , CS1 SA0~SA2 SCL SDA TEST VDD VDDQ ,VDDSPD VREFDQ ,VREFCA VSS NC RFU VTT On die termination Parity bit for the Address and Control bus Row Address Strobe Register and PLL control pin Write Enable Chip Selects

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Electronics, Inc.
2590 North First Street, San Jose, CA 95131, U.S.A.

Tel 408-732-5000 Fax 408-732-5055

ATP AL48P72L8BNK0M
16GB DDR3-1600 REGISTERED ECC DIMM

DESCRIPTION The ATP AL48P72L8BNK0M is a high performance 16GB DDR3-1600 Registered ECC SDRAM memory module. It is organized as 2048M x 72 in a 240-pin Dual-In-Line Memory Module DIMM package. The module utilizes eighteen 1024Mx8 DDR3 SDRAMs in FBGA package. The module consists of a 256-byte serial EEPROM, which contains the module configuration information.

KEY FEATURES
• High Density 16GB 2048M x 72
• DIMM Rank 2 Ranks
• Cycle Time 1.25ns 800MHz
• CAS Latency 11
• Power supply 1.35V 1.28V~1.45V

Backward compatible to 1.5V ±0.075V
• Internal self calibration through ZQ
• Burst lengths 8
• On-board I2C temperature sensor with
integrated SPD EEPROM
• Auto & Self refresh
• Asynchronous Reset
• Minimum Thickness of Golden Finger 30 Micro-inch
• refresh interval at lower than TCASE 85°C, refresh interval at 85°C < TCASE < 95 °C
• Support address and command signals parity function
• Dynamic On Die Termination
• Fly-by topology
• PCB Height inches Very Low Profile
• RoHS compliant

Part No. AL48P72L8BNK0M

Max Freq 800MHz x2

Interface SSTL_15

PIN DESCRIPTION

Pin Name

A0~A9, A11~A15 A10/AP BA0~BA2

CAS CB0~CB7 CK0

Address Inputs Address Input/Auto precharge SDRAM Bank Address

Column Address Strobe

Data check bits Input/Output Clock Inputs, positive line

CK0 CKE0, CKE1 DM0~DM8 Event DQ0~DQ63 DQS0~DQS8

DQS0 ~ DQS8 TDQS9~TDQS17 TDQS9 ~ TDQS17

Err_Out

Clock Inputs, negative line

Clock Enables Data Masks Temperature sensor Event output Data Input/Output Data strobes Data strobes, negative line

Termination Data Strobe Termination Data Strobe, negative line

Parity error found in the Address and Control bus

PIN ASSIGNMENT

Pin Name

ODT0, ODT1 Par_In

RESET

WE CS0 , CS1 SA0~SA2

SCL SDA TEST VDD VDDQ ,VDDSPD VREFDQ ,VREFCA

VSS NC RFU VTT

On die termination Parity bit for the Address and Control bus Row Address Strobe

Register and PLL control pin

Write Enable Chip Selects

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Datasheet ID: AL48P72L8BNK0M 519543