S25FL256LDPNFN010

S25FL256LDPNFN010 Datasheet

S25FL256L

Part	Datasheet
S25FL256LDPNFN010	S25FL256LDPNFN010 (pdf)

Related Parts	Information
S25FL256LDPBHN033	S25FL256LDPBHN033
S25FL256LDPNFN013	S25FL256LDPNFN013
S25FL256LAGMFN003	S25FL256LAGMFN003
S25FL256LDPMFN003	S25FL256LDPMFN003
S25FL256LDPBHN023	S25FL256LDPBHN023
S25FL256LAGNFN013	S25FL256LAGNFN013
S25FL256LAGBHN033	S25FL256LAGBHN033
S25FL256LAGBHN023	S25FL256LAGBHN023
S25FL256LAGBHN030	S25FL256LAGBHN030
S25FL256LAGBHN020	S25FL256LAGBHN020
S25FL256LAGNFN010	S25FL256LAGNFN010
S25FL256LDPBHN020	S25FL256LDPBHN020
S25FL256LDPBHN030	S25FL256LDPBHN030
S25FL256LDPMFN000	S25FL256LDPMFN000
S25FL256LAGMFN000	S25FL256LAGMFN000
S25FL256LDPMFN001	S25FL256LDPMFN001
S25FL256LAGMFN001	S25FL256LAGMFN001
S25FL256LDPNFN011	S25FL256LDPNFN011
S25FL256LAGNFN011	S25FL256LAGNFN011

PDF Datasheet Preview
ADVANCE S25FL256L 256 Mbit 32 Mbyte V FL-L Flash Memory Serial Peripheral Interface SPI with Multi-I/O Clock polarity and phase modes 0 and 3 Double Data Rate DDR option Quad peripheral Interface QPI option Extended Addressing 24- or 32-bit address options Serial Command subset and footprint compatible with S25FL-A, S25FL1-K, S25FL-P, S25FL-S and S25FS-S SPI families Multi I/O Command subset and footprint compatible with S25FL-P, S25FL-S and S25FS-S SPI families Read Commands Normal, Fast, Dual I/O, Quad I/O, DualO, QuadO, DDR Quad I/O. Modes Burst Wrap, Continuous XIP , QPI Serial Flash Discoverable Parameters SFDP for configuration information. Program Architecture 256 Bytes Page Programming buffer3.0 V FL-L Flash Memory Program suspend and resume Erase Architecture Uniform 4KB Sector Erase Uniform 32KB Half Block Erase Uniform 64KB Block Erase Chip erase suspend and resume 100,000 Program-Erase Cycles, min 20 Year Data Retention, typical Security features Status and Configuration Register Protection Four Security Regions of 256 bytes each outside the main Flash array Legacy Block Protection Block range Individual and Region Protection Individual Block Lock Volatile individual Sector/Block Pointer Region Non-Volatile Sector/Block range Power Supply Lock-down, Password, or Permanent protection of Security Regions 2 and 3 and Pointer Region Technology 65 nm Floating Gate Technology Single Supply Voltage with CMOS I/O V to V Temperature Range Industrial to +85°C Industrial Plus to +105°C Extended to +125°C Packages all Pb-free WSON 6 8 mm WNH008 16-pin SOIC 300 mil SO3016 BGA-24 6 8 mm 5 ball FAB024 footprint 4 6 ball FAC024 footprint Block Diagram SCK SI/IO0 SO/IO1 I/O WP#/IO2 RESET#/IO3 RESET# Control Logic X Decoders Memory Array Y Decoders Data Latch Data Path • San Jose, CA 95134-1709 • 408-943-2600 ADVANCE Performance Summary Maximum Read Rates SDR Read Fast Read Dual Read Quad Read Command Maximum Read Rates DDR DDR Quad Read Command Typical Program and Erase Rates Page Programming 4 KBytes Sector Erase 32 KBytes Half Block Erase 64 KBytes Block Erase Operation Typical Current Consumption, to +85°C Fast Read 5MHz Fast Read 10 MHz Fast Read 20 MHz Fast Read 50 MHz Fast Read 108 MHz Fast Read 133 MHz Quad I/O / QPI Read 108 MHz Quad I/O / QPI Read 133 MHz Quad I/O / QPI DDR Read 33MHz Quad I/O / QPI DDR Read 66MHz Program Erase Standby SPI Standby QPI Deep Power Down Ordering Information 141 Ordering Part 141 Glossary Document 144 Page 3 of 145 ADVANCE S25FL256L FL-L Family Overview The Cypress FL-L Family devices are Flash non-volatile memory products using Floating Gate technology 65 nm process lithography The FL-L family connects to a host system via a Serial Peripheral Interface SPI . Traditional SPI single bit serial input and output Single I/O or SIO is supported as well as optional two bit Dual I/O or DIO and four bit wide Quad I/O QIO and Quad Peripheral Interface QPI commands. In addition, there are Double Data Rate DDR read commands for QIO and QPI that transfer address and read data on both edges of the clock. The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block, 64KB block, or entire chip erase. By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically. The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or embedded applications. Provides an ideal storage solution for systems with limited space, signal connections, and power. These memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM, executing code directly XIP , and storing re-programmable data. Page 4 of 145 ADVANCE S25FL256L Migration Notes Features Comparison The FL-L family is command subset and footprint compatible with prior generation FL-S, FL1-K and FL-P families. Table Cypress SPI Families Comparison Parameter Technology Node Architecture Release Date Density Bus Width Supply Voltage Normal Read Speed Fast Read Speed Dual Read Speed Quad Read Speed Quad Read Speed DDR Program Buffer Size Erase Sector/Block Size Parameter Sector Size Sector / Block Erase Rate typ. Page Programming Rate typ. Security Region / OTP Individual and Region Protection or Advanced Sector Protection Erase Suspend/Resume Program Suspend/Resume Operating Temperature FL-L 65nm Floating Gate 256Mb x1, x2, x4 V - V 6MB/s 50MHz 16.5MB/s 133MHz 33MB/s 133MHz 66MB/s 133MHz 66MB/s 66MHz 256B 4KB / 32KB / 64KB 80 KB/s 4KB 168 KB/s 32KB 237KB/s 64KB 854KB/s 256B 1024B Yes to +85°C to +105°C 40°C to +125°C FL-S 65nm Eclipse In Production 128Mb - 1Gb x1, x2, x4 V - V / V - V VIO 6MB/s 50MHz 17MB/s 133MHz 26MB/s 104MHz 52MB/s 104MHz 80MB/s 80MHz 256B / 512B 64KB / 256KB 4KB option 500 KB/s MB/s 256B MB/s 512B 1024B to +85°C to +105°C FL1-K 90nm Floating Gate In Production 4Mb - 64Mb x1, x2, x4 V - V 6MB/s 50MHz 13MB/s 108MHz 26MB/s 108MHz 52MB/s 108MHz 256B 4KB / 64KB 136 KB/s 4KB 437 KB/s 64KB 365 KB/s 768B 3 256B Ordering Information Ordering Part Number The ordering part number is formed by a valid combination of the following: S25FL 256 L AG M F I 00 1 Packing Type 0 = Tray 1 = Tube 3 = 13” Tape and Reel Model Number Additional Ordering Options 00 = SOIC16 footprint 300 mil 01 = 8-contact WSON footprint 02 = 5 x 5 ball BGA footprint 03 = 4 x 6 ball BGA footprint Temperature Range I = Industrial to +85°C V = Industrial Plus to +105°C N = Extended to +125°C Package Materials F = Lead Pb -free H = L ow-Halogen, Lead Pb -free Package Type M = 16-pin SOIC N = 8-contact WSON 6 x 8 mm B = 24-ball BGA 6 x 8 mm package, mm pitch Speed AG = 133 MHz DP = 66 MHz DDR Device Technology L = µm Floating Gate Process Technology Density 256 = 256 Mb Device Family S25FL Cypress Memory Volt-only, SPI Flash Memory S25FL256L Page 141 of 145 ADVANCE S25FL256L Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations. Table General Market Valid OPN Combinations Valid Combinations General Market Base Ordering Part Number Speed Option Package and Temperature Model Number Packing Type MFI, MFV, MFN 0, 1, 3 NFI, NFV, NFN 0, 1, 3 S25FL256L BHI, BHV, BHN MFI, MFV, MFN 02, 03 00 0, 3 0, 1, 3 NFI, NFV, NFN 0, 1, 3 BHI, BHV, BHN 02, 03 Package Marking Base + A + Temp + F + Model Number Base + A + Temp + F + Model Number Base + A + Temp + H + Model Number Base + A + Temp + F + Model Number Base + A + Temp + F + Model Number Base + A + Temp + H + Model Number Page 142 of 145 ADVANCE S25FL256L Glossary Binary Coded Decimal. A value in which each 4 bit nibble represents a decimal numeral. Command All information transferred between the host system and memory during one period while CS# is low. This includes the instruction sometimes called an operation code or opcode and any required address, mode bits, latency cycles, or data. Dual Die Package = Two die stacked within the same package to increase the memory capacity of a single package. Often also referred to as a Multi-Chip Package MCP . Double Data Rate = When input and output are latched on every edge of SCK. Flash The name for a type of Electrical Erase Programmable Read Only Memory EEPROM that erases large blocks of memory bits in parallel, making the erase operation much faster than early EEPROM. High Instruction A signal voltage level VIH or a logic level representing a binary one The 8 bit code indicating the function to be performed by a command sometimes called an operation code or opcode . The instruction is always the first 8 bits transferred from host system to the memory in any command. Low LSB A signal voltage level VIL or a logic level representing a binary zero Least Significant Bit = Generally the right most bit, with the lowest order of magnitude value, within a group of bits of a register or data value. Most Significant Bit = Generally the left most bit, with the highest order of magnitude value, within a group of bits of a register or data value. Not Applicable. A value is not relevant to situation described. Non-Volatile No power is needed to maintain data stored in the memory. Ordering Part Number = The alphanumeric string specifying the memory device type, density, package, factory non-volatile configuration, etc. used to select the desired device. Quad Peripheral Interface 256 Byte length and aligned group of data. Printed Circuit Board Register Bit References In the format Register_name[bit_number] or Register_name[bit_range_MSB bit_range_LSB] Sector Erase unit size depending on device model and sector location this may be 4KBytes, 32KBytes or 64KBytes Single Data Rate = When input is latched on the rising edge and output on the falling edge of SCK. Write An operation that changes data within volatile or non-volatile registers bits or non-volatile Flash memory. When changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data is done, as part of the operation, such that the non-volatile data is modified by the write operation, in the same way that volatile data is modified as a single operation. The non-volatile data appears to the host system to be updated by the single write command, without the need for separate commands for erase and reprogram of adjacent, but unaffected data. Page 143 of 145 ADVANCE S25FL256L Document History Document Title S25FL256L 256 Mbit 32 Mbyte V FL-L Flash Memory V FL-L Flash Memory Document Number 002-00124 ECN No. 4905743 Orig. of Change BWHA Submission Date 09/18/2015 Initial release Description of Change 5147318 BWHA 02/22/2016 DC Characteristics Industrial, Industrial Plus and Extended tables changed ISB Max value SDR AC Characteristics table changed Min values for tCH and tCL Embedded Algorithm Performance Tables changed value for tPP Max Registers added sentences When volatile register bits are written, only the volatile version of the register has the appropriate bits updated. When either a non-volatile or volatile register is read, the volatile version of the register is delivered. Page 144 of 145 ADVANCE S25FL256L Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Clocks & Buffers cypress.com/go/clocks cypress.com/go/interface Lighting & Power Control............ cypress.com/go/powerpsoc cypress.com/go/memory PSoC Touch Sensing cypress.com/go/touch USB Wireless/RF cypress.com/go/wireless Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 4 \| PSoC 5LP Cypress Developer Community \| Forums \| Blogs \| Video \| Training Technical Support cypress.com/go/support Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.

PDF Datasheet Preview

ADVANCE

S25FL256L
256 Mbit 32 Mbyte V FL-L Flash Memory

Serial Peripheral Interface SPI with Multi-I/O Clock polarity and phase modes 0 and 3 Double Data Rate DDR option Quad peripheral Interface QPI option Extended Addressing 24- or 32-bit address options Serial Command subset and footprint compatible with S25FL-A, S25FL1-K, S25FL-P, S25FL-S and S25FS-S SPI families Multi I/O Command subset and footprint compatible with S25FL-P, S25FL-S and S25FS-S SPI families

Read Commands Normal, Fast, Dual I/O, Quad I/O, DualO, QuadO, DDR Quad I/O. Modes Burst Wrap, Continuous XIP , QPI Serial Flash Discoverable Parameters SFDP for configuration information.

Program Architecture 256 Bytes Page Programming buffer3.0 V FL-L Flash Memory Program suspend and resume

Erase Architecture Uniform 4KB Sector Erase Uniform 32KB Half Block Erase Uniform 64KB Block Erase Chip erase suspend and resume
100,000 Program-Erase Cycles, min
20 Year Data Retention, typical Security features

Status and Configuration Register Protection Four Security Regions of 256 bytes each outside the main Flash array Legacy Block Protection Block range Individual and Region Protection

Individual Block Lock Volatile individual Sector/Block Pointer Region Non-Volatile Sector/Block range Power Supply Lock-down, Password, or Permanent protection of

Security Regions 2 and 3 and Pointer Region Technology
65 nm Floating Gate Technology Single Supply Voltage with CMOS I/O

V to V Temperature Range

Industrial to +85°C Industrial Plus to +105°C

Extended to +125°C Packages all Pb-free

WSON 6 8 mm WNH008 16-pin SOIC 300 mil SO3016 BGA-24 6 8 mm
5 ball FAB024 footprint 4 6 ball FAC024 footprint

Block Diagram

SCK SI/IO0

SO/IO1 I/O

WP#/IO2 RESET#/IO3

RESET#

Control Logic

X Decoders

Memory Array Y Decoders Data Latch

Data Path
• San Jose, CA 95134-1709
• 408-943-2600

ADVANCE

Performance Summary

Maximum Read Rates SDR

Read Fast Read Dual Read Quad Read

Command

Maximum Read Rates DDR

DDR Quad Read

Command

Typical Program and Erase Rates

Page Programming 4 KBytes Sector Erase 32 KBytes Half Block Erase 64 KBytes Block Erase

Operation

Typical Current Consumption, to +85°C

Fast Read 5MHz Fast Read 10 MHz Fast Read 20 MHz Fast Read 50 MHz Fast Read 108 MHz Fast Read 133 MHz Quad I/O / QPI Read 108 MHz Quad I/O / QPI Read 133 MHz Quad I/O / QPI DDR Read 33MHz Quad I/O / QPI DDR Read 66MHz Program Erase Standby SPI Standby QPI Deep Power Down
Ordering Information 141 Ordering Part 141

Glossary

Document 144

Page 3 of 145

ADVANCE

S25FL256L

FL-L Family Overview

The Cypress FL-L Family devices are Flash non-volatile memory products using Floating Gate technology 65 nm process lithography

The FL-L family connects to a host system via a Serial Peripheral Interface SPI . Traditional SPI single bit serial input and output Single I/O or SIO is supported as well as optional two bit Dual I/O or DIO and four bit wide Quad I/O QIO and Quad Peripheral Interface QPI commands. In addition, there are Double Data Rate DDR read commands for QIO and QPI that transfer address and read data on both edges of the clock.

The architecture features a Page Programming Buffer that allows up to 256-bytes to be programmed in one operation and provides individual 4KB sector, 32KB half block, 64KB block, or entire chip erase.

By using FL-L family devices at the higher clock rates supported, with Quad commands, the instruction read transfer rate can match or exceed traditional parallel interface, asynchronous, NOR Flash memories, while reducing signal count dramatically.

The FL-L family products offer high densities coupled with the flexibility and fast performance required by a variety of mobile or embedded applications. Provides an ideal storage solution for systems with limited space, signal connections, and power. These memories offer flexibility and performance well beyond ordinary serial flash devices. They are ideal for code shadowing to RAM, executing code directly XIP , and storing re-programmable data.

Page 4 of 145

ADVANCE

S25FL256L

Migration Notes

Features Comparison

The FL-L family is command subset and footprint compatible with prior generation FL-S, FL1-K and FL-P families.

Table Cypress SPI Families Comparison

Parameter Technology Node Architecture Release Date Density Bus Width Supply Voltage Normal Read Speed Fast Read Speed Dual Read Speed Quad Read Speed Quad Read Speed DDR Program Buffer Size Erase Sector/Block Size Parameter Sector Size

Sector / Block Erase Rate typ.

Page Programming Rate typ.

Security Region / OTP Individual and Region Protection or Advanced Sector Protection Erase Suspend/Resume Program Suspend/Resume

Operating Temperature

FL-L 65nm Floating Gate
256Mb x1, x2, x4 V - V 6MB/s 50MHz 16.5MB/s 133MHz 33MB/s 133MHz 66MB/s 133MHz 66MB/s 66MHz
256B 4KB / 32KB / 64KB
80 KB/s 4KB 168 KB/s 32KB 237KB/s 64KB
854KB/s 256B
1024B

Yes to +85°C to +105°C 40°C to +125°C

FL-S 65nm Eclipse In Production 128Mb - 1Gb x1, x2, x4 V - V / V - V VIO 6MB/s 50MHz 17MB/s 133MHz 26MB/s 104MHz 52MB/s 104MHz 80MB/s 80MHz 256B / 512B 64KB / 256KB 4KB option
500 KB/s

MB/s 256B MB/s 512B
1024B
to +85°C to +105°C

FL1-K 90nm Floating Gate In Production 4Mb - 64Mb x1, x2, x4 V - V 6MB/s 50MHz 13MB/s 108MHz 26MB/s 108MHz 52MB/s 108MHz
256B 4KB / 64KB
136 KB/s 4KB 437 KB/s 64KB
365 KB/s
768B 3 256B
Ordering Information
Ordering Part Number
The ordering part number is formed by a valid combination of the following:

S25FL 256 L AG M F

I 00 1 Packing Type 0 = Tray 1 = Tube 3 = 13” Tape and Reel
Model Number Additional Ordering Options 00 = SOIC16 footprint 300 mil 01 = 8-contact WSON footprint 02 = 5 x 5 ball BGA footprint 03 = 4 x 6 ball BGA footprint

Temperature Range

I = Industrial to +85°C V = Industrial Plus to +105°C N = Extended to +125°C

Package Materials F = Lead Pb -free H = L ow-Halogen, Lead Pb -free

Package Type M = 16-pin SOIC N = 8-contact WSON 6 x 8 mm B = 24-ball BGA 6 x 8 mm package, mm pitch

Speed AG = 133 MHz DP = 66 MHz DDR

Device Technology L = µm Floating Gate Process Technology

Density 256 = 256 Mb

Device Family S25FL Cypress Memory Volt-only, SPI Flash Memory

S25FL256L

Page 141 of 145

ADVANCE

S25FL256L

Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult your local sales office to confirm availability of specific valid combinations and to check on newly released combinations.

Table General Market Valid OPN Combinations

Valid Combinations General Market
Base Ordering Part Number

Speed Option

Package and Temperature

Model Number

Packing Type

MFI, MFV, MFN
0, 1, 3

NFI, NFV, NFN
0, 1, 3

S25FL256L

BHI, BHV, BHN

MFI, MFV, MFN
02, 03 00
0, 3 0, 1, 3

NFI, NFV, NFN
0, 1, 3

BHI, BHV, BHN
02, 03

Package Marking

Base + A + Temp + F + Model Number Base + A + Temp + F + Model Number Base + A + Temp + H + Model Number Base + A + Temp + F + Model Number Base + A + Temp + F + Model Number Base + A + Temp + H + Model Number

Page 142 of 145

ADVANCE

S25FL256L

Glossary

Binary Coded Decimal. A value in which each 4 bit nibble represents a decimal numeral.

Command

All information transferred between the host system and memory during one period while CS# is low. This includes the instruction sometimes called an operation code or opcode and any required address, mode bits, latency cycles, or data.

Dual Die Package = Two die stacked within the same package to increase the memory capacity of a single package. Often also referred to as a Multi-Chip Package MCP .

Double Data Rate = When input and output are latched on every edge of SCK.

Flash

The name for a type of Electrical Erase Programmable Read Only Memory EEPROM that erases large blocks of memory bits in parallel, making the erase operation much faster than early EEPROM.

High Instruction

A signal voltage level VIH or a logic level representing a binary one The 8 bit code indicating the function to be performed by a command sometimes called an operation code or opcode . The instruction is always the first 8 bits transferred from host system to the memory in any command.

Low LSB

A signal voltage level VIL or a logic level representing a binary zero Least Significant Bit = Generally the right most bit, with the lowest order of magnitude value, within a group of bits of a register or data value.

Most Significant Bit = Generally the left most bit, with the highest order of magnitude value, within a group of bits of a register or data value.

Not Applicable. A value is not relevant to situation described.

Non-Volatile

No power is needed to maintain data stored in the memory.
Ordering Part Number = The alphanumeric string specifying the memory device type, density, package, factory non-volatile configuration, etc. used to select the desired device.

Quad Peripheral Interface
256 Byte length and aligned group of data.

Printed Circuit Board

Register Bit References In the format Register_name[bit_number] or Register_name[bit_range_MSB bit_range_LSB]

Sector

Erase unit size depending on device model and sector location this may be 4KBytes, 32KBytes or 64KBytes

Single Data Rate = When input is latched on the rising edge and output on the falling edge of SCK.

Write

An operation that changes data within volatile or non-volatile registers bits or non-volatile Flash memory. When changing non-volatile data, an erase and reprogramming of any unchanged non-volatile data is done, as part of the operation, such that the non-volatile data is modified by the write operation, in the same way that volatile data is modified as a single operation. The non-volatile data appears to the host system to be updated by the single write command, without the need for separate commands for erase and reprogram of adjacent, but unaffected data.

Page 143 of 145

ADVANCE

S25FL256L

Document History

Document Title S25FL256L 256 Mbit 32 Mbyte V FL-L Flash Memory V FL-L Flash Memory Document Number 002-00124

ECN No. 4905743

Orig. of Change

BWHA

Submission Date
09/18/2015 Initial release

Description of Change
5147318 BWHA 02/22/2016 DC Characteristics Industrial, Industrial Plus and Extended tables changed

ISB Max value

SDR AC Characteristics table changed Min values for tCH and tCL

Embedded Algorithm Performance Tables changed value for tPP Max

Registers added sentences When volatile register bits are written, only the
volatile version of the register has the appropriate bits updated.

When either a non-volatile or volatile register is read, the volatile version of the register is delivered.

Page 144 of 145

ADVANCE

S25FL256L

Sales, Solutions, and Legal Information

Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.

Products Clocks & Buffers cypress.com/go/clocks cypress.com/go/interface Lighting & Power Control............ cypress.com/go/powerpsoc cypress.com/go/memory PSoC Touch Sensing cypress.com/go/touch USB Wireless/RF cypress.com/go/wireless

Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP

Cypress Developer Community | Forums | Blogs | Video | Training

Technical Support cypress.com/go/support

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code software and/or firmware is owned by Cypress Semiconductor Corporation Cypress and is protected by and subject to worldwide patent protection United States and foreign , United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.

Disclaimer CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived S25FL256LDPNFN010 Datasheet file may be downloaded here without warranties.

Datasheet ID: S25FL256LDPNFN010 508315