EVAL-AD7676CBZ

EVAL-AD7676CBZ Datasheet


Evaluation Board For AD761x,762x/AD763x

Part Datasheet
EVAL-AD7676CBZ EVAL-AD7676CBZ EVAL-AD7676CBZ (pdf)
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Evaluation Board For AD761x,762x/AD763x

AD764x/AD765x/AD766x/AD767x/AD795x

Preliminary Technical Data

EVAL-AD76XXCBZ

Converter and Evaluation Development EVAL-CED1Z and Control Board EVAL-CONTRL BRDxZ compatibility Versatile analog signal conditioning circuitry On-board reference, clock oscillator and buffers Buffered 14, 16 or 18 bit parallel outputs Buffered serial port interface Ideal for DSP and data acquisition card interfaces Analog and digital prototyping area PC software for control and data analysis
The EVAL-AD76XXCBZ is an evaluation board for the 48 lead AD761X, AD762X, AD763X, AD764X, AD765X, AD766X, AD767X and AD795X 14-bit, 16-bit and 18- bit analog to digital converter ADC family. These low power, successive approximation register SAR architecture ADCs see ordering guide for product list offer very high performance with 100kSPS to 3MSPS throughput rate range with a flexible parallel or serial interface. The evaluation board is designed to demonstrate the ADC's performance and to provide an easy to understand interface for a variety of system applications. A full description of the AD761X, AD762X, AD763X, AD764X, AD765X, AD766X, AD767X and AD795X is available in the

Analog Devices data sheets and should be consulted when utilizing this evaluation board.

The evaluation board is ideal for use with either Analog Devices Converter and Evaluation Development EVAL-CED1Z, CED or Evaluation Control Board EVAL-CONTRL BRDxZ ECB capture boards, or as a stand-alone system. The design offers the flexibility of applying external control signals and is capable of generating conversion results on parallel 14-bit, 16-bit or 18-bit wide buffered outputs.

On-board components include a high precision band gap reference, AD780, ADR431, or ADR435 , reference buffers, a signal conditioning circuit with two op-amps and digital logic.

The EVAL-AD76xxCBZ interfaces to the capture board with a 96-pin DIN connector. A 40-pin IDC connector is used for parallel output, and test points are provided for the serial port. SMB connectors are provided for the low noise analog signal source, and for an externally generated CNVST convert start input.
The term AD76XX-48 is used in this document to represent all the 48 lead PulSAR ADCs listed in the ordering guide. CED is used for the EVAL-CED1Z and ECB is used for the EVALCONTROL BRDxZ capture boards.

External CNVST

Reference/Buffer PulSAR ADC
96-Pin CED/ECB Interface

Analog Inputs

Supplies

Figure Evaluation Board

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

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2007 Analog Devices, Inc. All rights reserved.

EVAL-AD76XXCB

TABLE OF CONTENTS

FEATURES 1 GENERAL DESCRIPTION 1
3 Conversion Control/Master 3 Analog Input 3 Power Supplies and Grounding 3 Using the Eval-AD762X/AD765X/AD766X/ AD767XCBZ as 3 Schematics/PCB 4 Supplying Power for Stand-Alone use 4 Evaluation Board Setting for Bipolar ADC Input Configurations 4

LIST OF FIGURES

Figure Evaluation Board 1 Figure Schematic, Analog 10 Figure Schematic, 11 Figure Schematic, Power 12 Figure Top Side 13 Figure Top Layer 13 Figure Ground Layer 14 Figure Shield Layer 14 Figure Bottom Side Layer 15 Figure Bottom Side Silk-Screen 15 Figure Setup Screen 16 Figure Context Help 17 Figure Histogram Screen 18

LIST OF TABLES

Table CNVST Generation, Analog Input Range....................... 7 Table Jumper 8 Table S16 - Configuration Select Switch Description.............. 8 Table S35 - Configuration Select Switch Description.............. 9

Preliminary Technical Data
Hardware Setup Software Installation Running the Software DC Testing - Histogram AC Testing Decimated AC Testing Serial Programmable Port AD7610, AD7612, AD7631, AD7634, AD7951, Table 5.Test Points Ordering 29

Figure Summary 19 Figure FFT 20 Figure 16 21 Figure 17 .Decimated 22 Figure Setup 23 Figure Histogram 24 Figure FFT Screen 25 Figure Time-Domain Screen 26 Figure Decimated Averaging Screen.................................. 27 Figure Serial Programmable Port SPP Screen AD7610/7612/7631/7634/7951/7952 only ............................... 28

Table 5.Test Points Table Bill of Materials for the Connectors

Preliminary Technical Data

OVERVIEW

Figure 1 shows the EVAL-AD76XXCBZ evaluation board. When used in stand-alone mode or in conjunction with the CED/ECB, the gate array, U10, provides the necessary control signals for conversion and buffers the ADC data. The evaluation board is a flexible design that enables the user to choose among many different board configurations, analog signal conditioning, reference, and different modes of conversion data.

CONVERSION CONTROL/MASTER CLOCK

Conversion start CNVST controls the sample rate of the ADC and is the only input needed for conversion all SAR timing is generated internally. CNVST is generated either by the gate array or externally via J3 SMB and setting JP22 in the external EXT position. The evaluation board is factory configured for the CNVST range shown in Table Externally generated CNVST should have very low jitter and sharp edges for the maximum dynamic performance of the part. Since CNVST jitter usually results in poor SNR performance, it is recommended to use the on-board CNVST generation whenever possible.

The master clock MCLK source for the gate array is generated from the CED/ECB capture board or from U12, the 40MHz local oscillator selectable when using the accompanying software. The range for CNVST in Table 1is a ratio generated from this master clock. In stand-alone mode, other clock frequencies can be used to change the gate array generated CNVST by this ratio. However, other timings will be affected namely the slave serial clock SCLK interface. In serial slave mode, SCLK = MCLK.

While the ADC is converting, activity on the BUSY pin turns on the LED, D2. Additionally, the BUSY signal can be monitored test point TP1. Buffered conversion data BD is available at U10 on the output bus BD[0:15] on the 40-pin IDC connector P2, and on the 96-pin connector P3. When operating with the ECB/CED, data is transferred using a 16 bit bus and corresponding word and byte modes selectable with the software. For the 18 bit converters two consecutive 16 bit words are read, however, the ADC data is still read into the gate array as 18 bits. Additionally, BD is updated on the falling edge of BBUSY on P3-C17, and on the rising edge of DBUSY on P2-33. When either parallel or serial reading mode of the ADC is used, data is available on this parallel bus.

When using Serial Mode, serial data is available at T3, T4, T5, and T6 SDOUT, SCLK, SYNC and RDERROR and buffered serial data is output on TP17, TP18, and TP19 SCLK, SYNC, and SDOUT . When using Slave Serial Mode, the external serial clock SCLK applied to the ADC is the MCLK, U12, frequency 40MHz . Refer to the device specific datasheet for full details of the interface modes.

EVAL-AD76XXCBZ

ANALOG INPUT

The analog input amplifier circuitry U6, U7 and discretes allows configuration changes such as positive or negative gain, input range scaling, filtering, addition of a DC component, use of different op-amp and supplies depending on the ADC. The analog input amplifiers are set as unity gain buffers at the factory. The supplies are selectable with solder pads and are set for the ±12V range. Table 1 shows the analog input range for the available evaluation boards.

The default configuration for the single ended SE unipolar ADCs sets U6 at mid-scale from the voltage divider VCM * R6/ R6+R7 and U7 at mid-scale from the voltage divider VCM * R29+R60 for the differential unipolar ADCs.

For the bipolar devices, the input is at 0V mid-scale . This allows a transition noise test histogram without any other equipment. In some applications, it is desired to use a bipolar or wider analog input range, for instance, ± 10V, ± 5V, ± 2.5V, or 0 to -5V. For the AD76XX-48 parts which do not use these input ranges directly, simple modifications of the input driver circuitry can be made without any performance degradation. Refer to the datasheet under the Application Hints section for component values or to application note AN594 on the product web page for other input ranges.

For dynamic performance, an FFT test can be done by applying a very low distortion AC source.

POWER SUPPLIES AND GROUNDING

The evaluation board ground plane is separated into two sections a plane for the digital interface circuitry and an analog plane for the analog input and external reference circuitry. To attain high resolution performance, the board was designed to ensure that all digital ground return paths do not cross the analog ground return paths by connecting the planes together directly under the converter. Power is supplied to the board through P3 when using with the EVAL-CONTROL-BRDX

USING THE EVAL-AD762X/AD765X/AD766X/ AD767XCBZ AS STAND-ALONE

Using the evaluation board as stand-alone does not require the CED/ECB nor does it require use of the accompanied software. When the CONTROL input to the gate array is LOW, which is pulled down by default, the gate array provides the necessary signals for conversion and buffers the conversion data.

In stand-alone mode, the gate arrays flexible logic buffers the ADC data according to the read data mode configuration word or byte . In parallel reading mode the board is configured for continuous reading since CS and RD are always driven LOW by the gate array. Thus, the digital bus is not tri-stated in this mode of operation and BD[0:15] will continuously be updated after a new conversion. BD[0:15] is available on P2 after BUSY goes HIGH. Note that with the 18 bit devices the full 18 bits of data BD[-2:15] are output directly on P2 since the evaluation board

EVAL-AD76XXCBZ

Preliminary Technical Data
is not limited to 16 bit wide transfers in stand-alone operation. When either parallel or serial reading mode, the data is available on this parallel bus. Refer to Figure 3 to obtain the data output pins on P2.

Configuration Switches

The evaluation board is configurable for the different operating modes with 16 positions on the configuration select switches, S16 and S35. A description of each switch setting and jumper position is listed in Figure 3 and the available test points are listed in Table Note that the switches in the ON position define a logic HIGH level pulled up with 10kΩ, and that the switches are active only in stand-alone mode.

For all interface modes, S16 and S35 allows the selection of Warp, Normal or Impulse mode conversions where applicable Binary or 2s complement data output Reading during or after conversion Resetting the ADC power-down Internal Reference and Buffer power-down where applicable

In parallel reading mode, s16 allows the selection of Byte swapping for 8 bit interfacing LSByte with MSByte 18-bit, 16-bit and 8-bit interfacing for 18-bit converters

In serial reading mode, the default settings are Master Read during Conversion Mode using the internal ADC serial clock. Serial data is available at T3, T4, T5 and T6 for SDOUT, SCLK, SYNC and RDERROR respectively. Buffered serial data is output on the three test points TP17, TP18 and TP19 for SCLK, SYNC, and SDOUT respectively.

For serial reading mode, S16 allows the selection of Choice of inverting SCLK and SYNC Choice of using internal or external slave mode SCLK

SCHEMATICS/PCB LAYOUT

The EVAL-AD76XXCBZ is a 4-layer board carefully laid out and tested to demonstrate the specific high accuracy performance of the AD76XX-48 device. Figure 2 to Figure 4 show the schematics of the evaluation board. The printed circuit layouts of the board are given in Figure 5 - Figure Note these layouts are not to scale.

Top side silk-screen - Figure 5 Top side layer - Figure 6 Ground layer - Figure 7 Shield layer - Figure 8 Bottom side layer - Figure 9 Bottom side silk-screen - Figure 10

SUPPLYING POWER FOR STAND-ALONE USE

Power needs to be supplied through the two power supply blocks SJ1 and SJ2. Linear supplies are recommended. SJ1 is the analog supply for the ADC AVDD , front end op amps and reference circuitry. SJ2 is the digital supply for the ADC DVDD, OVDD and gate array. The supplies to the device are
configurable through the power supply jumpers shown in Table In most applications four supplies are required ±12V and +5V for analog, and +5V for digital. On board regulators, where applicable, are used to reduce the operating voltages to the correct levels. The analog and digital supplies can be from the same source however, R27 typically 20Ω is required from AVDD to DVDD. In this configuration, JP9, DVDD selection, should be left open. Furthermore, the OVDD ADC digital output supply may need to be brought up after the analog +5V supply. See datasheet for details.

EVALUATION BOARD SETTING FOR BIPOLAR ADC INPUT CONFIGURATIONS

The AD7610, AD7612, AD7631, AD7634, AD7663, AD7665, AD7671, AD7951 and AD7952 can use both unipolar and bipolar ranges. The available options are +/-10V, +/-5V, +/-2.5V, 0 to 10V, 0 to 5V and 0 to 2.5V depending on the ADC .

For the AD7663, AD7665 and AD7671 the evaluation board is set for the ±5V bipolar input range since these ADCs input ranges are hardware pin strapped. Simple modifications to these evaluation boards can be made to accommodate the different input ranges by changing the INA-IND inputs with the available solder pads.
iCMOS ADCs
ORDERING GUIDE

Evaluation Board Model EVAL-AD7610CBZ EVAL-AD7612CBZ EVAL-AD7621CBZ EVAL-AD7622CBZ EVAL-AD7623CBZ EVAL-AD7631CBZ EVAL-AD7634CBZ EVAL-AD7641CBZ EVAL-AD7643CBZ EVAL-AD7650CBZ EVAL-AD7651CBZ EVAL-AD7652CBZ EVAL-AD7653CBZ EVAL-AD7654CBZ EVAL-AD7655CBZ EVAL-AD7660CBZ EVAL-AD7661CBZ EVAL-AD7663CBZ EVAL-AD7664CBZ EVAL-AD7665CBZ EVAL-AD7666CBZ EVAL-AD7667CBZ EVAL-AD7671CBZ EVAL-AD7674CBZ EVAL-AD7675CBZ EVAL-AD7676CBZ EVAL-AD7677CBZ EVAL-AD7678CBZ EVAL-AD7679CBZ EVAL-AD7951CBZ EVAL-AD7952CBZ EVAL-CED1Z EVAL-CONTROL BRD2Z1 EVAL-CONTROL BRD3Z

Product AD7610ASTZ/ACPZ AD7612ASTZ/ACPZ AD7621ASTZ/ACPZ AD7622BSTZ/BCPZ AD7623ASTZ/ACPZ AD7631ASTZ/ACPZ AD7634ASTZ/ACPZ AD7641BSTZ/BCPZ AD7643BSTZ/BCPZ AD7650ASTZ/ACPZ AD7651ASTZ/ACPZ AD7652ASTZ/ACPZ AD7653ASTZ/ACPZ AD7654ASTZ/ACPZ AD7655ASTZ/ACPZ AD7660ASTZ/ACPZ AD7661ASTZ/ACPZ AD7663ASTZ/ACPZ AD7664ASTZ/ACPZ AD7665ASTZ/ACPZ AD7666ASTZ/ACPZ AD7667ASTZ/ACPZ AD7671ASTZ/ACPZ AD7674ASTZ/ACPZ AD7675ASTZ/ACPZ AD7676ASTZ/ACPZ AD7677ASTZ/ACPZ AD7678ASTZ/ACPZ AD7679ASTZ/ACPZ AD7951ASTZ/ACPZ AD7951ASTZ/ACPZ USB Capture Board Parallel Port Capture Board Parallel Port Capture Board
1 Not in production any longer.

EVAL-AD76XXCBZ

EVAL-AD76XXCBZ NOTES

Preliminary Technical Data
2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

PR07201-0-11/07 PrA
More datasheets: 94 | 2029B | ADUC7030BCPZ-8V | 80289717 | 30-01USOC/S400-A9 | EVAL-AD7678CBZ | EVAL-AD7634CBZ | EVAL-AD7610CBZ | EVAL-AD7667CBZ | EVAL-AD7675CBZ


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Datasheet ID: EVAL-AD7676CBZ 517907