ADSP-2195MBST-140

ADSP-2195MBST-140 Datasheet

DSP Microcomputer ADSP-2195

Part	Datasheet
ADSP-2195MBST-140	ADSP-2195MBST-140 (pdf)

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Preliminary Technical Data DSP Microcomputer ADSP-2195 ADSP-219x DSP CORE FEATURES ns Instruction Cycle Time Internal , for up to 160 MIPS Sustained Performance ADSP-218x Family Code Compatible with the Same Easy -to-Use Algebraic Syntax Single-Cycle Instruction Execution Up to 16M words of Addressable Memory Space with 24 Bits of Addressing Width Dual Purpose Program Memory for Both Instruction and Data Storage Fully Transparent Instruction Cache Allows Dual Operand Fetches in Every Instruction Cycle Unified Memory Space Permits Flexible Address Generation, Using Two Independent DAG Units Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units with Dual 40-bit Accumulators Single-Cycle Context Switch between Two Sets of Computational and DAG Registers Parallel Execution of Computation and Memory Instructions Pipelined Architecture Supports Efficient Code Execution at Speeds up to 160 MIPS Register File Computations with All Nonconditional, Nonparallel Computational Instructions Powerful Program Sequencer Provides Zero-Overhead Looping and Conditional Instruction Execution Architectural Enhancements for Compiled C Code Efficiency '63 &25 FUNCTIONAL BLOCK DIAGRAM ,17 55837 7,0 5 6 * 6 0 02 5< 7:2 ,1' 3 1' 17 5 6 5 6 6 4 8 1& 5 30 %86 '0 %86 %86 &211 &7 30 %86 '0 %86 5 * ,67 5 ,13 87 5 * ,6 7 56 08/7 5 68/7 5 * ,6 7 56 6 + , 7 5 5 *,67 56 0 025< &21752/ %8 56 &21752// 5 7 67 0 8/ 7,2 1 3257 0 025< ,17 5 352& 6625 +267 3257 32576 UART and Transmit Timing 50 JTAG Test And Emulation Port Timing 51 Output Drive Currents 52 Power Dissipation 52 Test Conditions 54 Output Disable Time 54 Output Enable Time 54 Example System Hold Time Calculation 55 Capacitive Loading 55 Environmental Conditions 55 Thermal Characteristics 55 ADSP-2195 144-Lead LQFP Pinout 58 ADSP-2195 144-Lead Mini-BGA Pinout 67 Ordering Guide 68 This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. ADSP-2195 For current information contact Analog Devices at 800/262-5643 September 2001 General Note This data sheet provides preliminary information for the ADSP-2195 Digital Signal Processor. GENERAL DESCRIPTION The ADSP-2195 DSP is a single-chip microcomputer optimized for digital signal processing DSP and other high speed numeric processing applications. The ADSP-2195 combines the ADSP-219x family base architecture three computational units, two data address generators, and a program sequencer with three serial ports, two SPI-compatible ports, one UART port, a DMA controller, three programmable timers, general-purpose Programmable Flag pins, extensive interrupt capabilities, and on-chip program and data memory spaces. The ADSP-2195 architecture is code-compatible with ADSP-218x family DSPs. Although the architectures are compatible, the ADSP-2195 architecture has a number of enhancements over the ADSP-218x architecture. The enhancements to computational units, data address generators, and program sequencer make the ADSP-2195 more flexible and even easier to program than the ADSP-218x DSPs. Indirect addressing options provide addressing premodify with no update, pre- and post-modify by an immediate 8-bit, two’s-complement value and base address registers for easier implementation of circular buffering. The ADSP-2195 integrates 48K words of on-chip memory configured as 16K words 24-bit of program RAM, 16K words 16-bit of data RAM, and 16K words 24-bit of program ROM. Power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. The ADSP-2195 is available in 144-lead LQFP and mini-BGA packages. Fabricated in a high-speed, low-power, CMOS process, the ADSP-2195 operates with a ns instruction cycle time 160 MIPS . All instructions, except two multiword instructions, can execute in a single DSP cycle. The ADSP-2195’s flexible architecture and comprehensive instruction set support multiple operations in parallel. For example, in one processor cycle, the ADSP-2195 can: • Generate an address for the next instruction fetch • Fetch the next instruction • Perform one or two data moves • Update one or two data address pointers • Perform a computational operation These operations take place while the processor continues to: • Receive and transmit data through two serial ports • Receive and/or transmit data from a Host • Receive or transmit data through the UART • Receive or transmit data over two SPI ports • Access external memory through the external memory interface • Decrement the timers DSP Core Architecture The ADSP-2195 instruction set provides flexible data moves and multifunction one or two data moves with a computation instructions. Every single-word instruction can be executed in a single processor cycle. The ADSP-2195 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. The functional block diagram on page 1 shows the architecture of the ADSP-219x core. It contains three independent computational units the ALU, the multiplier/accumulator MAC , and the shifter. The computational units process 16-bit data from the register file and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, and multiply/subtract operations. The MAC has two 40-bit accumulators, which help with overflow. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control, including multiword and block floating-point representations. Register-usage rules influence placement of input and results within the computational units. For most operations, the computational units’ data registers act as a data register file, permitting any input or result register to provide input to any unit for a computation. For feedback operations, the computational units let the output result of any unit be input to any unit on the next cycle. For conditional or multifunction instructions, there are restrictions on which data registers may provide inputs or receive results from each computational unit. For more information, see the ADSP-219x DSP Instruction Set Reference. A powerful program sequencer controls the flow of instruction execution. The sequencer supports conditional jumps, subroutine calls, and low interrupt overhead. With internal loop counters and loop stacks, the ADSP-2195 executes looped code with zero overhead no explicit jump instructions are required to maintain loops. Two data address generators DAGs provide addresses for simultaneous dual operand fetches from data memory and program memory . Each DAG maintains and updates four 16-bit address pointers. Whenever the pointer is used to access data indirect addressing , it is pre- or post-modified by the value of one of four possible modify registers. A length value and base address may be associated with each pointer to implement automatic modulo addressing for circular buffers. Page registers in the DAGs allow circular addressing This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing. September 2001 For current information contact Analog Devices at 800/262-5643 ADSP-2195 within 64K word boundaries of each of the 256 memory pages, but these buffers may not cross page boundaries. Secondary registers duplicate all the primary registers in the DAGs switching between primary and secondary registers provides a fast context switch. Efficient data transfer in the core is achieved with the use of internal buses: • Program Memory Address PMA Bus • Program Memory Data PMD Bus • Data Memory Address DMA Bus • Data Memory Data DMD Bus ORDERING GUIDE ADSP-2195 Part Number1, 2 Ambient Temperature Range Instruction Rate On-Chip SRAM Operating Voltage ADSP-2195MKST-160X 0ºC to 70ºC 160 MHz 1.3M bit Int./3.3 Ext. V ADSP-2195MBST-140X -40ºC to 85ºC 140 MHz 1.3M bit Int./3.3 Ext. V ADSP-2195MKCA-160X 0ºC to 70ºC 160 MHz 1.3M bit Int./3.3 Ext. V ADSP-2195MBCA-140X -40ºC to 85ºC 1ST = Plastic Thin Quad Flatpack LQFP . 2CA = Mini Ball Grid Array 140 MHz 1.3M bit Int./3.3 Ext. V This information applies to a product under development. Its characteristics and specifications are subject to change with- out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

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Preliminary Technical Data

DSP Microcomputer ADSP-2195

ADSP-219x DSP CORE FEATURES ns Instruction Cycle Time Internal , for up to
160 MIPS Sustained Performance ADSP-218x Family Code Compatible with the Same

Easy -to-Use Algebraic Syntax Single-Cycle Instruction Execution Up to 16M words of Addressable Memory Space with
24 Bits of Addressing Width Dual Purpose Program Memory for Both Instruction and

Data Storage Fully Transparent Instruction Cache Allows Dual

Operand Fetches in Every Instruction Cycle Unified Memory Space Permits Flexible Address

Generation, Using Two Independent DAG Units

Independent ALU, Multiplier/Accumulator, and Barrel Shifter Computational Units with Dual 40-bit Accumulators

Single-Cycle Context Switch between Two Sets of Computational and DAG Registers

Parallel Execution of Computation and Memory Instructions

Pipelined Architecture Supports Efficient Code Execution at Speeds up to 160 MIPS

Register File Computations with All Nonconditional, Nonparallel Computational Instructions

Powerful Program Sequencer Provides Zero-Overhead Looping and Conditional Instruction Execution

Architectural Enhancements for Compiled C Code Efficiency
'63 &25

FUNCTIONAL BLOCK DIAGRAM
,17 55837 7,0 5 6 * 6
0 02 5<
7:2 ,1' 3 1' 17
5 6 5 6
6 4 8 1& 5
30 %86
'0 %86
%86 &211 &7
30 %86 '0 %86
5 * ,67 5
,13 87 5 * ,6 7 56
08/7
5 68/7 5 * ,6 7 56
6 + , 7 5
5 *,67 56 0 025<
&21752/ %8 56
&21752// 5
7 67 0 8/ 7,2 1
3257
0 025< ,17 5
352& 6625
+267 3257
32576
UART and Transmit Timing 50 JTAG Test And Emulation Port Timing 51 Output Drive Currents 52 Power Dissipation 52 Test Conditions 54 Output Disable Time 54 Output Enable Time 54 Example System Hold Time Calculation 55 Capacitive Loading 55 Environmental Conditions 55 Thermal Characteristics 55 ADSP-2195 144-Lead LQFP Pinout 58 ADSP-2195 144-Lead Mini-BGA Pinout 67 Ordering Guide 68

This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

ADSP-2195

For current information contact Analog Devices at 800/262-5643

September 2001

General Note This data sheet provides preliminary information for the ADSP-2195 Digital Signal Processor.

GENERAL DESCRIPTION The ADSP-2195 DSP is a single-chip microcomputer optimized for digital signal processing DSP and other high speed numeric processing applications.

The ADSP-2195 combines the ADSP-219x family base architecture three computational units, two data address generators, and a program sequencer with three serial ports, two SPI-compatible ports, one UART port, a DMA controller, three programmable timers, general-purpose Programmable Flag pins, extensive interrupt capabilities, and on-chip program and data memory spaces.

The ADSP-2195 architecture is code-compatible with ADSP-218x family DSPs. Although the architectures are compatible, the ADSP-2195 architecture has a number of enhancements over the ADSP-218x architecture. The enhancements to computational units, data address generators, and program sequencer make the ADSP-2195 more flexible and even easier to program than the ADSP-218x DSPs.

Indirect addressing options provide addressing premodify with no update, pre- and post-modify by an immediate 8-bit, two’s-complement value and base address registers for easier implementation of circular buffering.

The ADSP-2195 integrates 48K words of on-chip memory configured as 16K words 24-bit of program RAM, 16K words 16-bit of data RAM, and 16K words 24-bit of program ROM. Power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. The ADSP-2195 is available in 144-lead LQFP and mini-BGA packages.

Fabricated in a high-speed, low-power, CMOS process, the ADSP-2195 operates with a ns instruction cycle time 160 MIPS . All instructions, except two multiword instructions, can execute in a single DSP cycle.

The ADSP-2195’s flexible architecture and comprehensive instruction set support multiple operations in parallel. For example, in one processor cycle, the ADSP-2195 can:
• Generate an address for the next instruction fetch
• Fetch the next instruction
• Perform one or two data moves
• Update one or two data address pointers
• Perform a computational operation

These operations take place while the processor continues to:
• Receive and transmit data through two serial ports
• Receive and/or transmit data from a Host
• Receive or transmit data through the UART
• Receive or transmit data over two SPI ports
• Access external memory through the external memory interface
• Decrement the timers

DSP Core Architecture The ADSP-2195 instruction set provides flexible data moves and multifunction one or two data moves with a computation instructions. Every single-word instruction can be executed in a single processor cycle. The ADSP-2195 assembly language uses an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development.

The functional block diagram on page 1 shows the architecture of the ADSP-219x core. It contains three independent computational units the ALU, the multiplier/accumulator MAC , and the shifter. The computational units process 16-bit data from the register file and have provisions to support multiprecision computations. The ALU performs a standard set of arithmetic and logic operations division primitives are also supported. The MAC performs single-cycle multiply, multiply/add, and multiply/subtract operations. The MAC has two 40-bit accumulators, which help with overflow. The shifter performs logical and arithmetic shifts, normalization, denormalization, and derive exponent operations. The shifter can be used to efficiently implement numeric format control, including multiword and block floating-point representations.

Register-usage rules influence placement of input and results within the computational units. For most operations, the computational units’ data registers act as a data register file, permitting any input or result register to provide input to any unit for a computation. For feedback operations, the computational units let the output result of any unit be input to any unit on the next cycle. For conditional or multifunction instructions, there are restrictions on which data registers may provide inputs or receive results from each computational unit. For more information, see the ADSP-219x DSP Instruction Set Reference.

A powerful program sequencer controls the flow of instruction execution. The sequencer supports conditional jumps, subroutine calls, and low interrupt overhead. With internal loop counters and loop stacks, the ADSP-2195 executes looped code with zero overhead no explicit jump instructions are required to maintain loops.

Two data address generators DAGs provide addresses for simultaneous dual operand fetches from data memory and program memory . Each DAG maintains and updates four 16-bit address pointers. Whenever the pointer is used to access data indirect addressing , it is pre- or post-modified by the value of one of four possible modify registers. A length value and base address may be associated with each pointer to implement automatic modulo addressing for circular buffers. Page registers in the DAGs allow circular addressing

This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

September 2001 For current information contact Analog Devices at 800/262-5643

ADSP-2195
within 64K word boundaries of each of the 256 memory pages, but these buffers may not cross page boundaries. Secondary registers duplicate all the primary registers in the DAGs switching between primary and secondary registers provides a fast context switch.

Efficient data transfer in the core is achieved with the use of internal buses:
• Program Memory Address PMA Bus
• Program Memory Data PMD Bus
• Data Memory Address DMA Bus
• Data Memory Data DMD Bus
ORDERING GUIDE

ADSP-2195

Part Number1, 2

Ambient Temperature Range Instruction Rate On-Chip SRAM Operating Voltage

ADSP-2195MKST-160X 0ºC to 70ºC
160 MHz
1.3M bit

Int./3.3 Ext. V

ADSP-2195MBST-140X -40ºC to 85ºC
140 MHz
1.3M bit

Int./3.3 Ext. V

ADSP-2195MKCA-160X 0ºC to 70ºC
160 MHz
1.3M bit

Int./3.3 Ext. V

ADSP-2195MBCA-140X -40ºC to 85ºC
1ST = Plastic Thin Quad Flatpack LQFP . 2CA = Mini Ball Grid Array
140 MHz
1.3M bit

Int./3.3 Ext. V

This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ADSP-2195MBST-140 Datasheet file may be downloaded here without warranties.

Datasheet ID: ADSP-2195MBST-140 517873