ADSP-21065LCCA-240

ADSP-21065LCCA-240 Datasheet

ADSP-21065L

Part	Datasheet
ADSP-21065LCCA-240	ADSP-21065LCCA-240 (pdf)

Related Parts	Information
ADSP-21065LCCAZ240	ADSP-21065LCCAZ240
ADSP-21065LKSZ-240	ADSP-21065LKSZ-240

PDF Datasheet Preview
DSP Microcomputer ADSP-21065L SUMMARY High Performance Signal Computer for Communica- tions, Audio, Automotive, Instrumentation and Industrial Applications Super Harvard Architecture Computer Four Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle 32-Bit Fixed-Point Arithmetic 32-Bit and 40-Bit FloatingPoint Arithmetic 544 Kbits On-Chip SRAM Memory and Integrated I/O Peripheral I2S Support, for Eight Simultaneous Receive and Transmit Channels KEY FEATURES 66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained Performance User-Configurable 544 Kbits On-Chip SRAM Memory Two External Port, DMA Channels and Eight Serial Port, DMA Channels SDRAM Controller for Glueless Interface to Low Cost External Memory 66 MHz 64M Words External Address Range 12 Programmable I/O Pins and Two Timers with Event Capture Options Code-Compatible with ADSP-2106x Family 208-Lead MQFP or 196-Ball Mini-BGA Package Volt Operation Flexible Data Formats and 40-Bit Extended Precision 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE Floating-Point Data Formats 32-Bit Fixed-Point Data Format, Integer and Fractional, with Dual 80-Bit Accumulators Parallel Computations Single-Cycle Multiply and ALU Operations in Parallel with Dual Memory Read/Writes and Instruction Fetch Multiply with Add and Subtract for Accelerated FFT But- terfly Computation 1024-Point Complex FFT Benchmark ms 18,221 Cycles CORE PROCESSOR INSTRUCTION CACHE 32 48 BIT DAG1 DAG2 8 4 32 8 4 24 PROGRAM SEQUENCER 24 PM ADDRESS BUS 32 DM ADDRESS BUS BUS CONNECT 48 PM DATA BUS 40 DM DATA BUS DUAL-PORTED SRAM TWO INDEPENDENT DUAL-PORTED BLOCKS PROCESSOR PORT ADDR DATA ADDR DATA I/O PORT DATA ADDR ADDR DATA BLOCK 0 BLOCK 1 ORDERING GUIDE Instruction Rate 60 MHz 60 MHz 60 MHz 66 MHz 66 MHz 60 MHz On-Chip SRAM 544 Kbit 544 Kbit 544 Kbit 544 Kbit 544 Kbit 544 Kbit Operating Voltage Package Options MQFP Mini-BGA MQFP Mini-BGA Mini-BGA OUTLINE DIMENSIONS 196-Lead Chip Scale Ball Grid Array [CSPBGA] Dimensions shown in millimeters TOP VIEW DETAIL A DETAIL B 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P BOTTOM VIEW MAX BALL COPLANARITY BALL SEATING PLANE DIAMETER DETAIL A DETAIL B NOTES THE ACTUAL POSITION OF THE BALL GRID IS WITHIN OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES. THE ACTUAL POSITION OF EACH BALL IS WITHIN OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID. DIMENSIONS COMPLY WITH JEDEC STANDARD MS-034AAE-1. CENTER DIMENSIONS ARE NOMINAL. Location Edit to GENERAL DESCRIPTION 3 Removal of overbar from DQM Universal Edit to POWER DISSIPATION ADSP-21065L equations above Table III 13 Addition to ORDERING GUIDE 44 Update to OUTLINE DIMENSIONS 41, 44 PRINTED IN U.S.A.

PDF Datasheet Preview

DSP Microcomputer

ADSP-21065L

SUMMARY High Performance Signal Computer for Communica-
tions, Audio, Automotive, Instrumentation and Industrial Applications Super Harvard Architecture Computer Four Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle 32-Bit Fixed-Point Arithmetic 32-Bit and 40-Bit FloatingPoint Arithmetic 544 Kbits On-Chip SRAM Memory and Integrated I/O Peripheral I2S Support, for Eight Simultaneous Receive and Transmit Channels

KEY FEATURES 66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained

Performance User-Configurable 544 Kbits On-Chip SRAM Memory Two External Port, DMA Channels and Eight Serial

Port, DMA Channels

SDRAM Controller for Glueless Interface to Low Cost External Memory 66 MHz
64M Words External Address Range 12 Programmable I/O Pins and Two Timers with Event

Capture Options Code-Compatible with ADSP-2106x Family 208-Lead MQFP or 196-Ball Mini-BGA Package Volt Operation

Flexible Data Formats and 40-Bit Extended Precision 32-Bit Single-Precision and 40-Bit Extended-Precision IEEE

Floating-Point Data Formats 32-Bit Fixed-Point Data Format, Integer and Fractional,
with Dual 80-Bit Accumulators

Parallel Computations Single-Cycle Multiply and ALU Operations in Parallel with

Dual Memory Read/Writes and Instruction Fetch Multiply with Add and Subtract for Accelerated FFT But-
terfly Computation 1024-Point Complex FFT Benchmark ms 18,221

Cycles

CORE PROCESSOR

INSTRUCTION CACHE
32 48 BIT

DAG1

DAG2
8 4 32 8 4 24

PROGRAM SEQUENCER
24 PM ADDRESS BUS
32 DM ADDRESS BUS

BUS CONNECT
48 PM DATA BUS 40 DM DATA BUS

DUAL-PORTED SRAM

TWO INDEPENDENT DUAL-PORTED BLOCKS

PROCESSOR PORT

ADDR

DATA

ADDR

DATA

I/O PORT

DATA

ADDR

ADDR

DATA

BLOCK 0 BLOCK 1
ORDERING GUIDE

Instruction Rate
60 MHz 60 MHz 60 MHz 66 MHz 66 MHz 60 MHz

On-Chip SRAM
544 Kbit 544 Kbit 544 Kbit 544 Kbit 544 Kbit 544 Kbit

Operating Voltage

Package Options

MQFP Mini-BGA MQFP Mini-BGA Mini-BGA

OUTLINE DIMENSIONS
196-Lead Chip Scale Ball Grid Array [CSPBGA]

Dimensions shown in millimeters

TOP VIEW

DETAIL A

DETAIL B
14 13 12 11 10 9 8 7 6 5 4 3 2 1

A B C D E F G H J K L M N P

BOTTOM VIEW

MAX BALL

COPLANARITY

BALL

SEATING PLANE

DIAMETER

DETAIL A

DETAIL B

NOTES THE ACTUAL POSITION OF THE BALL GRID IS WITHIN OF ITS IDEAL POSITION RELATIVE TO THE PACKAGE EDGES.

THE ACTUAL POSITION OF EACH BALL IS WITHIN OF ITS IDEAL POSITION RELATIVE TO THE BALL GRID.

DIMENSIONS COMPLY WITH JEDEC STANDARD MS-034AAE-1.

CENTER DIMENSIONS ARE NOMINAL.

Location

Edit to GENERAL DESCRIPTION 3

Removal of overbar from DQM Universal

Edit to POWER DISSIPATION ADSP-21065L equations above Table III 13
Addition to ORDERING GUIDE 44

Update to OUTLINE DIMENSIONS 41, 44

PRINTED IN U.S.A.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ADSP-21065LCCA-240 Datasheet file may be downloaded here without warranties.

Datasheet ID: ADSP-21065LCCA-240 517872