AD9940BSTZ

AD9940BSTZ Datasheet

High Speed, Correlated Double Sampler with Integrated Timing Driver AD9940

Part	Datasheet
AD9940BSTZ	AD9940BSTZ (pdf)

Related Parts	Information
AD9940BCPZRL	AD9940BCPZRL
AD9940BSTZRL	AD9940BSTZRL
AD9940BCPZ	AD9940BCPZ

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High Speed, Correlated Double Sampler with Integrated Timing Driver AD9940 56 MSPS correlated double sampler CDS with 6 dB gain On-chip horizontal and RG timing driver Single-supply operation V min Precision Timing core with ns resolution at 56 MSPS Low power CMOS 105 mW at V 115 mW at V 48-lead LQFP and 48-lead LFCSP packages Professional HDTV camcorders Professional/high end digital cameras Broadcast cameras Industrial high speed cameras High speed data-acquisition systems The AD9940 is a high speed, correlated double sampler for high speed digital imaging applications. Integrated with a programmable timing driver using the Precision Timing core, the AD9940 features a 56 MHz CDS amplifier with 6 dB of fixed gain, an internal voltage reference supply, and timing control for all the high speed clocks necessary for CCD imaging systems. The Precision Timing core allows adjustment of high speed clocks with a resolution of ns. Output buffers are also included, providing drive strength for PCB traces and direct connection to an image signal processor such as the AD9941. The AD9940 is ideal for applications that need to place the CDS and VGA/ADC circuits on separate PC boards. The fully differential outputs of the AD9940 provide good signal integrity when interfaced with the differential input AD9941. The AD9940 operates from a single V power supply, typically dissipates 105 mW excluding the H/RG drive current , and is packaged in 48-lead LQFP and 48-lead LFCSP packages. CCDIN AD9940 FUNCTIONAL BLOCK DIAGRAM REFT REFB VREF DIFFN DIFFP RG HL H1 TO H4 HORIZONTAL DRIVERS INTERNAL CLOCKS PRECISION TIMING GENERATOR SYNC GENERATOR INTERNAL REGISTERS HD SHP SHD CLI Figure SL SCK SDI 05261-001 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax: 2005 Analog Devices, Inc. All rights reserved. AD9940 TABLE OF CONTENTS 3 Analog 4 Digital Specifications 5 Timing Specifications Slave Timing Mode 5 Absolute Maximum 6 Thermal Characteristics 6 ESD 6 Pin Configuration and Function 7 Data Bit Descriptions 9 Serial Interface Timing 12 0 Initial Version System Overview 13 Analog Front End 13 Precision Timing, High Speed Timing Generation 14 Timing 14 High Speed Clock 14 H-Driver and RG Outputs 16 HBLK Sequences 17 Application 19 Outline Dimensions 20 Ordering Guide 20 AD9940 SPECIFICATIONS Table Parameter TEMPERATURE RANGE Operating Storage MAXIMUM CLOCK RATE POWER SUPPLY VOLTAGE AVDD, TCVDD AFE, Timing Core OVDD Analog Buffer DVDD Digital HVDD H1 to H4 Drivers RGVDD RG Driver POWER DISSIPATION1 56 MHz, AFE supplies = V, HVDD = RGVDD = V, 70 pF, H1 to H4 Loading 56 MHz, AFE supplies = V, HVDD = RGVDD = V, 70 pF, H1 to H4 Loading 56 MHz, AFE supplies = V, no H or RG drivers 56 MHz, AFE supplies = V, no H or RG drivers Standby Mode Unit −25 −65 +150 1 The total power dissipated by the HVDD supply can be approximated using the following equation Total HVDD Power = CLOAD x HVDD x Pixel Frequency x HVDD Reducing the H-loading and/or using a lower HVDD supply reduces the power dissipation. AD9940 ANALOG SPECIFICATIONS fCLI = 56 MHz, AVDD = OVDD = DVDD = TCVDD = V, −25°C to +85°C, unless otherwise noted. Table Parameter CDS Gain Allowable CCD Reset Transient1 Maximum Input Range Before Saturation1 Maximum CCD Black Pixel Amplitude1 Peak Nonlinearity, 500 mV Input Signal Power Supply Rejection PSR ANALOG OUTPUTS2 Typical DIFFP Output Signal Range Typical DIFFN Output Signal Range Typical Common Mode Level Maximum Differential Output Voltage Swing Output Voltage Compliance Maximum Load Capacitance Minimum Load Resistance if required Min Typ Max 500 1 ±50 36 5,000 Unit Notes dB mV V p-p mV % FS dB Measured with step change on supply V corresponds to black level V corresponds to black level Midscale voltage where DIFFP = DIFFN Defined as DIFFP − DIFFN Limitation of output swing into external load Value for each output AD9941 CIN is < 24 pF Only use resistive loading if required by the differential receiver. Proper dc biasing should be used to be compatible with levels in Figure 3 1 Input signal characteristics are defined in Figure 2 Output signal characteristics are defined in Figure 05261-002 500mV TYP RESET TRANSIENT 50mV TYP OPTICAL BLACK PIXEL 850mV TYP INPUT SIGNAL RANGE Figure Input Signal Characteristics 1V MAX OUTPUT SIGNAL SWING, DIFFP AND DIFFN 2V p-p MAX DIFFERENTIAL SIGNAL, DIFFN ORDERING GUIDE Model Temperature Range AD9940BSTZ1 −25°C to +85°C AD9940BSTZRL1 −25°C to +85°C AD9940BCPZ1 −25°C to +85°C AD9940BCPZRL1 −25°C to +85°C Package Description 48-lead Low Profile Quad Flat Package [LQFP] 48-lead Low Profile Quad Flat Package [LQFP] 48-lead Frame Chip Scale Package [LFCSP_VQ] 48-lead Frame Chip Scale Package [LFCSP_VQ] 1 Z = Pb-free part. PIN 1 INDICATOR Package Option ST-48 ST-48 CP-48-1 CP-48-1 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

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High Speed, Correlated Double Sampler with Integrated Timing Driver AD9940
56 MSPS correlated double sampler CDS with 6 dB gain On-chip horizontal and RG timing driver Single-supply operation V min Precision Timing core with ns resolution at 56 MSPS Low power CMOS 105 mW at V 115 mW at V 48-lead LQFP and 48-lead LFCSP packages

Professional HDTV camcorders Professional/high end digital cameras Broadcast cameras Industrial high speed cameras High speed data-acquisition systems

The AD9940 is a high speed, correlated double sampler for high speed digital imaging applications. Integrated with a programmable timing driver using the Precision Timing core, the AD9940 features a 56 MHz CDS amplifier with 6 dB of fixed gain, an internal voltage reference supply, and timing control for all the high speed clocks necessary for CCD imaging systems. The Precision Timing core allows adjustment of high speed clocks with a resolution of ns. Output buffers are also included, providing drive strength for PCB traces and direct connection to an image signal processor such as the AD9941.

The AD9940 is ideal for applications that need to place the CDS and VGA/ADC circuits on separate PC boards. The fully differential outputs of the AD9940 provide good signal integrity when interfaced with the differential input AD9941. The AD9940 operates from a single V power supply, typically dissipates 105 mW excluding the H/RG drive current , and is packaged in 48-lead LQFP and 48-lead LFCSP packages.

CCDIN

AD9940

FUNCTIONAL BLOCK DIAGRAM

REFT REFB

VREF

DIFFN DIFFP

RG HL

H1 TO H4

HORIZONTAL

DRIVERS

INTERNAL CLOCKS

PRECISION TIMING

GENERATOR

SYNC GENERATOR

INTERNAL REGISTERS

HD SHP SHD CLI

Figure

SL SCK SDI
05261-001

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel:

Fax:
2005 Analog Devices, Inc. All rights reserved.

AD9940

TABLE OF CONTENTS
3 Analog 4 Digital Specifications 5 Timing Specifications Slave Timing Mode 5

Absolute Maximum 6 Thermal Characteristics 6 ESD 6

Pin Configuration and Function 7 Data Bit Descriptions 9 Serial Interface Timing 12
0 Initial Version

System Overview 13 Analog Front End 13

Precision Timing, High Speed Timing Generation 14 Timing 14 High Speed Clock 14 H-Driver and RG Outputs 16 HBLK Sequences 17

Application 19 Outline Dimensions 20
Ordering Guide 20

AD9940

SPECIFICATIONS

Table Parameter TEMPERATURE RANGE

Operating Storage MAXIMUM CLOCK RATE POWER SUPPLY VOLTAGE AVDD, TCVDD AFE, Timing Core OVDD Analog Buffer DVDD Digital HVDD H1 to H4 Drivers RGVDD RG Driver POWER DISSIPATION1 56 MHz, AFE supplies = V, HVDD = RGVDD = V, 70 pF, H1 to H4 Loading 56 MHz, AFE supplies = V, HVDD = RGVDD = V, 70 pF, H1 to H4 Loading 56 MHz, AFE supplies = V, no H or RG drivers 56 MHz, AFE supplies = V, no H or RG drivers Standby Mode

Unit
−25
−65
+150
1 The total power dissipated by the HVDD supply can be approximated using the following equation Total HVDD Power = CLOAD x HVDD x Pixel Frequency x HVDD Reducing the H-loading and/or using a lower HVDD supply reduces the power dissipation.

AD9940

ANALOG SPECIFICATIONS
fCLI = 56 MHz, AVDD = OVDD = DVDD = TCVDD = V, −25°C to +85°C, unless otherwise noted.

Table Parameter CDS

Gain Allowable CCD Reset Transient1 Maximum Input Range Before Saturation1 Maximum CCD Black Pixel Amplitude1 Peak Nonlinearity, 500 mV Input Signal Power Supply Rejection PSR ANALOG OUTPUTS2 Typical DIFFP Output Signal Range Typical DIFFN Output Signal Range Typical Common Mode Level Maximum Differential Output Voltage Swing Output Voltage Compliance Maximum Load Capacitance Minimum Load Resistance if required

Min Typ Max
500 1 ±50 36
5,000

Unit Notes
dB mV V p-p mV % FS dB

Measured with step change on supply

V corresponds to black level

V corresponds to black level

Midscale voltage where DIFFP = DIFFN

Defined as DIFFP − DIFFN

Limitation of output swing into external load

Value for each output AD9941 CIN is < 24 pF

Only use resistive loading if required by the
differential receiver. Proper dc biasing should
be used to be compatible with levels in Figure 3
1 Input signal characteristics are defined in Figure 2 Output signal characteristics are defined in Figure
05261-002
500mV TYP RESET TRANSIENT
50mV TYP

OPTICAL BLACK PIXEL
850mV TYP

INPUT SIGNAL RANGE

Figure Input Signal Characteristics
1V MAX OUTPUT SIGNAL SWING, DIFFP AND DIFFN
2V p-p MAX DIFFERENTIAL SIGNAL,

DIFFN
ORDERING GUIDE

Model

Temperature Range

AD9940BSTZ1
−25°C to +85°C

AD9940BSTZRL1
−25°C to +85°C

AD9940BCPZ1
−25°C to +85°C

AD9940BCPZRL1
−25°C to +85°C

Package Description 48-lead Low Profile Quad Flat Package [LQFP] 48-lead Low Profile Quad Flat Package [LQFP] 48-lead Frame Chip Scale Package [LFCSP_VQ] 48-lead Frame Chip Scale Package [LFCSP_VQ]
1 Z = Pb-free part.

PIN 1 INDICATOR

Package Option ST-48 ST-48 CP-48-1 CP-48-1
2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AD9940BSTZ Datasheet file may be downloaded here without warranties.

Datasheet ID: AD9940BSTZ 517794