AD9822JRSZRL

AD9822JRSZRL Datasheet

AD9822

Part	Datasheet
AD9822JRSZRL	AD9822JRSZRL (pdf)

Related Parts	Information
AD9822JRSZ	AD9822JRSZ

PDF Datasheet Preview
Complete 14-Bit CCD/CIS Signal Processor AD9822 14-bit 15 MSPS ADC No missing codes guaranteed 3-channel operation up to 15 MSPS 1-channel operation up to MSPS Correlated double sampling programmable gain ±350 mV programmable offset Input clamp circuitry Internal voltage reference Multiplexed byte-wide output 8 + 6 format 3-wire serial digital interface 3 V/5 V digital I/O compatibility 28-Lead SOIC or SSOP Low power CMOS 385 mW typ Power-down mode <1 mW Flatbed document scanners Film scanners Digital color copiers Multifunction peripherals The AD9822 is a complete analog signal processor for CCD imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of trilinear color CCD arrays. Each channel consists of an input clamp, correlated double sampler CDS , offset DAC, and programmable gain amplifier PGA multiplexed to a high performance 14-bit ADC. The CDS amplifiers may be disabled for use with sensors such as contact image sensors CIS and CMOS active pixel sensors, which do not require CDS. The 14-bit digital output is multiplexed into an 8-bit output word that is accessed using two read cycles. The internal registers are programmed through a 3-wire serial interface and provide adjustment of the gain, offset, and operating mode. The AD9822 operates from a single 5 V power supply, consumes 385 mW of power typically, and is packaged in a 28-lead SOIC or SSOP. FUNCTIONAL BLOCK DIAGRAM AVDD AVSS CAPT CAPB AVDD AVSS DRVDD DRVSS VINR VING VINB OFFSET 9-BIT DAC BAND GAP REFERENCE AD9822 3:1 MUX 14-BIT ADC 14:8 9-BIT DAC INPUT CLAMP BIAS 9-BIT DAC PGA 6 CONFIGURATION REGISTER MUX REGISTER RED GREEN BLUE RED GREEN BLUE GAIN REGISTERS OFFSET REGISTERS DIGITAL CONTROL INTERFACE CDSCLK1 CDSCLK2 ADCCLK Figure DOUT SCLK SLOAD SDATA 00623-001 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. 1-Channel CDS Mode 12 1-Channel SHA Mode 12 Internal Register 13 Circuit Operation 15 Analog Mode 15 External Input Coupling 15 Analog 16 Programmable Gain AmplifierS PGA 16 17 Circuit and Layout Recommendations 17 Outline Dimensions 18 Ordering Guide 18 AD9822 SPECIFICATIONS ANALOG SPECIFICATIONS TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, PGA gain = 1, unless otherwise noted. Table Parameter MAXIMUM CONVERSION RATE 3-Channel Mode with CDS 1-Channel Mode with CDS ACCURACY ENTIRE SIGNAL PATH ADC Resolution Integral Nonlinearity INL INL 6 MHz Differential Nonlinearity DNL DNL 6 MHz No Missing Codes No Missing Codes 6 MHz Offset Error Gain Error ANALOG INPUTS Input Signal Range1 Allowable Reset Transient1 Input Limits2 Input Capacitance Input Bias Current AMPLIFIERS PGA Gain at Minimum PGA Gain at Maximum PGA Gain Resolution2 PGA Gain Monotonicity Programmable Offset at Minimum Programmable Offset at Maximum Programmable Offset Resolution Programmable Offset Monotonicity NOISE AND CROSSTALK Total Output Noise PGA Minimum Total Output Noise PGA Maximum Channel-to-Channel Crosstalk 6 MHz POWER SUPPLY REJECTION AVDD = 5 V ± V DIFFERENTIAL VREF 25°C CAPT to CAPB 2 V ADC Full-Scale Range TEMPERATURE RANGE Operating Storage POWER SUPPLIES AVDD DRVDD OPERATING CURRENT AVDD DRVDD Power-Down Mode Current Min 15 14 −240 AVSS − 0 −65 −19 1 64 Guaranteed −350 +350 512 Guaranteed 73 4 150 +200 AVDD + +70 +150 Unit MSPS Bits LSB Bits mV % FSR V p-p V pF nA V/V/V Steps mV Steps LSB rms LSB rms LSB % FSR °C °C mA µA AD9822 Parameter POWER DISSIPATION 3-Channel Mode 3-Channel Mode 6 MHz 1-Channel Mode 1-Channel Mode 6 MHz 385 335 300 250 1 Linear input signal range is from 2 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9822’s input clamp. 450 410 00623-002 1V TYP RESET TRANSIENT 4V SET BY INPUT CLAMP 3V OPTION ALSO AVAILABLE 2V p-p MAX INPUT SIGNAL RANGE [ 2 The PGA gain is approximately linear-in-dB and follows the equation Gain = ] where G is the register value. See Figure 63 − G ORDERING GUIDE Model Temperature Range AD9822JR 0°C to 70°C AD9822JRRL 0°C to 70°C AD9822JRS 0°C to 70°C AD9822JRSRL 0°C to 70°C AD9822JRSZ1 0°C to 70°C AD9822JRSZRL1 0°C to 70°C Package Description 28-Lead SOIC 28-Lead SOIC 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP Package Options R-28 R-28 RS-28 RS-28 RS-28 RS-28 1 Z = Pb-free part. NOTES AD9822 AD9822 NOTES 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

PDF Datasheet Preview

Complete 14-Bit CCD/CIS Signal Processor

AD9822
14-bit 15 MSPS ADC No missing codes guaranteed 3-channel operation up to 15 MSPS 1-channel operation up to MSPS Correlated double sampling programmable gain ±350 mV programmable offset Input clamp circuitry Internal voltage reference Multiplexed byte-wide output 8 + 6 format 3-wire serial digital interface 3 V/5 V digital I/O compatibility 28-Lead SOIC or SSOP Low power CMOS 385 mW typ Power-down mode <1 mW

Flatbed document scanners Film scanners Digital color copiers Multifunction peripherals

The AD9822 is a complete analog signal processor for CCD imaging applications. It features a 3-channel architecture designed to sample and condition the outputs of trilinear color CCD arrays. Each channel consists of an input clamp, correlated double sampler CDS , offset DAC, and programmable gain amplifier PGA multiplexed to a high performance 14-bit ADC.

The CDS amplifiers may be disabled for use with sensors such as contact image sensors CIS and CMOS active pixel sensors, which do not require CDS.

The 14-bit digital output is multiplexed into an 8-bit output word that is accessed using two read cycles. The internal registers are programmed through a 3-wire serial interface and provide adjustment of the gain, offset, and operating mode.

The AD9822 operates from a single 5 V power supply, consumes 385 mW of power typically, and is packaged in a 28-lead SOIC or SSOP.

FUNCTIONAL BLOCK DIAGRAM

AVDD AVSS

CAPT

CAPB

AVDD

AVSS DRVDD DRVSS

VINR VING VINB OFFSET
9-BIT DAC

BAND GAP REFERENCE

AD9822
3:1 MUX
14-BIT ADC
14:8
9-BIT DAC

INPUT CLAMP

BIAS
9-BIT DAC

PGA 6

CONFIGURATION REGISTER

MUX REGISTER

RED GREEN BLUE

RED GREEN BLUE

GAIN REGISTERS

OFFSET REGISTERS

DIGITAL CONTROL INTERFACE

CDSCLK1 CDSCLK2

ADCCLK

Figure

DOUT

SCLK SLOAD SDATA
00623-001

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
1-Channel CDS Mode 12 1-Channel SHA Mode 12 Internal Register 13 Circuit Operation 15 Analog Mode 15 External Input Coupling 15 Analog 16 Programmable Gain AmplifierS PGA 16 17 Circuit and Layout Recommendations 17 Outline Dimensions 18 Ordering Guide 18

AD9822

SPECIFICATIONS

ANALOG SPECIFICATIONS

TMIN to TMAX, AVDD = 5 V, DRVDD = 5 V, CDS mode, fADCCLK = 15 MHz, fCDSCLK1 = fCDSCLK2 = 5 MHz, PGA gain = 1, unless otherwise noted.

Table Parameter MAXIMUM CONVERSION RATE
3-Channel Mode with CDS 1-Channel Mode with CDS ACCURACY ENTIRE SIGNAL PATH ADC Resolution Integral Nonlinearity INL

INL 6 MHz Differential Nonlinearity DNL

DNL 6 MHz No Missing Codes

No Missing Codes 6 MHz Offset Error Gain Error ANALOG INPUTS Input Signal Range1 Allowable Reset Transient1 Input Limits2 Input Capacitance Input Bias Current AMPLIFIERS PGA Gain at Minimum PGA Gain at Maximum PGA Gain Resolution2 PGA Gain Monotonicity Programmable Offset at Minimum Programmable Offset at Maximum Programmable Offset Resolution Programmable Offset Monotonicity NOISE AND CROSSTALK Total Output Noise PGA Minimum Total Output Noise PGA Maximum Channel-to-Channel Crosstalk 6 MHz POWER SUPPLY REJECTION AVDD = 5 V ± V DIFFERENTIAL VREF 25°C CAPT to CAPB 2 V ADC Full-Scale Range TEMPERATURE RANGE Operating Storage POWER SUPPLIES AVDD DRVDD OPERATING CURRENT AVDD DRVDD Power-Down Mode Current

Min 15
14 −240 AVSS −
0 −65
−19
1 64 Guaranteed −350 +350 512 Guaranteed
73 4 150
+200 AVDD +
+70 +150

Unit

MSPS

Bits LSB Bits mV % FSR

V p-p V pF nA

V/V/V Steps
mV Steps

LSB rms LSB rms LSB
% FSR
°C °C
mA µA

AD9822

Parameter POWER DISSIPATION
3-Channel Mode 3-Channel Mode 6 MHz
1-Channel Mode 1-Channel Mode 6 MHz
385 335 300 250
1 Linear input signal range is from 2 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9822’s input clamp.
450 410
00623-002
1V TYP RESET TRANSIENT
4V SET BY INPUT CLAMP 3V OPTION ALSO AVAILABLE 2V p-p MAX INPUT SIGNAL RANGE
[ 2 The PGA gain is approximately linear-in-dB and follows the equation Gain =
] where G is the register value. See Figure
63 − G
ORDERING GUIDE

Model

Temperature Range

AD9822JR
0°C to 70°C

AD9822JRRL
0°C to 70°C

AD9822JRS
0°C to 70°C

AD9822JRSRL
0°C to 70°C

AD9822JRSZ1
0°C to 70°C

AD9822JRSZRL1
0°C to 70°C

Package Description 28-Lead SOIC 28-Lead SOIC 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP 28-Lead SSOP

Package Options R-28 R-28 RS-28 RS-28 RS-28 RS-28
1 Z = Pb-free part.

NOTES

AD9822

AD9822 NOTES
2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

More datasheets: 278071055012833 | ELSF-505SYGWA/S530-E2 | FIN1002M5 | 5894S5;5;5;5 | 5894S7;7;7;7 | 5894S1;1;1;1 | 612NL | 612NML | 612NM | BB-BONE-AUDI-01

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AD9822JRSZRL Datasheet file may be downloaded here without warranties.

Datasheet ID: AD9822JRSZRL 517790