AD5680BRJZ-1REEL7

AD5680BRJZ-1REEL7 Datasheet

The AD5680, a member of the nanoDAC family, is a single, 18-bit buffered voltage-out digital-to-analog converter DAC that operates from a single V to V supply and is 18-bit monotonic.

Part	Datasheet
AD5680BRJZ-1REEL7	AD5680BRJZ-1REEL7 (pdf)

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Data Sheet Single 18-bit nanoDAC 18-bit monotonic 12-bit accuracy guaranteed Tiny 8-lead SOT-23 package Power-on reset to zero scale/midscale V to V power supply Serial interface Rail-to-rail operation SYNC interrupt facility Temperature range −40°C to +105°C Closed-loop process control Low bandwidth data acquisition systems Portable battery-powered instruments Gain and offset adjustment Precision setpoint control The AD5680, a member of the nanoDAC family, is a single, 18-bit buffered voltage-out digital-to-analog converter DAC that operates from a single V to V supply and is 18-bit monotonic. The AD5680 requires an external reference voltage to set the output range of the DAC. The part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V AD5680-1 or to midscale AD5680-2 and remains there until a valid write takes place. The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The power consumption is mW at 5 V. The AD5680 on-chip precision output amplifier allows rail-torail output swing to be achieved. For remote sensing applications, the output amplifier’s inverting input is available to the user. 5 V 18-Bit in a SOT-23 AD5680 FUNCTIONAL BLOCK DIAGRAM VREF POWER-ON RESET DAC REGISTER REF + 18-BIT DAC OUTPUT BUFFER VFB VOUT INPUT CONTROL LOGIC SYNC SCLK DIN Figure AD5680 05854-001 The AD5680 uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz, and is compatible with standard QSPI , MICROWIRE , and DSP interface standards. PRODUCT HIGHLIGHTS 18 bits of resolution. 12-bit accuracy guaranteed for 18-bit DAC. Available in an 8-lead SOT-23. Low power typically consumes mW at 5 V. Power-on reset to zero scale or to midscale. RELATED DEVICES DAC in SOT-23. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks arethe property of their respectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel Analog Devices, Inc. All rights reserved. Technical Support AD5680* PRODUCT PAGE QUICK LINKS Last Content Update 07/19/2017 COMPARABLE PARTS View a parametric search of comparable parts. EVALUATION KITS • AD5680DBZ Evaluation Board 0 Initial Version Data Sheet Output 11 Interpolator Architecture 11 Serial Interface 12 Input Shift Register 12 SYNC Interrupt 12 Power-On Reset 12 Microprocessor 13 Applications Information 14 Closed-Loop Applications 14 Filter 14 Choosing a Reference for the AD5680 15 Using a Reference as a Power Supply for the AD5680 16 Using the AD5680 with a Galvanically Isolated Interface 16 Power Supply Bypassing and Grounding 16 Outline Dimensions 17 Ordering Guide 17 Data Sheet AD5680 SPECIFICATIONS VDD = V to V RL = 2 kΩ to GND CL = 200 pF to GND VREF = VDD all specifications TMIN to TMAX, unless otherwise noted. Table Parameter STATIC PERFORMANCE2 Resolution Relative Accuracy Differential Nonlinearity3 Zero-Code Error Full-Scale Error Offset Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio OUTPUT CHARACTERISTICS3 Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Output Noise Spectral Density4 Output Noise Hz to 10 Hz 4 Total Harmonic Distortion THD 4 Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current4 REFERENCE INPUT Reference Current Reference Input Range5 Reference Input Impedance LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD Normal Mode VDD = V to V POWER EFFICIENCY IOUT/IDD B Grade1 Min Typ Max ±32 ±64 −1 ±10 −100 2 10 80 25 −80 5 30 ±2 3 325 450 Unit Conditions/Comments Bits LSB mV % FSR mV % FSR uV/°C ppm dB Measured in 50 Hz system bandwidth Measured in 300 Hz system bandwidth All 0s loaded to DAC register All 1s loaded to DAC register Of FSR/°C DAC code = midscale VDD = 5 V ± 10% V/us nF uV p-p dB nV-s nV-s Ω mA ¼ to scale change settling to ±8 LSB, RL = 2 kΩ 0 pF < CL < 200 pF ¼ to scale RL = ∞ RL = 2 kΩ DAC code = midscale, 10 kHz DAC code = midscale VREF = 2 V ± 300 mV p-p, f = 200 Hz 1 LSB change around major carry VDD = 5 V VREF = VDD = 5 V All digital inputs VDD = 5 V VDD = 5 V All digital inputs at 0 V or VDD DAC active and excluding load current VIH = VDD and VIL = GND ILOAD = 2 mA, VDD = 5 V 1 Temperature range for B version is −40°C to +105°C, typical at +25°C. 2 DC specifications tested with the outputs unloaded, unless otherwise stated. Linearity calculated using a reduced code range of 2048 to 3 Guaranteed by design and characterization not production tested. 4 Output unloaded. 5 Reference input range at ambient where maximum DNL specification is achievable. AD5680 Data Sheet TIMING CHARACTERISTICS All input signals are specified with tR = tF = 1 ns/V 10% to 90% of VDD and timed from a voltage level of VIL + VIH /2. See Figure VDD = V to V all specifications TMIN to TMAX, unless otherwise noted. Table ORDERING GUIDE Model1 AD5680BRJZ-1500RL7 AD5680BRJZ-1REEL7 AD5680BRJZ-2500RL7 AD5680BRJZ-2REEL7 AD5680BCPZ-1500RL7 AD5680BCPZ-1RL7 AD5680BCPZ-2500RL7 AD5680BCPZ-2RL7 EVAL-AD5680DBZ 1 Z = RoHS Compliant Part. PIN 1 INDEX AREA SEATING PLANE COMPLIANT TO JEDEC STANDARDS MO-178-BA Figure 8-Lead Small Outline Transistor Package [SOT-23] RJ-8 Dimensions shown in millimeters TOP VIEW BOTTOM VIEW PIN 1 CORNER C 45° COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-229-WEEC-2 Figure 8-Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Thin, Dual Lead CP-8-15 Dimensions shown in millimeters 02-23-2011-A Power-On Reset to Code Zero Midscale Zero Midscale Accuracy ±64 LSB INL ±64 LSB INL ±64 LSB INL ±64 LSB INL ±64 LSB INL ±64 LSB INL ±64 LSB INL ±64 LSB INL Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C Package Description 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead LFCSP 8-Lead LFCSP 8-Lead LFCSP 8-Lead LFCSP Evaluation Board Package Option RJ-8 RJ-8 RJ-8 RJ-8 CP-8-15 CP-8-15 CP-8-15 CP-8-15 Branding D3C D3D DLN DLP AD5680 NOTES Data Sheet Data Sheet NOTES AD5680 AD5680 NOTES Data Sheet Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05854-0-7/17 C

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Data Sheet

Single 18-bit nanoDAC 18-bit monotonic 12-bit accuracy guaranteed Tiny 8-lead SOT-23 package Power-on reset to zero scale/midscale V to V power supply Serial interface Rail-to-rail operation SYNC interrupt facility Temperature range −40°C to +105°C

Closed-loop process control Low bandwidth data acquisition systems Portable battery-powered instruments Gain and offset adjustment Precision setpoint control

The AD5680, a member of the nanoDAC family, is a single, 18-bit buffered voltage-out digital-to-analog converter DAC that operates from a single V to V supply and is 18-bit monotonic.

The AD5680 requires an external reference voltage to set the output range of the DAC. The part incorporates a power-on reset circuit that ensures the DAC output powers up to 0 V AD5680-1 or to midscale AD5680-2 and remains there until a valid write takes place.

The low power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The power consumption is mW at 5 V.

The AD5680 on-chip precision output amplifier allows rail-torail output swing to be achieved. For remote sensing applications, the output amplifier’s inverting input is available to the user.
5 V 18-Bit in a SOT-23 AD5680

FUNCTIONAL BLOCK DIAGRAM

VREF

POWER-ON RESET

DAC REGISTER

REF + 18-BIT DAC

OUTPUT BUFFER

VFB VOUT

INPUT CONTROL

LOGIC

SYNC SCLK DIN

Figure

AD5680
05854-001

The AD5680 uses a versatile 3-wire serial interface that operates at clock rates up to 30 MHz, and is compatible with standard QSPI , MICROWIRE , and DSP interface standards.

PRODUCT HIGHLIGHTS
18 bits of resolution. 12-bit accuracy guaranteed for 18-bit DAC. Available in an 8-lead SOT-23. Low power typically consumes mW at 5 V. Power-on reset to zero scale or to midscale.

RELATED DEVICES

DAC in SOT-23.

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks arethe property of their respectiveowners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel Analog Devices, Inc. All rights reserved.

Technical Support

AD5680* PRODUCT PAGE QUICK LINKS

Last Content Update 07/19/2017

COMPARABLE PARTS

View a parametric search of comparable parts.

EVALUATION KITS
• AD5680DBZ Evaluation Board
0 Initial Version

Data Sheet
Output 11 Interpolator Architecture 11 Serial Interface 12 Input Shift Register 12 SYNC Interrupt 12 Power-On Reset 12 Microprocessor 13 Applications Information 14 Closed-Loop Applications 14 Filter 14 Choosing a Reference for the AD5680 15 Using a Reference as a Power Supply for the AD5680 16 Using the AD5680 with a Galvanically Isolated Interface 16 Power Supply Bypassing and Grounding 16 Outline Dimensions 17 Ordering Guide 17

Data Sheet

AD5680

SPECIFICATIONS

VDD = V to V RL = 2 kΩ to GND CL = 200 pF to GND VREF = VDD all specifications TMIN to TMAX, unless otherwise noted.

Table

Parameter STATIC PERFORMANCE2

Resolution Relative Accuracy Differential Nonlinearity3

Zero-Code Error Full-Scale Error Offset Error Gain Error Zero-Code Error Drift Gain Temperature Coefficient DC Power Supply Rejection Ratio OUTPUT CHARACTERISTICS3 Output Voltage Range Output Voltage Settling Time

Slew Rate Capacitive Load Stability

Output Noise Spectral Density4 Output Noise Hz to 10 Hz 4 Total Harmonic Distortion THD 4 Digital-to-Analog Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current4 REFERENCE INPUT Reference Current Reference Input Range5 Reference Input Impedance LOGIC INPUTS3 Input Current VINL, Input Low Voltage VINH, Input High Voltage Pin Capacitance POWER REQUIREMENTS VDD IDD Normal Mode VDD = V to V POWER EFFICIENCY IOUT/IDD

B Grade1 Min Typ Max
±32 ±64
−1
±10
−100
2 10 80 25 −80 5 30
±2 3
325 450

Unit

Conditions/Comments

Bits LSB mV % FSR mV % FSR uV/°C ppm dB

Measured in 50 Hz system bandwidth Measured in 300 Hz system bandwidth All 0s loaded to DAC register All 1s loaded to DAC register

Of FSR/°C DAC code = midscale VDD = 5 V ± 10%

V/us nF uV p-p dB nV-s nV-s Ω mA
¼ to scale change settling to ±8 LSB, RL = 2 kΩ 0 pF < CL < 200 pF ¼ to scale RL = ∞ RL = 2 kΩ DAC code = midscale, 10 kHz DAC code = midscale VREF = 2 V ± 300 mV p-p, f = 200 Hz 1 LSB change around major carry

VDD = 5 V

VREF = VDD = 5 V

All digital inputs

VDD = 5 V

VDD = 5 V

All digital inputs at 0 V or VDD

DAC active and excluding load current

VIH = VDD and VIL = GND

ILOAD = 2 mA, VDD = 5 V
1 Temperature range for B version is −40°C to +105°C, typical at +25°C. 2 DC specifications tested with the outputs unloaded, unless otherwise stated. Linearity calculated using a reduced code range of 2048 to 3 Guaranteed by design and characterization not production tested. 4 Output unloaded. 5 Reference input range at ambient where maximum DNL specification is achievable.

AD5680

Data Sheet

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V 10% to 90% of VDD and timed from a voltage level of VIL + VIH /2. See Figure VDD = V to V all specifications TMIN to TMAX, unless otherwise noted.

Table
ORDERING GUIDE

Model1 AD5680BRJZ-1500RL7 AD5680BRJZ-1REEL7 AD5680BRJZ-2500RL7 AD5680BRJZ-2REEL7 AD5680BCPZ-1500RL7 AD5680BCPZ-1RL7 AD5680BCPZ-2500RL7 AD5680BCPZ-2RL7 EVAL-AD5680DBZ
1 Z = RoHS Compliant Part.

PIN 1 INDEX AREA

SEATING PLANE

COMPLIANT TO JEDEC STANDARDS MO-178-BA

Figure 8-Lead Small Outline Transistor Package [SOT-23] RJ-8

Dimensions shown in millimeters

TOP VIEW

BOTTOM VIEW

PIN 1 CORNER C 45°

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-229-WEEC-2

Figure 8-Lead Frame Chip Scale Package [LFCSP_WD] 3 mm x 3 mm Body, Very Thin, Dual Lead CP-8-15 Dimensions shown in millimeters
02-23-2011-A

Power-On Reset to Code Zero Midscale Zero Midscale

Accuracy ±64 LSB INL ±64 LSB INL ±64 LSB INL ±64 LSB INL ±64 LSB INL ±64 LSB INL ±64 LSB INL ±64 LSB INL

Temperature Range −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C −40°C to +105°C

Package Description 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead SOT-23 8-Lead LFCSP 8-Lead LFCSP 8-Lead LFCSP 8-Lead LFCSP Evaluation Board

Package Option RJ-8 RJ-8 RJ-8 RJ-8 CP-8-15 CP-8-15 CP-8-15 CP-8-15

Branding D3C D3D DLN DLP

AD5680 NOTES

Data Sheet

Data Sheet NOTES

AD5680

AD5680 NOTES

Data Sheet

Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

D05854-0-7/17 C

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Datasheet ID: AD5680BRJZ-1REEL7 517715