AS1161-BCCT

AS1161-BCCT Datasheet

AS1160/AS1161

Part	Datasheet
AS1161-BCCT	AS1161-BCCT (pdf)

Related Parts	Information
AS1160-BCCT	AS1160-BCCT

PDF Datasheet Preview
Datasheet AS1160/AS1161 20MHz - 66MHz, 10-Bit Bus, IEEE JTAG Compliant LVDS Serializer/Deserializer 1 General Description 2 Key Features The AS1160 serializer is designed to convert 10-bit wide parallel LVCMOS/LVTTL data bus signals into a single high-speed LVDS serial data stream with clock. The AS1161 deserializer transforms the high-speed LVDS serial data stream back into a 10-bit wide parallel data bus with recovered parallel clock. Both devices are compliant with IEEE Standard Test Access Port and Boundary Scan Architecture including the defined boundary-scan test logic and test access port consisting of Test Data Input, Test Data Out, and Test Mode Select, Test Clock, and Test Reset . The devices also feature an at-speed BIST mode which allows the interconnects between the serializer and deserializer to be verified at-speed. The single differential-pair data-path makes PCB design easier, and reduced cable/PCB-trace count and connector size significantly reduce cost. Since one output transmits clock and data bits serially, clock-to-data and datato-data skew are eliminated. Powerdown mode reduces supply current when both devices are idle. Both devices are available in a CTBGA 49-bumps pin package. ! Serial Bus LVDS Data Rate 660 Mbps 66MHz Clock ! 10-bit Parallel Interface ! Synchronization Mode and Lock Indicator ! Programmable Edge Trigger on Clock ! High Impedance on Rx Inputs during Poweroff ! Bus LVDS Serial Output Load 28Ω ! IEEE JTAG Compliant and At-Speed BIST Test Mode ! Clock Recovery from PLL Lock to Random Data Patterns ! Guaranteed Transition each Data Transfer Cycle ! Chipset Tx + Rx Power Consumption < 500 mW 66MHz ! Single Differential-Pair eliminates Multi-Channel Skew ! Flow-Through Pinout for Simple PCB Layout ! Small CTBGA 49-bumps Package 3 Applications The devices are ideal for cellular phone base stations, add drop muxes, digital cross-connects. DSLAMs, networkswitches and routers or backplane interconnect. Figure Block Diagrams DIN0:9 Input Latch TCKR/FN TCLK PLL Parallelto-Serial Timing & Control SYNC1 SYNC2 TDI TDO TMS TCK AS1160 IEEE Test Access Port DO- LVDS RI- Parallelto-Serial Output 10 Latch ROUT0:9 Timing & Control AS1161 Clock Recovery TRSTN Serializer Timing Requirements for TCLK 6 Serializer Switching Characteristics 6 Deserializer Electrical Characteristics Deserializer Timing Requirements for 8 Deserializer Switching Characteristics 8 Scan Circuitry Timing 9 7 Typical Operating Characteristics AS1160 10 8 Typical Operating Characteristics AS1161 11 9 Timing Diagrams 12 10 Detailed Description 19 Initialization Data 20 Resynchronization 21 Tri-State 21 11 Application Information 22 Power Considerations 22 Powering up the Deserializer 22 Transmitting Data 22 Noise Margin 23 Lock Loss Recovery 23 Hot Insertion 23 PCB Considerations 24 Transmission Media 24 Failsafe Biasing 25 Signal 25 JTAG Test Modes 26 SAMPLE/PRELOAD 26 EXTEST 26 IDCODE 26 RUNBIST 26 12 Package Drawings and Markings 27 13 Ordering 28 2 - 29 AS1160/AS1161 Datasheet - Pinout 4 Pinout Pin Assignments and Descriptions Figure AS1160 Pin Assignments Top View DGND N/C DIN0 SYNC1 AVDD N/C B1 DIN1 N/C SYNC2 AVDD AGND AVDD C1 C2 C3 C4 C5 C6 C7 DIN3 DGND DVDD N/C AGND PWDNN D1 D2 D3 D4 D5 D6 D7 DIN5 DIN2 DIN4 N/C DO- DEN DO+ DIN7 DIN6 TMS TCLK DVDD DGND AGND TDI DIN8 TCK DIN9 DGND N/C AGND G1 G2 G3 G4 G5 G6 G7 TDO TRSTNTCKR/FN DGND AVDD N/C N/C Table AS1160 Pin Descriptions Pin Number See Figure 2 Pin Name DIN0:DIN9 TCKR/FN DO+ DODEN PWDNN TCLK SYNC1, SYNC2 DVDD DGND AVDD AGND TDI TDO TMS TCK TRSTN N/C Description Data Input. LVTTL levels inputs. Data on these pins are loaded into a 10-bit input register. Transmit Clock Rising/Falling Strobe Select. LVTTL level input. Selects TCLK active edge for strobing of DINx data. 1 = Rising edge. 0 = Falling edge. + Serial Data Output. Non-inverting Bus LVDS differential output. - Serial Data Output. Inverting Bus LVDS differential output. Serial Data Output Enable. LVTTL level input. If DEN is set to logic low the Bus LVDS outputs are in tri-state condition. Powerdown. LVTTL level input. Driving this pin low shuts down the PLL, tri-states the outputs and puts the device into low power sleep mode. Transmit Clock. LVTTL level input. Input for 20MHz to 66MHz system clock. Synchronization. LVTTL level input. Assertion of SYNC high for at least 5 clock cycles to be transmit a synchronization signal SYNCPAT on the Bus LVDS serial output. Synchronization symbols continue to be sent if SYNCx continues to be asserted. SYNC1 and SYNC2 pins are combined through an OR gate. +3.0V to +3.6V Digital Circuit Power Supply. This is the supply for all digital circuitry. Digital Circuit Ground. GND reference point for the digital part of the AS1160. +3.0V to +3.6V Analog Power Supply PLL and Analog Circuits . AVDD and DVDD should be at the same potential and must not be more than 0.3V apart even on transient basis. Both supplys should be decoupled by a capacitor of typically 10nF. Analog Ground PLL and Analog Circuits . IEEE Test Data Input IEEE Test Data Output IEEE Test Mode Select Input IEEE Test Clock Input IEEE Test Reset Input No Connection. Leave open-circuit, do not connect these pins. 3 - 29 AS1160/AS1161 Datasheet - Pinout Figure AS1161 Pin Assignments Top View DGND N/C REFCLK AGND ROUT1 DGND DVDD AVDD AGND RCKR/FN ROUT2 DGND ROUT3 DVDD C1 C2 C3 C4 C5 C6 C7 RI- AVDD N/C ROUT0 DVDD ROUT4 D1 REN D2 D3 D4 D5 D6 D7 RI+ PWDNN N/C DVDD ROUT5 DGND LOCKN RCLK N/C DGND TCK TRSTN DGND AVDD AGND ROUT8 TDI ROUT6 G1 G2 G3 G4 G5 G6 G7 AVDD AGND DGND ROUT9 ROUT7 TDO TMS Table AS1161 Pin Descriptions Pin Number Pin Name Datasheet - Ordering Information 13 Ordering Information The devices are available as the standard products shown in Table Table Ordering Information Ordering Code AS1160-BCTT AS1161-BCTT Description Serializer Deserializer Delivery Form Tape and Reel Tape and Reel Package CTBGA 49-bumps CTBGA 49-bumps Note All products are RoHS compliant and Pb-free. Buy our products or get free samples online at ICdirect: For further information and requests, please contact us or find your local distributor at 28 - 29 AS1160/AS1161 Datasheet Copyrights Copyright 1997-2009, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies. Disclaimer Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services. Contact Information Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel +43 0 3136 500 0 Fax +43 0 3136 525 01 For Sales Offices, Distributors and Representatives, please visit: 29 - 29

PDF Datasheet Preview

Datasheet

AS1160/AS1161
20MHz - 66MHz, 10-Bit Bus, IEEE JTAG Compliant LVDS Serializer/Deserializer
1 General Description
2 Key Features

The AS1160 serializer is designed to convert 10-bit wide parallel LVCMOS/LVTTL data bus signals into a single high-speed LVDS serial data stream with clock. The AS1161 deserializer transforms the high-speed LVDS serial data stream back into a 10-bit wide parallel data bus with recovered parallel clock.

Both devices are compliant with IEEE Standard Test Access Port and Boundary Scan Architecture including the defined boundary-scan test logic and test access port consisting of Test Data Input, Test Data Out, and Test Mode Select, Test Clock, and Test Reset .

The devices also feature an at-speed BIST mode which allows the interconnects between the serializer and deserializer to be verified at-speed.

The single differential-pair data-path makes PCB design easier, and reduced cable/PCB-trace count and connector size significantly reduce cost. Since one output transmits clock and data bits serially, clock-to-data and datato-data skew are eliminated.

Powerdown mode reduces supply current when both devices are idle.

Both devices are available in a CTBGA 49-bumps pin package.
! Serial Bus LVDS Data Rate 660 Mbps 66MHz Clock
! 10-bit Parallel Interface ! Synchronization Mode and Lock Indicator ! Programmable Edge Trigger on Clock ! High Impedance on Rx Inputs during Poweroff ! Bus LVDS Serial Output Load 28Ω ! IEEE JTAG Compliant and At-Speed BIST

Test Mode ! Clock Recovery from PLL Lock to Random Data

Patterns ! Guaranteed Transition each Data Transfer Cycle ! Chipset Tx + Rx Power Consumption < 500 mW
66MHz ! Single Differential-Pair eliminates Multi-Channel

Skew ! Flow-Through Pinout for Simple PCB Layout ! Small CTBGA 49-bumps Package
3 Applications

The devices are ideal for cellular phone base stations, add drop muxes, digital cross-connects. DSLAMs, networkswitches and routers or backplane interconnect.

Figure Block Diagrams

DIN0:9

Input Latch

TCKR/FN

TCLK PLL

Parallelto-Serial

Timing & Control

SYNC1 SYNC2

TDI TDO TMS TCK

AS1160

IEEE Test Access

Port

DO- LVDS RI-

Parallelto-Serial

Output 10

Latch

ROUT0:9

Timing &

Control

AS1161

Clock Recovery

TRSTN
Serializer Timing Requirements for TCLK 6 Serializer Switching Characteristics 6 Deserializer Electrical Characteristics Deserializer Timing Requirements for 8 Deserializer Switching Characteristics 8 Scan Circuitry Timing 9 7 Typical Operating Characteristics AS1160 10 8 Typical Operating Characteristics AS1161 11 9 Timing Diagrams 12 10 Detailed Description 19 Initialization Data 20 Resynchronization 21 Tri-State 21 11 Application Information 22 Power Considerations 22 Powering up the Deserializer 22 Transmitting Data 22 Noise Margin 23 Lock Loss Recovery 23 Hot Insertion 23 PCB Considerations 24 Transmission Media 24 Failsafe Biasing 25 Signal 25 JTAG Test Modes 26 SAMPLE/PRELOAD 26 EXTEST 26 IDCODE 26 RUNBIST 26 12 Package Drawings and Markings 27 13 Ordering 28
2 - 29

AS1160/AS1161

Datasheet - Pinout
4 Pinout

Pin Assignments and Descriptions

Figure AS1160 Pin Assignments Top View

DGND N/C DIN0 SYNC1 AVDD N/C

B1 DIN1

N/C SYNC2 AVDD AGND AVDD

C1 C2 C3 C4 C5 C6 C7 DIN3 DGND DVDD N/C AGND PWDNN

D1 D2 D3 D4 D5 D6 D7 DIN5 DIN2 DIN4 N/C DO- DEN DO+

DIN7 DIN6 TMS TCLK DVDD DGND AGND

TDI DIN8 TCK DIN9 DGND N/C AGND

G1 G2 G3 G4 G5 G6 G7 TDO TRSTNTCKR/FN DGND AVDD N/C N/C

Table AS1160 Pin Descriptions

Pin Number See Figure 2

Pin Name DIN0:DIN9

TCKR/FN

DO+ DODEN

PWDNN TCLK

SYNC1, SYNC2

DVDD DGND

AVDD

AGND TDI TDO TMS TCK

TRSTN N/C

Description Data Input. LVTTL levels inputs. Data on these pins are loaded into a 10-bit input register. Transmit Clock Rising/Falling Strobe Select. LVTTL level input. Selects TCLK active edge for strobing of DINx data. 1 = Rising edge. 0 = Falling edge. + Serial Data Output. Non-inverting Bus LVDS differential output. - Serial Data Output. Inverting Bus LVDS differential output. Serial Data Output Enable. LVTTL level input. If DEN is set to logic low the Bus LVDS outputs are in tri-state condition. Powerdown. LVTTL level input. Driving this pin low shuts down the PLL, tri-states the outputs and puts the device into low power sleep mode. Transmit Clock. LVTTL level input. Input for 20MHz to 66MHz system clock. Synchronization. LVTTL level input. Assertion of SYNC high for at least 5 clock cycles to be transmit a synchronization signal SYNCPAT on the Bus LVDS serial output. Synchronization symbols continue to be sent if SYNCx continues to be asserted. SYNC1 and SYNC2 pins are combined through an OR gate. +3.0V to +3.6V Digital Circuit Power Supply. This is the supply for all digital circuitry. Digital Circuit Ground. GND reference point for the digital part of the AS1160. +3.0V to +3.6V Analog Power Supply PLL and Analog Circuits . AVDD and DVDD should be at the same potential and must not be more than 0.3V apart even on transient basis. Both supplys should be decoupled by a capacitor of typically 10nF. Analog Ground PLL and Analog Circuits . IEEE Test Data Input IEEE Test Data Output IEEE Test Mode Select Input IEEE Test Clock Input IEEE Test Reset Input No Connection. Leave open-circuit, do not connect these pins.
3 - 29

AS1160/AS1161

Datasheet - Pinout

Figure AS1161 Pin Assignments Top View

DGND N/C REFCLK AGND ROUT1 DGND DVDD

AVDD AGND RCKR/FN ROUT2 DGND ROUT3 DVDD

C1 C2 C3 C4 C5 C6 C7 RI- AVDD N/C ROUT0 DVDD ROUT4

D1 REN

D2 D3 D4 D5 D6 D7 RI+ PWDNN N/C DVDD ROUT5 DGND

LOCKN RCLK N/C DGND TCK TRSTN DGND

AVDD AGND ROUT8 TDI ROUT6

G1 G2 G3 G4 G5 G6 G7 AVDD AGND DGND ROUT9 ROUT7 TDO TMS

Table AS1161 Pin Descriptions

Pin Number Pin Name
Datasheet - Ordering Information
13 Ordering Information

The devices are available as the standard products shown in Table
Table Ordering Information Ordering Code AS1160-BCTT AS1161-BCTT

Description Serializer

Deserializer

Delivery Form Tape and Reel Tape and Reel

Package CTBGA 49-bumps CTBGA 49-bumps

Note All products are RoHS compliant and Pb-free. Buy our products or get free samples online at ICdirect:

For further information and requests, please contact us or find your local distributor at
28 - 29

AS1160/AS1161

Datasheet

Copyrights

Copyright 1997-2009, austriamicrosystems AG, Tobelbaderstrasse 30, 8141 Unterpremstaetten, Austria-Europe. Trademarks Registered All rights reserved. The material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. All products and companies mentioned are trademarks or registered trademarks of their respective companies.

Disclaimer

Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing in its Term of Sale. austriamicrosystems AG makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. austriamicrosystems AG reserves the right to change specifications and prices at any time and without notice. Therefore, prior to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information. This product is intended for use in normal commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard production flow, such as test flow or test location. The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However, austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the technical data herein. No obligation or liability to recipient or any third party shall arise or flow out of austriamicrosystems AG rendering of technical or other services.

Contact Information

Headquarters austriamicrosystems AG Tobelbaderstrasse 30 A-8141 Unterpremstaetten, Austria Tel +43 0 3136 500 0 Fax +43 0 3136 525 01

For Sales Offices, Distributors and Representatives, please visit:
29 - 29

More datasheets: 191-2811-050 | 191-2811-034 | 191-2811-020 | 191-2811-040 | 191-2811-037 | 191-2811-024 | 191-2811-025 | 191-2811-016 | 191-2811-060 | AS1160-BCCT

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AS1161-BCCT Datasheet file may be downloaded here without warranties.

Datasheet ID: AS1161-BCCT 519579