EPM3064ATI44-10NAE

EPM3064ATI44-10NAE Datasheet

EPM3032A

Part	Datasheet
EPM3064ATI44-10NAE	EPM3064ATI44-10NAE (pdf)

Related Parts	Information
EPM3032ATC44-10AA	EPM3032ATC44-10AA
EPM3256ATC144-10AA	EPM3256ATC144-10AA
EPM3128ATI144-10AA	EPM3128ATI144-10AA
EPM3064ATI44-10NAD	EPM3064ATI44-10NAD
EPM3064ATC44-4NAG	EPM3064ATC44-4NAG
EPM3064ATC44-10NAF	EPM3064ATC44-10NAF
EPM3064ATC100-10NA	EPM3064ATC100-10NA
EPM3032ATC44-10NAA	EPM3032ATC44-10NAA
EPM3032ATC44-10NAB	EPM3032ATC44-10NAB

PDF Datasheet Preview
June 2003, ver. MAX 3000A Programmable Logic Device Family Data Sheet Features... • CMOS programmable logic devices PLDs built on a architecture see Table 1 • 3.3-V in-system programmability ISP through the IEEE Std. Joint Test Action Group JTAG interface with advanced pin-locking capability ISP circuitry compliant with IEEE Std. 1532 • boundary-scan test BST circuitry compliant with IEEE Std. • Enhanced ISP features Enhanced ISP algorithm for faster programming ISP_Done bit to ensure complete programming Pull-up resistor on I/O pins during programming • PLDs ranging from 600 to 10,000 usable gates • logic delays with counter frequencies of up to MHz • MultiVoltTM I/O interface enabling the device core to run at V, while I/O pins are compatible with and logic levels • Pin counts ranging from 44 to 256 in a variety of thin quad flat pack TQFP , plastic quad flat pack PQFP , plastic chip carrier PLCC , and FineLine BGATM packages • support • Programmable interconnect array PIA continuous routing structure for fast, predictable performance • Industrial temperature range Table MAX 3000A Device Features Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD ns tSU ns tCO1 ns fCNT MHz EPM3032A 600 32 2 34 EPM3064A 1,250 64 4 66 Altera Corporation DS-MAX3000A-3.4 EPM3128A 2,500 128 EPM3256A 5,000 256 16 161 EPM3512A 10,000 512 32 208 MAX 3000A Programmable Logic Device Family Data Sheet ...and More Features • PCI compatible • architecture including programmable control • output option • Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls • Programmable mode for a power reduction of over 50% in each macrocell • Configurable expander distribution, allowing up to 32 product terms per macrocell • Programmable security bit for protection of proprietary designs • Enhanced architectural features, including: 6 or 10 or output enable signals Two global clock signals with optional inversion Enhanced interconnect resources for improved routability Programmable output control • Software design support and automatic provided by Altera’s development systems for PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations • Additional design entry and simulation support provided by EDIF 2 0 and 3 0 netlist files, library of parameterized modules LPM , Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest • Programming support with the Altera master programming unit MPU , MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from manufacturers and any tester that supports JamTM Standard Test and Programming Language STAPL Files .jam , Jam STAPL Byte-Code Files .jbc , or Serial Vector Format Files .svf Altera Corporation MAX 3000A Programmable Logic Device Family Data Sheet Table MAX 3000A Speed Grades Device Speed Grade EPM3032A EPM3064A EPM3128A

PDF Datasheet Preview

June 2003, ver.

MAX 3000A

Programmable Logic Device Family

Data Sheet

Features...
• CMOS programmable logic devices PLDs built on a architecture see Table 1
• 3.3-V in-system programmability ISP through the IEEE Std. Joint Test Action Group JTAG interface with advanced pin-locking capability ISP circuitry compliant with IEEE Std. 1532
• boundary-scan test BST circuitry compliant with IEEE Std.
• Enhanced ISP features Enhanced ISP algorithm for faster programming ISP_Done bit to ensure complete programming Pull-up resistor on I/O pins during programming
• PLDs ranging from 600 to 10,000 usable gates
• logic delays with counter frequencies of up to

MHz
• MultiVoltTM I/O interface enabling the device core to run at V,
while I/O pins are compatible with and logic levels
• Pin counts ranging from 44 to 256 in a variety of thin quad flat pack TQFP , plastic quad flat pack PQFP , plastic chip carrier PLCC , and FineLine BGATM packages
• support
• Programmable interconnect array PIA continuous routing structure for fast, predictable performance
• Industrial temperature range

Table MAX 3000A Device Features

Usable gates Macrocells Logic array blocks Maximum user I/O pins tPD ns tSU ns tCO1 ns fCNT MHz

EPM3032A
600 32 2 34

EPM3064A
1,250 64 4 66

Altera Corporation

DS-MAX3000A-3.4

EPM3128A
2,500 128

EPM3256A
5,000 256 16 161

EPM3512A
10,000 512 32 208

MAX 3000A Programmable Logic Device Family Data Sheet
...and More Features
• PCI compatible
• architecture including programmable control
• output option
• Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
• Programmable mode for a power reduction of over
50% in each macrocell
• Configurable expander distribution, allowing up to
32 product terms per macrocell
• Programmable security bit for protection of proprietary designs
• Enhanced architectural features, including:
6 or 10 or output enable signals Two global clock signals with optional inversion Enhanced interconnect resources for improved routability Programmable output control
• Software design support and automatic provided by Altera’s development systems for PCs and Sun SPARCstations, and HP 9000 Series 700/800 workstations
• Additional design entry and simulation support provided by EDIF 2 0 and 3 0 netlist files, library of parameterized modules LPM , Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
• Programming support with the Altera master programming unit MPU , MasterBlasterTM communications cable, ByteBlasterMVTM parallel port download cable, BitBlasterTM serial download cable as well as programming hardware from manufacturers and any tester that supports JamTM Standard Test and Programming Language STAPL Files .jam , Jam STAPL Byte-Code Files .jbc , or Serial Vector Format Files .svf

Altera Corporation

MAX 3000A Programmable Logic Device Family Data Sheet

Table MAX 3000A Speed Grades

Device

Speed Grade

EPM3032A

EPM3064A

EPM3128A

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Datasheet ID: EPM3064ATI44-10NAE 517150