MT48LC2M32B2TG-6A IT:J

MT48LC2M32B2TG-6A IT:J Datasheet

MT48LC2M32B2 512K x 32 x 4 Banks

Part	Datasheet
MT48LC2M32B2TG-6A IT:J	MT48LC2M32B2TG-6A IT:J (pdf)

Related Parts	Information
MT48LC2M32B2TG-6A:J	MT48LC2M32B2TG-6A:J
MT48LC2M32B2TG-6A IT:JTR	MT48LC2M32B2TG-6A IT:JTR

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SDR SDRAM MT48LC2M32B2 512K x 32 x 4 Banks 64Mb x32 SDRAM Features • PC100-compliant • Fully synchronous all signals registered on positive edge of system clock • Internal pipelined operation column address can be changed every clock cycle • Internal banks for hiding row access/precharge • Programmable burst lengths 1, 2, 4, 8, or full page • Auto precharge, includes concurrent auto precharge and auto refresh modes • Self refresh mode not available on AT devices • Auto refresh 64ms, 4096-cycle refresh commercial and industrial 16ms, 4096-cycle refresh automotive • LVTTL-compatible inputs and outputs • Single 3.3V ±0.3V power supply • Supports CAS latency CL of 1, 2, and 3 Options • Configuration 2 Meg x 32 512K x 32 x 4 banks • Plastic package OCPL1 86-pin TSOP II 400 mil standard 86-pin TSOP II 400 mil Pb-free 90-ball VFBGA 8mm x 13mm Pbfree • Timing cycle time 5ns 200 MHz 5.5ns 183 MHz 6ns 167 MHz 6ns 167 MHz 7ns 143 MHz • Operating temperature range Commercial to Industrial to Automotive to Marking 2M32B2 TG P B5 -5 -552 -6A3 -62 -72 None IT AT4 :G/:J Table 1 Key Timing Parameters CL = CAS READ latency Clock Speed Grade Frequency MHz Target tRCD-tRP-CL 3-3-3-3-3-3-3-3-3-3-3 tRCD ns 15 18 20 tRP ns 15 18 20 CL ns 15 18 21 Micron Technology, Inc. reserves the right to change products or specifications without notice. 1999 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. Table 2 Address Table Parameter Configuration Refresh count Row addressing Bank addressing Column addressing Table 3 64Mb x32 SDR Part Numbering Part Numbers MT48LC2M32B2TG MT48LC2M32B2P MT48LC2M32B2B51 Architecture 2 Meg x 32 2 Meg x 32 2 Meg x 32 Note FBGA Device Decoder: 64Mb x32 SDRAM Features 2 Meg x 32 512K x 32 x 4 banks 4K 2K A[10:0] 4 BA[1:0] 256 A[7:0] The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. Micron Technology, Inc. reserves the right to change products or specifications without notice. 1999 Micron Technology, Inc. All rights reserved. 64Mb x32 SDRAM Mode Register Table 18 Burst Definition Table Burst Length 2 4 8 Continuous Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 n = location Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1, Cn... Not supported For full-page accesses y = 2048 x4 y = 1024 x8 y = 512 x16 . For BL = 2, A11 x4 x8 or x16 select the block-of-two burst A0 selects the starting column within the block. For BL = 4, A11 x4 x8 or x16 select the block-of-four burst select the starting column within the block. For BL = 8, A11 x4 x8 or x16 select the block-of-eight burst select the starting column within the block. For a full-page burst, the full row is selected and A11 x4 x8 or x16 select the starting column. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. For BL = 1, A11 x4 x8 or x16 select the unique column to be accessed, and mode register bit M3 is ignored. Micron Technology, Inc. reserves the right to change products or specifications without notice. 1999 Micron Technology, Inc. All rights reserved. 64Mb x32 SDRAM Mode Register CAS Latency The CAS latency CL is the delay, in clock cycles, between the registration of a READ command and the availability of the output data. The latency can be set to two or three clocks. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data is valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ start driving after T1 and the data is valid by T2. Reserved states should not be used as unknown operation or incompatibility with future versions may result. Figure 14 CAS Latency Command DQ READ NOP tLZ NOP tOH DOUT CL = 2 Command READ NOP tLZ tAC CL = 3

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SDR SDRAM

MT48LC2M32B2 512K x 32 x 4 Banks
64Mb x32 SDRAM Features
• PC100-compliant
• Fully synchronous all signals registered on positive
edge of system clock
• Internal pipelined operation column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths 1, 2, 4, 8, or full page
• Auto precharge, includes concurrent auto precharge
and auto refresh modes
• Self refresh mode not available on AT devices
• Auto refresh
64ms, 4096-cycle refresh commercial and industrial
16ms, 4096-cycle refresh automotive
• LVTTL-compatible inputs and outputs
• Single 3.3V ±0.3V power supply
• Supports CAS latency CL of 1, 2, and 3

Options
• Configuration 2 Meg x 32 512K x 32 x 4 banks
• Plastic package OCPL1 86-pin TSOP II 400 mil standard 86-pin TSOP II 400 mil Pb-free 90-ball VFBGA 8mm x 13mm Pbfree
• Timing cycle time 5ns 200 MHz 5.5ns 183 MHz 6ns 167 MHz 6ns 167 MHz 7ns 143 MHz
• Operating temperature range Commercial to Industrial to Automotive to

Marking
2M32B2

TG P B5
-5 -552 -6A3 -62 -72

None IT AT4
:G/:J

Table 1 Key Timing Parameters

CL = CAS READ latency

Clock

Speed Grade

Frequency MHz

Target tRCD-tRP-CL 3-3-3-3-3-3-3-3-3-3-3
tRCD ns 15 18 20
tRP ns 15 18 20

CL ns 15 18 21

Micron Technology, Inc. reserves the right to change products or specifications without notice. 1999 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.

Table 2 Address Table

Parameter Configuration Refresh count Row addressing Bank addressing Column addressing

Table 3 64Mb x32 SDR Part Numbering

Part Numbers MT48LC2M32B2TG MT48LC2M32B2P MT48LC2M32B2B51

Architecture 2 Meg x 32 2 Meg x 32 2 Meg x 32

Note FBGA Device Decoder:
64Mb x32 SDRAM Features
2 Meg x 32 512K x 32 x 4 banks
4K 2K A[10:0] 4 BA[1:0] 256 A[7:0]
The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 1999 Micron Technology, Inc. All rights reserved.
64Mb x32 SDRAM Mode Register

Table 18 Burst Definition Table

Burst Length 2 4 8

Continuous

Starting Column Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2
0-1-2-3 1-0-3-2-3-0-1 3-2-1-0
0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
n = location

Cn, Cn + 1, Cn + 2, Cn + 3...Cn - 1, Cn...

Not supported

For full-page accesses y = 2048 x4 y = 1024 x8 y = 512 x16 .

For BL = 2, A11 x4 x8 or x16 select the block-of-two burst A0 selects the starting column within the block.

For BL = 4, A11 x4 x8 or x16 select the block-of-four burst select the starting column within the block.

For BL = 8, A11 x4 x8 or x16 select the block-of-eight burst select the starting column within the block.

For a full-page burst, the full row is selected and A11 x4 x8 or x16 select the starting column.

Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.

For BL = 1, A11 x4 x8 or x16 select the unique column to be accessed, and mode register bit M3 is ignored.

Micron Technology, Inc. reserves the right to change products or specifications without notice. 1999 Micron Technology, Inc. All rights reserved.
64Mb x32 SDRAM Mode Register

CAS Latency

The CAS latency CL is the delay, in clock cycles, between the registration of a READ command and the availability of the output data. The latency can be set to two or three clocks.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m. The DQ start driving as a result of the clock edge one cycle earlier n + m - 1 , and provided that the relevant access times are met, the data is valid by clock edge n + m. For example, assuming that the clock cycle time is such that all relevant access times are met, if a READ command is registered at T0 and the latency is programmed to two clocks, the DQ start driving after T1 and the data is valid by T2.

Reserved states should not be used as unknown operation or incompatibility with future versions may result.

Figure 14 CAS Latency

Command DQ

READ

NOP tLZ

NOP tOH

DOUT

CL = 2

Command

READ

NOP tLZ
tAC CL = 3

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Datasheet ID: MT48LC2M32B2TG-6A IT:J 516146