MT46V64M8CV-5B IT:J

MT46V64M8CV-5B IT:J Datasheet

MT46V128M4 32 Meg x 4 x 4 banks MT46V64M8 16 Meg x 8 x 4 banks MT46V32M16 8 Meg x 16 x 4 banks

Part	Datasheet
MT46V64M8CV-5B IT:J	MT46V64M8CV-5B IT:J (pdf)

Related Parts	Information
MT46V32M16TG-5B IT:JTR	MT46V32M16TG-5B IT:JTR
MT46V32M16TG-5B IT:J	MT46V32M16TG-5B IT:J
MT46V32M16CV-5B IT:J	MT46V32M16CV-5B IT:J

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512Mb x4, x8, x16 DDR SDRAM Features Double Data Rate DDR SDRAM MT46V128M4 32 Meg x 4 x 4 banks MT46V64M8 16 Meg x 8 x 4 banks MT46V32M16 8 Meg x 16 x 4 banks • VDD = 2.5V ±0.2V, VDDQ = 2.5V ±0.2V VDD = 2.6V ±0.1V, VDDQ = 2.6V ±0.1V DDR400 1 • Bidirectional data strobe DQS transmitted/ received with data, i.e., source-synchronous data capture x16 has two one per byte • Internal, pipelined double-data-rate DDR architecture two data accesses per clock cycle • Differential clock inputs CK and CK# • Commands entered on each positive CK edge • DQS edge-aligned with data for READs center- aligned with data for WRITEs • DLL to align DQ and DQS transitions with CK • Four internal banks for concurrent operation • Data mask DM for masking write data x16 has two one per byte • Programmable burst lengths 2, 4, or 8 • Auto refresh 64ms, 8192-cycle • Longer-lead TSOP for improved reliability OCPL • 2.5V I/O SSTL_2 compatible • Concurrent auto precharge option is supported • tRAS lockout supported tRAP = tRCD Options Marking • Configuration 128 Meg x 4 32 Meg x 4 x 4 banks 128M4 64 Meg x 8 16 Meg x 8 x 4 banks 64M8 32 Meg x 16 8 Meg x 16 x 4 banks 32M16 • Plastic package 66-pin TSOP 66-pin TSOP Pb-free 60-ball FBGA 10mm x 12.5mm 60-ball FBGA 10mm x 12.5mm Pb-free BN2 60-ball FBGA 8mm x 12.5mm 60-ball FBGA 8mm x 12.5mm Pb-free • Timing cycle time 5ns CL = 3 DDR400 6ns CL = DDR333 FBGA only 6ns CL = DDR333 TSOP only -6T2 • Self refresh Standard None Low-power self refresh • Temperature rating Commercial 0°C to +70°C None Industrial to +85°C x4, x8, x16 x4, x8, x16 The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table Table 36 Burst Definition Burst Length 2 4 Starting Column Address Order of Accesses Within a Burst Type = Sequential Type = Interleaved 0-1-0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 0-1-0-1-2-3 1-0-3-2-3-0-1 3-2-1-0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 Micron Technology, Inc., reserves the right to change products or specifications without notice. 2000 Micron Technology, Inc. All rights reserved. 512Mb x4, x8, x16 DDR SDRAM Operations CAS Latency CL The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, or 3 -5B only clocks, as shown in Figure Reserved states should not be used, as unknown operation or incompatibility with future versions may result. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 37 on page 60 indicates the operating frequencies at which each CL setting can be used. Figure 25 CAS Latency CK# CK Command T0 READ T1 NOP CL = 2 CK# CK Command T0 READ DQS DQ NOP CL = CK# CK Command T0 READ T1 NOP T2 NOP CL = 3 Note: Transitioning Data Don’t Care BL = 4 in the cases shown with nominal tAC, tDQSCK, and tDQSQ. Micron Technology, Inc., reserves the right to change products or specifications without notice. 2000 Micron Technology, Inc. All rights reserved. 512Mb x4, x8, x16 DDR SDRAM Operations Table 37 CAS Latency Speed -5B -6/-6T -75E -75Z -75 Allowable Operating Clock Frequency MHz

PDF Datasheet Preview

512Mb x4, x8, x16 DDR SDRAM Features

Double Data Rate DDR SDRAM

MT46V128M4 32 Meg x 4 x 4 banks MT46V64M8 16 Meg x 8 x 4 banks MT46V32M16 8 Meg x 16 x 4 banks
• VDD = 2.5V ±0.2V, VDDQ = 2.5V ±0.2V VDD = 2.6V ±0.1V, VDDQ = 2.6V ±0.1V DDR400 1
• Bidirectional data strobe DQS transmitted/ received with data, i.e., source-synchronous data capture x16 has two one per byte
• Internal, pipelined double-data-rate DDR architecture two data accesses per clock cycle
• Differential clock inputs CK and CK#
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask DM for masking write data
x16 has two one per byte
• Programmable burst lengths 2, 4, or 8
• Auto refresh
64ms, 8192-cycle
• Longer-lead TSOP for improved reliability OCPL
• 2.5V I/O SSTL_2 compatible
• Concurrent auto precharge option is supported
• tRAS lockout supported tRAP = tRCD

Options

Marking
• Configuration
128 Meg x 4 32 Meg x 4 x 4 banks
128M4
64 Meg x 8 16 Meg x 8 x 4 banks
64M8
32 Meg x 16 8 Meg x 16 x 4 banks
32M16
• Plastic package
66-pin TSOP
66-pin TSOP Pb-free
60-ball FBGA 10mm x 12.5mm
60-ball FBGA 10mm x 12.5mm Pb-free BN2
60-ball FBGA 8mm x 12.5mm
60-ball FBGA 8mm x 12.5mm Pb-free
• Timing cycle time
5ns CL = 3 DDR400
6ns CL = DDR333 FBGA only
6ns CL = DDR333 TSOP only
-6T2
• Self refresh

Standard

None

Low-power self refresh
• Temperature rating

Commercial 0°C to +70°C

None

Industrial to +85°C
x4, x8, x16
x4, x8, x16
The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address, as shown in Table

Table 36 Burst Definition

Burst Length 2 4

Starting Column Address

Order of Accesses Within a Burst

Type = Sequential

Type = Interleaved
0-1-0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6
0-1-0-1-2-3 1-0-3-2-3-0-1 3-2-1-0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2000 Micron Technology, Inc. All rights reserved.
512Mb x4, x8, x16 DDR SDRAM Operations

CAS Latency CL

The CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, or 3 -5B only clocks, as shown in Figure Reserved states should not be used, as unknown operation or incompatibility with future versions may result.

If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 37 on page 60 indicates the operating frequencies at which each CL setting can be used.

Figure 25 CAS Latency

CK# CK

Command

T0 READ

T1 NOP

CL = 2

CK# CK

Command

T0 READ

DQS DQ

NOP CL =

CK# CK

Command

T0 READ

T1 NOP

T2 NOP

CL = 3

Note:

Transitioning Data

Don’t Care

BL = 4 in the cases shown with nominal tAC, tDQSCK, and tDQSQ.

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2000 Micron Technology, Inc. All rights reserved.
512Mb x4, x8, x16 DDR SDRAM Operations

Table 37 CAS Latency

Speed -5B
-6/-6T -75E -75Z -75

Allowable Operating Clock Frequency MHz

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Datasheet ID: MT46V64M8CV-5B IT:J 516142