AS4C8M16D1-5TCNTR

AS4C8M16D1-5TCNTR Datasheet

128M DDR1 -AS4C8M16D1

Part	Datasheet
AS4C8M16D1-5TCNTR	AS4C8M16D1-5TCNTR (pdf)

Related Parts	Information
AS4C8M16D1-5TCN	AS4C8M16D1-5TCN
AS4C8M16D1-5TINTR	AS4C8M16D1-5TINTR
AS4C8M16D1-5TIN	AS4C8M16D1-5TIN

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128M DDR1 -AS4C8M16D1 Details Preliminary datasheet Add Part numbering system Date Feb 2009 May 2015 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL 650 610-6800 FAX 650 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential -1/65- 128M DDR1 -AS4C8M16D1 Confidential 8M x 16 DDR Synchronous DRAM SDRAM • Fast clock rate 200MHz • Differential Clock CK & CK input • Bi-directional DQS • DLL enable/disable by EMRS • Fully synchronous operation • Internal pipeline architecture • Four internal banks, 2M x 16-bit for each bank • Programmable Mode and Extended Mode registers - CAS Latency 2, 3 - Burst length 2, 4, 8 - Burst Type Sequential & Interleaved • Individual byte write mask control • DM Write Latency = 0 • Auto Refresh and Self Refresh • 4096 refresh cycles / 64ms • Operating temperature range - Commercial 0 ~ 70°C - Industrial -40 ~ 85°C • Precharge & active power down • Power supplies VDD & VDDQ = 2.5V  5% • Interface SSTL_2 I/O Interface • Package 66 Pin TSOP II, 0.65mm pin pitch - Pb free and Halogen free Overview The 128Mb DDR AS4C8M16D1 SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 128 Mbits. It is internally configured as a quad 2M x 16 DRAM with a synchronous interface all signals are registered on the positive edge of the clock signal, CK . Data outputs occur at both rising edges of CK and CK. Read and write accesses to the SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The DDR SDRAM provides programmable Read or Write burst lengths of 2, 4, or An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, The DDR SDRAM features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and high performance. Table 1.Ordering Information Part Number AS4C8M16D1-TCN AS4C8M16D1-5TIN Org Max Clock MHz 8M x 16 8M x 16 Temperature Temp Range Commercial 0 ~ 70°C Industrial -40 ~ 85°C Package 66pin TSOPII 66pin TSOPII T indicates TSOP II package C indicates Commercial temp. I indicates Industrial temp. N indicates lead free ROHS Confidential -2/65- 128M DDR1 -AS4C8M16D1 Figure Pin Assignment Top View VDDQ VSSQ VDDQ VSSQ VDDQ LDQS A10/AP DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 VDDQ VSSQ UDQS VREF Confidential -3/65- F igure Block Diagram DLL CLOCK BUFFER CS RAS CAS WE COMMAND DECODER 128M DDR1 -AS4C8M16D1 Row Decoder Table Burst Address ordering Burst Length Start Address A2 A1 A0 Sequential 0, 1, 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave 0, 1, 0, 1, 2, 3 1, 0, 3, 2, 3, 0, 1 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 • CAS Latency Field A6~A4 This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the following formula must be programmed into this field. tCAC min CAS Latency X tCK Table CAS Latency CAS Latency Reserved 2 clocks 3 clocks Reserved clocks Reserved Confidential -9/65- 128M DDR1 -AS4C8M16D1 • Test Mode field A8~A7 These two bits are used to enter the test mode and must be programmed to "00" in normal operation. Table Test Mode • BA0, BA1 Table MRS/EMRS Test Mode Normal mode DLL Reset Test mode A11 ~ A0 MRS Cycle Extended Functions EMRS Extended Mode Register Set EMRS The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore must be written after power up for proper operation. The extended mode register is written by asserting low on CS , RAS , CAS , and WE The state of A0, A2 ~ A5, A7 ~ A11and BA1 is written in the mode register in the same cycle as CS , RAS , CAS , and WE going low. The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for specific codes. Table Extended Mode Register Bitmap BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field RFU must be set to “0” DS1 RFU must be set to “0” DS0 DLL Extended Mode Register BA0 Mode 0 MRS 1 EMRS A6 A1 Drive Strength Comment Full Weak Reserved For Future 1 Matched impedance Output driver matches impedance A0 DLL 0 Enable 1 Disable Confidential -10/65- 128M DDR1 -AS4C8M16D1 Table Absolute Maximum Rating

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128M DDR1 -AS4C8M16D1

Details Preliminary datasheet

Add Part numbering system

Date Feb 2009 May 2015

Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL 650 610-6800 FAX 650 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice

Confidential
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128M DDR1 -AS4C8M16D1

Confidential
8M x 16 DDR Synchronous DRAM SDRAM
• Fast clock rate 200MHz
• Differential Clock CK & CK input
• Bi-directional DQS
• DLL enable/disable by EMRS
• Fully synchronous operation
• Internal pipeline architecture
• Four internal banks, 2M x 16-bit for each bank
• Programmable Mode and Extended Mode registers
- CAS Latency 2, 3 - Burst length 2, 4, 8 - Burst Type Sequential & Interleaved
• Individual byte write mask control
• DM Write Latency = 0
• Auto Refresh and Self Refresh
• 4096 refresh cycles / 64ms
• Operating temperature range - Commercial 0 ~ 70°C - Industrial -40 ~ 85°C
• Precharge & active power down
• Power supplies VDD & VDDQ = 2.5V  5%
• Interface SSTL_2 I/O Interface
• Package 66 Pin TSOP II, 0.65mm pin pitch - Pb free and Halogen free

Overview

The 128Mb DDR AS4C8M16D1 SDRAM is a high-speed CMOS double data rate synchronous DRAM containing 128 Mbits. It is internally configured as a quad 2M x 16 DRAM with a synchronous interface all signals are registered on the positive edge of the clock signal, CK . Data outputs occur at both rising edges of CK and CK.

Read and write accesses to the SDRAM are burst oriented accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The DDR SDRAM provides programmable Read or Write burst lengths of 2, 4, or An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. In addition, The DDR SDRAM features programmable DLL option. By having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and high performance.
Table 1.Ordering Information

Part Number AS4C8M16D1-TCN AS4C8M16D1-5TIN

Org Max Clock MHz
8M x 16
8M x 16

Temperature Temp Range Commercial 0 ~ 70°C

Industrial -40 ~ 85°C

Package 66pin TSOPII 66pin TSOPII

T indicates TSOP II package C indicates Commercial temp. I indicates Industrial temp. N indicates lead free ROHS

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128M DDR1 -AS4C8M16D1

Figure Pin Assignment Top View

VDDQ

VSSQ

VDDQ

VSSQ

VDDQ

LDQS

A10/AP

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

VDDQ

VSSQ

UDQS

VREF

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F igure Block Diagram

DLL CLOCK BUFFER

CS RAS CAS WE

COMMAND DECODER
128M DDR1 -AS4C8M16D1

Row Decoder
Table Burst Address ordering

Burst Length

Start Address

A2 A1 A0

Sequential
0, 1, 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6

Interleave
0, 1, 0, 1, 2, 3 1, 0, 3, 2, 3, 0, 1 3, 2, 1, 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
• CAS Latency Field A6~A4

This field specifies the number of clock cycles from the assertion of the Read command to the first read data. The minimum whole value of CAS Latency depends on the frequency of CK. The minimum whole value satisfying the following formula must be programmed into this field.
tCAC min CAS Latency X tCK

Table CAS Latency

CAS Latency Reserved 2 clocks 3 clocks Reserved clocks Reserved

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128M DDR1 -AS4C8M16D1
• Test Mode field A8~A7

These two bits are used to enter the test mode and must be programmed to "00" in normal operation.

Table Test Mode
• BA0, BA1

Table MRS/EMRS

Test Mode Normal mode

DLL Reset Test mode

A11 ~ A0 MRS Cycle Extended Functions EMRS

Extended Mode Register Set EMRS

The Extended Mode Register Set stores the data for enabling or disabling DLL and selecting output driver strength. The default value of the extended mode register is not defined, therefore must be written after power up for proper operation. The extended mode register is written by asserting low on CS , RAS , CAS , and WE The state of A0, A2 ~ A5, A7 ~ A11and BA1 is written in the mode register in the same cycle as CS , RAS , CAS , and WE going low. The DDR SDRAM should be in all bank precharge with CKE already high prior to writing into the extended mode register. A1 and A6 are used for setting driver strength to normal, weak or matched impedance. Two clock cycles are required to complete the write operation in the extended mode register. The mode register contents can be changed using the same command and clock cycle requirements during operation as long as all banks are in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. Refer to the table for specific codes.

Table Extended Mode Register Bitmap

BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Field

RFU must be set to “0” DS1 RFU must be set to “0” DS0 DLL Extended Mode Register

BA0 Mode 0 MRS 1 EMRS

A6 A1 Drive Strength

Comment

Full

Weak

Reserved For Future
1 Matched impedance Output driver matches impedance

A0 DLL 0 Enable 1 Disable

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128M DDR1 -AS4C8M16D1

Table Absolute Maximum Rating

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Datasheet ID: AS4C8M16D1-5TCNTR 516136