AK8859VQ

AK8859VQ Datasheet

[AK8859VQ]

Part	Datasheet
AK8859VQ	AK8859VQ (pdf)

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[AK8859VQ] AK8859VQ NTSC/PAL/SECAM Digital Video Decoder Overview The AK8859VQ is a single-chip digital video decoder for composite and S-video signals. Its output data is in YCbCr format and compliant with ITU-R BT.601 and ITU-R BT.656 standard interface. Its output also included HD / VD / FIELD and DVALID signals. Its operational temperature is between ranges of -40°C ~ 105°C. Microprocessor access is via I2C interface. • Decodes composite and S-Video signals NTSC-J, M, / PAL-B, D, G, H, I, N, Nc, M, 60 / SECAM • 2 input channel • 10-bit 27MHz ADC 2 channel • Digital PGA • Adaptive Automatic Gain Control AGC • Auto Color Control ACC • Image adjustment Contrast, Saturation, Brightness, Hue, Sharpness • Automatic input signal detection • Adaptive 2-D Y/C separation • Output data format ITU-R BT.601 YCbCr, 4:2:2, 8bit • Output interface ITU-R BT.656 4:2:2, 8bit parallel with EAV/SAV HD, VD, FIELD and DVALID signal timing output • Closed Caption signal decoding output via register • VBID CGMS-A signal decoding output via register • WSS signal decoding output via register • Macrovision signal detection Macrovision certification • Powerdown function • I2C control • Core supply voltage ~ 2.00V • I/O power supply ~ 3.60V • Operating temperature -40°C ~ 105°C • 48-pin LQFP package 7.0mm x 7.0mm Notice This device is protected by U.S. patent number 6,600,873 and other intellectual property rights. MS1178-E-00 AKM Confidential -1- 2010/04 [AK8859VQ] Contents Functional block 5 Pin 6 Pin function description 7 Pin function 7 Output pin state 9 Electrical 10 Absolute maximum ratings 10 Recommended operating conditions 10 DC characteristics 10 Analog characteristics Input range ADC Current consumption Crystal circuit 12 AC 13 External clock input 13 Clock output DTCLK 13 Output data 14 Power down 14 Power-on 15 I2C bus input 16 Timing 1 16 Timing 2 16 Functional 17 Functional Description 18 Analog 18 Clock mode 18 Analog clamp circuit 18 Input video signal categorization 20 Auto detection mode of input signal 21 Limiting auto detection candidates of input signal 22 VBI blanking interval data output 23 Output data code 23 V-bit 24 Slice function 24 VBI period decode 25 Output pin status 26 HD pin 27 VD_F, VAR and VARSUB pin output 27 Output pin polarity 28 Phase correction 28 No signal output 29 Active video data start position 29 VLOCK mechanism 30 Y/C 30 EAV/SAV code 30 Output 31 656 interface 31 MS1178-E-00 AKM Confidential -2- 2010/04 [AK8859VQ] Output timing signal diagram 32 Digital Pixel interpolator 33 Clock generation 34 Line-locked clock mode 34 Frame-locked clock 34 Fixed-clock 34 Auto transition 34 PGA Programmable Gain Amp 34 AGC Auto Gain Control 35 ACC Auto Color Control 36 Sharpness adjustment 36 Color Killer 36 Image quality adjustment 37 Contrast adjustment 37 Brightness adjustment 37 Color saturation 38 HUE adjustment 38 VBI information 39 Internal status 40 Input signal 40 Status of VLOCK mechanism 40 Interlace signal 40 Color killer 40 Clock 40 Luminance decode overflow 40 Color decode overflow 41 AGC 41 Macrovision signal detection 41 Auto detection result of input video signal 42 Device control interface 43 I2C bus SLAVE Address 43 I2C control sequence 43 Write sequence 43 Read 43 I2C General Call 43 Register 45 Register setting overview 47 Sub Address 0x00 “Input Channel Select Register 47 Sub Address 0x01 “Clamp Control Register R/W ” 48 Sub Address 0x02 “Input Video Standard Register R/W ” 49 Sub Address 0x03 “NDMODE Register R/W ” 50 Sub Address 0x04 “Output Format Register R/W ” 51 Sub Address 0x05 “Output Pin Control Register R/W ” 53 Sub Address 0x06 “Output Pin Polarity Set Register R/W ” 54 Sub Address 0x07 “Control 0 Register R/W ” 55 Sub Address 0x08 “Control 1 Register R/W ” 56 Sub Address 0x09 “Reserved Register R/W ” 56 Sub Address 0x0A “PGA1 Control Register R/W ” 57 Sub Address 0x0B “PGA2 Control Register R/W ” 57 Sub Address 0x0C “AGC and Color Control Register 58 Sub Address 0x0D “Contrast Control Register R/W ” 59 MS1178-E-00 AKM Confidential -3- 2010/04 [AK8859VQ] MS1178-E-00 AKM Confidential -4- 2010/04 [AK8859VQ] Functional block diagram TEST XTI XTO SELA SDA SCL PDN TEST LOGIC AIN1 AIN2 CLAMP VREF Clock Module 10-bit ADC 10-bit ADC Timing Controller Digital PLL

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[AK8859VQ]

AK8859VQ

NTSC/PAL/SECAM Digital Video Decoder

Overview

The AK8859VQ is a single-chip digital video decoder for composite and S-video signals. Its output data is in YCbCr format and compliant with ITU-R BT.601 and ITU-R BT.656 standard interface. Its output also included HD / VD / FIELD and DVALID signals. Its operational temperature is between ranges of -40°C ~ 105°C. Microprocessor access is via I2C interface.
• Decodes composite and S-Video signals NTSC-J, M, / PAL-B, D, G, H, I, N, Nc, M, 60 / SECAM
• 2 input channel
• 10-bit 27MHz ADC 2 channel
• Digital PGA
• Adaptive Automatic Gain Control AGC
• Auto Color Control ACC
• Image adjustment Contrast, Saturation, Brightness, Hue, Sharpness
• Automatic input signal detection
• Adaptive 2-D Y/C separation
• Output data format ITU-R BT.601 YCbCr, 4:2:2, 8bit
• Output interface ITU-R BT.656 4:2:2, 8bit parallel with EAV/SAV

HD, VD, FIELD and DVALID signal timing output
• Closed Caption signal decoding output via register
• VBID CGMS-A signal decoding output via register
• WSS signal decoding output via register
• Macrovision signal detection Macrovision certification
• Powerdown function
• I2C control
• Core supply voltage ~ 2.00V
• I/O power supply ~ 3.60V
• Operating temperature -40°C ~ 105°C
• 48-pin LQFP package 7.0mm x 7.0mm

Notice This device is protected by U.S. patent number 6,600,873 and other intellectual property rights.

MS1178-E-00

AKM Confidential -1-
2010/04
[AK8859VQ]

Contents

Functional block 5 Pin 6 Pin function description 7

Pin function 7 Output pin state 9 Electrical 10 Absolute maximum ratings 10 Recommended operating conditions 10 DC characteristics 10 Analog characteristics

Input range ADC Current consumption Crystal circuit 12 AC 13 External clock input 13 Clock output DTCLK 13 Output data 14 Power down 14 Power-on 15 I2C bus input 16 Timing 1 16 Timing 2 16 Functional 17 Functional Description 18 Analog 18 Clock mode 18 Analog clamp circuit 18 Input video signal categorization 20 Auto detection mode of input signal 21 Limiting auto detection candidates of input signal 22 VBI blanking interval data output 23 Output data code 23 V-bit 24 Slice function 24 VBI period decode 25 Output pin status 26 HD pin 27 VD_F, VAR and VARSUB pin output 27 Output pin polarity 28 Phase correction 28 No signal output 29 Active video data start position 29 VLOCK mechanism 30 Y/C 30 EAV/SAV code 30 Output 31 656 interface 31

MS1178-E-00

AKM Confidential -2-
2010/04
[AK8859VQ]

Output timing signal diagram 32 Digital Pixel interpolator 33 Clock generation 34

Line-locked clock mode 34 Frame-locked clock 34 Fixed-clock 34 Auto transition 34 PGA Programmable Gain Amp 34 AGC Auto Gain Control 35 ACC Auto Color Control 36 Sharpness adjustment 36 Color Killer 36 Image quality adjustment 37 Contrast adjustment 37 Brightness adjustment 37 Color saturation 38 HUE adjustment 38 VBI information 39 Internal status 40 Input signal 40 Status of VLOCK mechanism 40 Interlace signal 40 Color killer 40 Clock 40 Luminance decode overflow 40 Color decode overflow 41 AGC 41 Macrovision signal detection 41 Auto detection result of input video signal 42 Device control interface 43 I2C bus SLAVE Address 43 I2C control sequence 43 Write sequence 43 Read 43 I2C General Call 43 Register 45 Register setting overview 47 Sub Address 0x00 “Input Channel Select Register 47 Sub Address 0x01 “Clamp Control Register R/W ” 48 Sub Address 0x02 “Input Video Standard Register R/W ” 49 Sub Address 0x03 “NDMODE Register R/W ” 50 Sub Address 0x04 “Output Format Register R/W ” 51 Sub Address 0x05 “Output Pin Control Register R/W ” 53 Sub Address 0x06 “Output Pin Polarity Set Register R/W ” 54 Sub Address 0x07 “Control 0 Register R/W ” 55 Sub Address 0x08 “Control 1 Register R/W ” 56 Sub Address 0x09 “Reserved Register R/W ” 56 Sub Address 0x0A “PGA1 Control Register R/W ” 57 Sub Address 0x0B “PGA2 Control Register R/W ” 57 Sub Address 0x0C “AGC and Color Control Register 58 Sub Address 0x0D “Contrast Control Register R/W ” 59

MS1178-E-00

AKM Confidential -3-
2010/04
[AK8859VQ]

MS1178-E-00

AKM Confidential -4-
2010/04
[AK8859VQ]

Functional block diagram

TEST

XTI XTO

SELA SDA SCL PDN

TEST LOGIC

AIN1 AIN2

CLAMP

VREF

Clock Module
10-bit ADC 10-bit ADC

Timing Controller Digital PLL

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Datasheet ID: AK8859VQ 515927