74ACTQ827SCX
74ACTQ827SCX Datasheet
74ACTQ827 Quiet 10-Bit Buffer/Line Driver with 3-STATE Outputs
| Part | Datasheet |
|---|---|
74ACTQ827SCX |
74ACTQ827SCX (pdf) |
| Related Parts | Information |
|---|---|
|
74ACTQ827SC |
74ACTQ827SC |
74ACTQ827SPC |
74ACTQ827SPC |
| PDF Datasheet Preview |
|---|
| 74ACTQ827 Quiet 10-Bit Buffer/Line Driver with 3-STATE Outputs 74ACTQ827 Quiet 10-Bit Buffer/Line Driver with 3-STATE Outputs The ACTQ827 10-bit bus buffer provides high performance bus interface buffering for wide data/address paths or buses carrying parity. The 10-bit buffers have NOR output enables for maximum control flexibility. The ACTQ827 utilizes Fairchild Quiet technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet features output control and undershoot corrector in addition to a split ground bus for superior performance. s Guaranteed simultaneous switching noise level and dynamic threshold performance s Guaranteed pin-to-pin skew AC performance s Inputs and outputs on opposite sides of package allow easy interface with microprocessors s Improved latch-up immunity s Outputs source/sink 24 mA s TTL compatible inputs Ordering Code: Order Number Package Number Package Description 74ACTQ827SC M24B 24-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-013, Wide 74ACTQ827SPC N24C 24-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbols Connection Diagram IEEE/IEC Pin Descriptions Pin Names OE1, OE2 Description Output Enable Data Inputs Data Outputs Quiet FACT Quiet and are trademarks of Fairchild Semiconductor Corporation. 2000 Fairchild Semiconductor Corporation DS010687 74ACTQ827 Functional Description The ACTQ827 line driver is designed to be employed as memory address driver, clock driver and bus-oriented transmitter/receiver. The devices have 3-STATE outputs controlled by the Output Enable OE pins. When the OE is LOW, the device is transparent. When OE is HIGH, the device is in 3-STATE mode. Logic Diagram Function Table Inputs Outputs OE Dn Function H Transparent L Transparent H = HIGH Voltage Level L = LOW Voltage Level Z = HIGH Impedance X = Immaterial Z High Z Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 74ACTQ827 Absolute Maximum Ratings Note 1 Supply Voltage VCC DC Input Diode Current IIK VI = −0.5V VI = VCC + 0.5V DC Input Voltage VI DC Output Diode Current IOK VO = −0.5V VO = VCC + 0.5V DC Output Voltage VO DC Output Source or Sink Current IO DC VCC or Ground Current per Output Pin ICC or IGND Storage Temperature TSTG DC Latch-Up Source or Sink Current Junction Temperature TJ PDIP −0.5V to +7.0V −20 mA +20 mA −0.5V to VCC + 0.5V −20 mA +20 mA −0.5V to VCC + 0.5V ± 50 mA ± 50 mA −65°C to +150°C ± 300 mA 140°C Recommended Operating Conditions Supply Voltage VCC Input Voltage VI Output Voltage VO Operating Temperature TA Minimum Input Edge Rate VIN from 0.8V to 2.0V VCC 4.5V, 5.5V |
Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived 74ACTQ827SCX Datasheet file may be downloaded here without warranties.