AK8186B
AK8186B Datasheet
AK8186B
| Part | Datasheet |
|---|---|
AK8186B |
AK8186B (pdf) |
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| AK8186B Multi Output Clock Generator with Integrated 2.0GHz VCO AK8186B Low phase noise PLL RMS Jitter < 300fs On-chip VCO tunes from 1.75GHz to 2.25GHz External VCO/VCXO to 500MHz optional 1 differential or 2 single-ended Inputs Reference Switchover/Holdover modes Lock Detect 3 pairs of 1GHz LVPECL outputs 2 pairs of 800MHz LVDS outputs 8 250MHz CMOS outputs two per LVDS Serial control register interface 3.3V+/-5% Operating Voltage 2.5V-3.3V LVPECL Drive Voltage Operating Temperature -40 to +85°C Package 64-pin Leadless QFN Pb free Pin compatible with AD9516-3 The AK8186B is a multi-output clock generator with sub-ps jitter performance. The on-chip VCO tunes from 1.75GHz to 2.25GHz. The distribution section has three pairs of LVPECL buffers 6 outputs and two pairs of LVDS buffers 4 outputs /eight CMOS buffers two per LVDS outputs . The LVPECL outputs operate up to 1GHz, the LVDS outputs operate up to 800MHz and the CMOS outputs operate up to 250MHz. Each pair of the outputs has a divider. The LVPECL outputs have the division range of 1 to The LVDS and CMOS outputs have the 1 to The AK8186B operates at 3.3V and the LVPECL outputs are supplied independently from 2.375V to 3.6V. The operating temperature range is from -40 to +85°C. The part is available in a 9mm 9 mm 64-pin Leadless-QFN Pb free package. ORDERING INFORMATION Part Number AK8186B Marking AK8186B Shipping Packaging Tape and Reel Package 64-pin Leadless QFN Temperature Range -40 to 85 ℃ draft-E-02 Sep-2012 AK8186B BLOCK DIAGRAM REF_SEL RSET REFMON REFIN/REF1 REFIN/REF2 REF1 REF2 REFERENCE SWITCHOVER STATUS BYPASS DISTRIBUTION REFERENCE R DIVIDER P,P+1 PRESCALER N DIVIDER A/B COUNTER VCO STATUS VCO Divider DIVIDE by 2 to 6 Divider 0 DIVIDE by 1 to 32 Divider 1 DIVIDE by 1 to 32 CPRSET PLL REFERENCE LOCK DETECT PHASE FREQUENCY DETECTOR HOLD CHARGE PUMP LVPECL PD SYNC RESET ORDERING 1 - BLOCK 2 - PIN DESCRIPTION 4 - PIN - 4 PIN FUNCTION - 5 - ABSOLUTE MAXIMUM 7 - RECOMMENDED OPERATING CONDITIONS...................- 7 - ELECTRICAL 7 - POWER DISSIPATION - 7 - PLL CHARACTERISTICS - 8 - CLOCK INPUT CHARACTERISTICS - 9 - CLOCK OUTPUT CHARACTERISTICS - 10 - TIMING - 11 - CLOCK OUTPUT ADDITIVE PHASE NOISE DISTRIBUTION ONLY VCO DIVIDER NOT 12 - CLOCK OUTPUT PHASE NOISE INTERNAL VCO USED - 13 - CLOCK OUTPUT ABSOLUTE TIME JITTER CLOCK GENERATION USING INTERNAL VCO - 14 - CLOCK OUTPUT ABSOLUTE TIME JITTER CLOCK GENERATION USING EXTERNAL VCXO - 14 - CLOCK OUTPUT ADDITIVE TIME JITTER VCO DIVIDER NOT USED - CLOCK OUTPUT ADDITIVE TIME JITTER VCO DIVIDER USED - 15 - SERIAL CONTROL PORT - 16 - - 17 - LD, STATUS AND REFMON - 17 - TIMING 18 - THEORY OF OPERATION 19 - OPERATIONAL CONFIGURATIONS - 19 - Internal VCO and Clock Distribution - 19 - External VCO and Clock Distribution.................... - 20 - PLL - 21 - REFERENCE INPUT - 21 - REFERENCE - 22 - R DIVIDER REFERENCE DIVIDER ......................... - 22 - PHASE FREQUENCY DETECTOR PFD - 23 - CHARGE PUMP CP - 23 - On-Chip VCO - 23 - External VCO/VCXO - 24 - PLL EXTERNAL LOOP FILTER................................. - 24 - Figure 12 Example of External Loop Filter for the Internal VCO Figure 13 Example of External |
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