96D1-1G400NN-AD

96D1-1G400NN-AD Datasheet

Part	Datasheet
96D1-1G400NN-AD	96D1-1G400NN-AD (pdf)

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Product Model Product Issuing AD1U400A1G3 DDR-400 CL3 184-Pin U-DIMM 1GB 128M x 64-bits 2010/08/23 General Description Features Pin Assignment Pin Description Block Diagram Absolute Maximum Ratings DC Operating Condition AC Operating Condition AC Operation Test Condition IDD Specification and Conditions AC Characteristics System Characteristics Conditions Command Truth-Table Package Dimensions Approval By Jerry Chu 2010/08/23 Write By Vincent Chang 2010/08/23 Version - Initial release Changes - 2010/08/23 AD1U400A1G3 DDR-400 CL3 184-Pin U-DIMM 1GB 128M x 64-bits General The ADATA’s module is a 128Mx64 bits 1024MB DDR-400 CL3 -3-3-8 SDRAM memory module. The SPD is programmed to JEDEC standard latency 400Mbps timing of 3-3-3-8 at 2.6V. The module is composed of six-teen 64Mx8 bits CMOS DDR SDRAMs in TSOP 66pin package and one 2Kbit EEPROM in 8pin SOIC package on a 184pin printed circuit board. The module is a Dual In-line Memory Module and intended for mounting onto 184-pins edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. • Power supply Normal VDD & VDDQ = 2.6V ± 0.1V • All inputs and outputs are compatible with SSTL_2 interface • Programmable Read latency DDR400 3 Clock • Programmable Burst Length 2, 4, 8 with both sequential and interleave mode • Programmable Burst type sequential & interleave • Differential clock input CK, /CK • DLL aligns DQ and DQS transition with CK transition • Double-data-rate architecture two data transfers per clock cycle • Bidirectional data strobe [DQ] x4,x8 & [L U DQS] x16 • Programmable Burst type sequential & interleave • Auto & Self refresh, 7.8us refresh interval 8K/64ms refresh • Lead-free products are RoHS Compliant Front Side PIN Name PIN Name VREF DQ24 DQ25 DQS0 DQS3 DQ26 DQ27 DQS1 15 VDDQ 46 DQS8 /CK1 DQ10 DQ11 CKE0 22 VDDQ DQ16 DQ32 DQ17

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Product Model Product Issuing

AD1U400A1G3

DDR-400 CL3 184-Pin U-DIMM 1GB 128M x 64-bits
2010/08/23

General Description Features Pin Assignment Pin Description Block Diagram Absolute Maximum Ratings DC Operating Condition

AC Operating Condition AC Operation Test Condition IDD Specification and Conditions AC Characteristics System Characteristics Conditions Command Truth-Table Package Dimensions

Approval By

Jerry Chu 2010/08/23

Write By

Vincent Chang 2010/08/23

Version
- Initial release

Changes
- 2010/08/23

AD1U400A1G3 DDR-400 CL3 184-Pin U-DIMM
1GB 128M x 64-bits

General

The ADATA’s module is a 128Mx64 bits 1024MB DDR-400 CL3 -3-3-8 SDRAM memory module. The SPD is programmed to JEDEC standard latency 400Mbps timing of 3-3-3-8 at 2.6V. The module is composed of six-teen 64Mx8 bits CMOS DDR SDRAMs in TSOP 66pin package and one 2Kbit EEPROM in 8pin SOIC package on a 184pin printed circuit board.

The module is a Dual In-line Memory Module and intended for mounting onto 184-pins edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
• Power supply Normal VDD & VDDQ = 2.6V ± 0.1V
• All inputs and outputs are compatible with SSTL_2 interface
• Programmable Read latency DDR400 3 Clock
• Programmable Burst Length 2, 4, 8 with both sequential and interleave mode
• Programmable Burst type sequential & interleave
• Differential clock input CK, /CK
• DLL aligns DQ and DQS transition with CK transition
• Double-data-rate architecture two data transfers per clock cycle
• Bidirectional data strobe [DQ] x4,x8 & [L U DQS] x16
• Programmable Burst type sequential & interleave
• Auto & Self refresh, 7.8us refresh interval 8K/64ms refresh
• Lead-free products are RoHS Compliant

Front Side

PIN Name PIN

Name

VREF

DQ24

DQ25

DQS0

DQS3

DQ26

DQ27

DQS1
15 VDDQ 46

DQS8
/CK1

DQ10

DQ11

CKE0
22 VDDQ

DQ16

DQ32

DQ17

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Datasheet ID: 96D1-1G400NN-AD 515681